Display substrate and display panel

Abstract

A display substrate and a display panel are disclosed. The display substrate includes a display area, a light-transmitting area, and a transition area. The transition area surrounds the light-transmitting area, and the display area surrounds the transition area. The display substrate includes a base, a first conductive layer, at least two intermediate conductive layers, and a second conductive layer, which are sequentially stacked on one side of the base. Multiple data lines are sequentially arranged along a first direction and extend from the display area to the transition area. In any two adjacent data lines in the transition area, one is located in the first conductive layer, and the other is located in the second conductive layer. This display substrate can improve or eliminate vertical bright bar mura defects appearing in parts of the display area corresponding to the light-transmitting area and the transition area, thereby improving the display effect of the display substrate.

Description

Technical Field

[0001] This disclosure pertains to the field of display technology, specifically relating to a display substrate and a display panel. Background Technology

[0002] OLED (Organic Light-Emitting Diode) displays have attracted widespread attention due to their advantages such as self-illumination, low power consumption, thinness, flexibility, vibrant colors, high contrast, and fast response speed. Summary of the Invention

[0003] In a first aspect, embodiments of this disclosure provide a display substrate having a display area, a light-transmitting area, and a transition area, wherein the transition area surrounds the periphery of the light-transmitting area, and the display area surrounds the periphery of the transition area, wherein the display substrate includes a substrate.

[0004] A first conductive layer, at least two intermediate conductive layers, and a second conductive layer are sequentially stacked on one side of the substrate;

[0005] Multiple data lines are arranged sequentially along a first direction and extend from the display area to the transition area respectively;

[0006] In the transition region, one of any two adjacent data lines is located in the first conductive layer and the other is located in the second conductive layer.

[0007] In some embodiments, a plurality of first signal lines are further included, arranged sequentially along the first direction, and extending from the display area to the transition area respectively;

[0008] The first signal line is located in the intermediate conductive layer;

[0009] In the transition region, any two adjacent data lines correspond to at least one first signal line, the orthographic projection of the first signal line on the substrate is located between the orthographic projections of the two adjacent data lines on the substrate, and the orthographic projections of the first signal line and the data lines on the substrate do not overlap.

[0010] The signal on the first signal line is a constant voltage signal.

[0011] In some embodiments, in the transition region, the orthographic projection of the first signal line onto the substrate is located at the midpoint of the distance between the orthographic projections of two adjacent data lines onto the substrate.

[0012] In some embodiments, a plurality of first signal lines are further included, arranged sequentially along the first direction, and extending from the display area to the transition area respectively;

[0013] The first signal line is located in the intermediate conductive layer;

[0014] In the transition region, any two adjacent data lines correspond to at least one of the first signal lines, and the orthographic projections of the first signal line and one of the two adjacent data lines on the substrate at least partially overlap.

[0015] The signal on the first signal line is a constant voltage signal.

[0016] In some embodiments, in the transition region, the orthographic projections of the first signal line and one of the two adjacent data lines located in the second conductive layer on the substrate coincide;

[0017] Alternatively, the orthographic projection of the first signal line and one of the two adjacent data lines located in the first conductive layer on the substrate coincides.

[0018] In some embodiments, a first signal line is also included, extending from the display area to the transition area;

[0019] The first signal line is located in the intermediate conductive layer;

[0020] In the transition region, the orthogonal projection of the first signal line on the substrate covers the orthogonal projection of the plurality of data lines on the substrate.

[0021] In some embodiments, a first signal line is also included, extending from the display area to the transition area;

[0022] The first signal line is located in the intermediate conductive layer near the second conductive layer;

[0023] The portion of the first signal line located in the transition region includes a first solid portion and a first cutout portion.

[0024] The orthogonal projection of the data line located in the second conductive layer within the transition zone onto the substrate is located within the orthogonal projection of the first hollow portion onto the substrate.

[0025] The orthographic projection of the first physical portion onto the substrate covers the orthographic projection of the data line located on the first conductive layer onto the substrate.

[0026] In some embodiments, a first signal line is also included, extending from the display area to the transition area;

[0027] The first signal line is located in the intermediate conductive layer near the first conductive layer;

[0028] The portion of the first signal line located in the transition region includes a first solid portion and a first cutout portion.

[0029] The orthogonal projection of the data line located in the first conductive layer within the transition zone onto the substrate is located within the orthogonal projection of the first hollow portion onto the substrate.

[0030] The orthographic projection of the first solid portion on the substrate covers the orthographic projection of the data line located on the second conductive layer on the substrate.

[0031] In some embodiments, the intermediate conductive layer includes a first intermediate conductive layer and a second intermediate conductive layer, wherein the first intermediate conductive layer and the second intermediate conductive layer are stacked sequentially away from the substrate;

[0032] The display substrate also includes a first signal line and a second signal line, both extending from the display area to the transition area;

[0033] The first signal line is located in the first intermediate conductive layer;

[0034] The second signal line is located in the second intermediate conductive layer;

[0035] The portion of the first signal line located in the transition region includes a first solid portion and a first cutout portion.

[0036] The orthogonal projection of the data line located in the first conductive layer within the transition zone onto the substrate is located within the orthogonal projection of the first hollow portion onto the substrate.

[0037] The orthographic projection of the first solid portion onto the substrate covers the orthographic projection of the data line located on the second conductive layer onto the substrate;

[0038] The portion of the second signal line located in the transition region includes a second solid portion and a second cutout portion.

[0039] The orthographic projection of the data line located on the second conductive layer within the transition zone onto the substrate is located within the orthographic projection of the second cutout portion onto the substrate;

[0040] The orthographic projection of the second physical portion onto the substrate overlaps the orthographic projection of the data line located on the first conductive layer onto the substrate.

[0041] In some embodiments, the first signal line includes a first voltage signal line, a second voltage signal line, or a reset signal line.

[0042] In some embodiments, the second signal line includes a first voltage signal line, a second voltage signal line, or a reset signal line.

[0043] In some embodiments, the display area is further provided with a plurality of sub-pixels of different colors, which are located in the display area and arranged in an array.

[0044] The data cable includes a first segment and a second segment, the first segment being located in the display area and the second segment being located in the transition area; the first segment and the second segment are connected.

[0045] In any two adjacent columns of sub-pixels, the odd-numbered rows of the first column of sub-pixels are connected to the first segment of the first data line, and the even-numbered rows of sub-pixels are connected to the first segment of the second data line; in the second column of sub-pixels, the odd-numbered rows of sub-pixels are connected to the first segment of the third data line, and the even-numbered rows of sub-pixels are connected to the first segment of the fourth data line.

[0046] In the display area, the first segment of the first data line, the first segment of the second data line, the first segment of the third data line, and the first segment of the fourth data line are arranged sequentially along the first direction;

[0047] The first, second, third, and fourth second segments within the transition zone are arranged sequentially along the first direction;

[0048] The first and third second segments are located in the first conductive layer, and the second and fourth second segments are located in the second conductive layer;

[0049] The first segment of the first data line is connected to the first second segment;

[0050] The first segment of the second data line is connected to the second segment;

[0051] The first segment of the third data line is connected to the third second segment;

[0052] The first segment of the fourth data line is connected to the fourth second segment.

[0053] In some embodiments, in the transition region, the second segment of the data line connecting the sub-pixels of the same color in the same row is located on the same layer; the second segment of the data line connecting the sub-pixels of the same color in adjacent rows is located on different layers.

[0054] In some embodiments, the display area is further provided with a plurality of sub-pixels of different colors, which are located in the display area and arranged in an array.

[0055] The data cable includes a first segment and a second segment, the first segment being located in the display area and the second segment being located in the transition area; the first segment and the second segment are connected.

[0056] In any two adjacent columns of sub-pixels, the odd-numbered rows of the first column of sub-pixels are connected to the first segment of the first data line, and the even-numbered rows of sub-pixels are connected to the first segment of the second data line; in the second column of sub-pixels, the odd-numbered rows of sub-pixels are connected to the first segment of the third data line, and the even-numbered rows of sub-pixels are connected to the first segment of the fourth data line.

[0057] In the display area, the first segment of the first data line, the first segment of the second data line, the first segment of the third data line, and the first segment of the fourth data line are arranged sequentially along the first direction;

[0058] The first, second, third, and fourth second segments within the transition zone are arranged sequentially along the first direction;

[0059] The first and third second segments are located in the first conductive layer, and the second and fourth second segments are located in the second conductive layer;

[0060] It also includes a first jumper and a second jumper, located in the transition region and in different intermediate conductive layers; the first jumper and the second jumper spatially intersect.

[0061] The first segment of the first data line is connected to the first second segment;

[0062] The first segment of the second data line is connected to one end of the first jumper, and the other end of the first jumper is connected to the third second segment;

[0063] The first segment of the third data line is connected to one end of the second jumper, and the other end of the second jumper is connected to the second segment.

[0064] The first segment of the fourth data line is connected to the fourth second segment.

[0065] In some embodiments, in the transition region, the second segment of the data line connecting the sub-pixels of the same color in the same row is located on the same layer; the second segment of the data line connecting the sub-pixels of the same color in adjacent rows is located on the same layer.

[0066] In some embodiments, the sub-pixels of different colors include red sub-pixels, green sub-pixels, and blue sub-pixels;

[0067] The second segment of the data line connecting the red sub-pixels in adjacent rows is located in the second conductive layer;

[0068] The second segment of the data line connecting the blue sub-pixels in adjacent rows is located in the second conductive layer;

[0069] The second segment of the data line connecting the green sub-pixels in adjacent rows is located in the first conductive layer.

[0070] In some embodiments, the first segment of the plurality of data lines is located in the second conductive layer.

[0071] In some embodiments, a plurality of insulating layers are disposed between the first conductive layer and the second conductive layer.

[0072] The total thickness of the plurality of insulating layers ranges from 1.6 to 1.8 μm.

[0073] In some embodiments, a plurality of scan lines are further included, located in the display area and in the first conductive layer.

[0074] The multiple scan lines are arranged sequentially along the second direction.

[0075] The second direction intersects with the first direction.

[0076] Secondly, embodiments of this disclosure also provide a display panel, which includes the aforementioned display substrate.

[0077] The display substrate provided in this embodiment, by placing one of any two adjacent data lines in the transition region on the first conductive layer and the other on the second conductive layer, significantly increases the longitudinal distance between any two adjacent data lines in the transition region along the first direction perpendicular to the substrate direction. This significantly reduces the coupling capacitance between any two adjacent data lines along the first direction, thereby reducing signal interference between any two adjacent data lines in the transition region along the first direction. Ultimately, this improves or eliminates the vertical bright bar mura defect in the corresponding part of the display area in the light-transmitting area and the transition region, thus improving the display effect of the display substrate.

[0078] The display panel provided in this embodiment, by employing the above-described display substrate, can improve or eliminate vertical bright bar mura defects in the display area corresponding to the light-transmitting area and the transition area of ​​the display panel, thereby improving the display effect of the display panel. Attached Figure Description

[0079] The accompanying drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0080] Figure 1aThis is a schematic diagram of the opening and the vertical bright stripe mura around the opening in the OLED display panel in the related technology.

[0081] Figure 1b This is a schematic diagram of the driving method of the display substrate in related technologies.

[0082] Figure 1c This is a schematic diagram of the driving method of the display substrate in an embodiment of this disclosure.

[0083] Figure 1d This is a schematic diagram of the wire wrapping around the opening area of ​​an OLED display panel in related technologies.

[0084] Figure 1e For along Figure 1d A structural cross-sectional view of the AA' section line.

[0085] Figure 2a This is a top view schematic diagram of a display substrate according to an embodiment of the present disclosure.

[0086] Figure 2b for Figure 2a An enlarged schematic diagram of part B in the diagram.

[0087] Figure 2c For along Figure 2b A structural cross-sectional view of the CC' section line.

[0088] Figure 3a for Figure 2a Another enlarged schematic diagram of part B.

[0089] Figure 3b For along Figure 3a A structural cross-sectional view of the DD' section line.

[0090] Figure 4a for Figure 2a Another enlarged schematic diagram of part B.

[0091] Figure 4b For along Figure 4a A structural cross-sectional view of the EE' section line.

[0092] Figure 4c for Figure 2a Another enlarged schematic diagram of part B.

[0093] Figure 4d For along Figure 4c A structural cross-sectional view of the GG' section line.

[0094] Figure 4e for Figure 2a Another enlarged schematic diagram of part B.

[0095] Figure 4f For along Figure 4e A structural cross-sectional view of the HH' section line.

[0096] Figure 4g This is a cross-sectional schematic diagram of the transition region in the display substrate according to an embodiment of the present disclosure.

[0097] Figure 4h This is another cross-sectional schematic diagram of the transition region in the substrate according to an embodiment of the present disclosure.

[0098] Figure 4i This is another cross-sectional schematic diagram of the transition region in the substrate shown in an embodiment of the present disclosure.

[0099] Figure 5 for Figure 2a Another enlarged schematic diagram of part B.

[0100] Figure 6a for Figure 2a Another enlarged schematic diagram of part B.

[0101] Figure 6b For along Figure 6a A structural cross-sectional view of the FF' section line.

[0102] Figure 7 This is a top view schematic diagram of another display substrate in an embodiment of this disclosure.

[0103] Figure 8a This is a circuit diagram of a sub-pixel driving circuit according to an embodiment of the present disclosure.

[0104] Figure 8b For along Figure 2a A structural cross-sectional view of the II' section line.

[0105] Figure 8c For along Figure 2a Another structural cross-sectional view of the II' section line. Detailed Implementation

[0106] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, a display substrate and a display panel provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0107] Embodiments of this disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms and should not be construed as limited to the embodiments set forth in this disclosure. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this disclosure.

[0108] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas, but are not intended to be limiting.

[0109] Among related technologies, the adoption of Ramless ICs has become an important direction for cost reduction in OLED display products (costs can be reduced by approximately 30%). A Ramless IC is an OLED display driver integrated circuit (DDIC) that retains the Demura Ram (an important component of the DDIC, primarily used to compensate for uneven screen display), but removes the Display Ram (used to store image data transmitted by the system and retrieve data during display). This means it does not need to store display data but directly receives image data from the host and displays it. This design gives Ramless ICs advantages in power consumption and cost.

[0110] To accommodate the use of Ramless ICs in OLED displays, OLED panels require DDL (Dual data line) technology (i.e., one row of subpixels connects to two data lines) and multiplexer technology (such as mux1:4, i.e., one data channel connects to four data lines). Compared to traditional single data line technology (i.e., one row of subpixels connects to one data line), interference between dual data lines becomes more prominent, especially in the winding area around openings (such as camera openings) in the display area, where the data line winding density is high and the distance is close. When heavy-load images (such as a periodic graphic with two rows of subpixels at L255 grayscale and two rows of subpixels at L0 grayscale) are lit, the interference between data lines in the winding area around the opening is extremely aggravated, causing a significant difference in the display of subpixels in the corresponding column of the opening and its surrounding area compared to subpixels in other areas of the display area, resulting in vertical bright bars (mura) in the opening and its surrounding area. Figure 1a .

[0111] In related technologies, refer to Figure 1b This is a schematic diagram of the driving method of the display substrate in the related technology. In this method, multiple sub-pixels 8 are arranged in an array. A data line 5 (Data(i)) connects the sub-pixels in each row of a column. Scan lines 11 (Gate(n), Gate(n+1)) drive the sub-pixel 8 array row by row. It can be seen that if 4 columns of sub-pixels 8 are driven, two output ports of IC (data driver chip) are required.

[0112] In this embodiment, refer to Figure 1cThis is a schematic diagram of the driving method of the display substrate in this embodiment. In this method, multiple sub-pixels 8 are arranged in an array. One data line 5 (Data-odd(i)) connects to the sub-pixels in the odd-numbered rows of a column, and one data line 5 (Data-even(i)) connects to the sub-pixels in the even-numbered rows of a column. Scan lines 11 (Gate(n), Gate(n+1)) drive the sub-pixel array row by row. That is, driving the same number of sub-pixels 8 requires twice the number of data lines 5. With the help of a 1:4 multiplexer (MUX), it can be seen that if 4 columns of sub-pixels 8 are driven, only one output port of the IC (data driver chip) is needed. That is, driving 4 columns of sub-pixels 8 can be achieved by leading out one data line 5 from the output port. This can save ICs, reduce IC size, and reduce costs. In this embodiment, for the winding area around the opening, the data line 5 needs to be wound, which is more efficient than... Figure 1b In terms of the driving method, the data lines in the winding area around the opening are more dense in this embodiment. Since two adjacent data lines 5 drive sub-pixels 8 in different rows, the mutual influence will increase, resulting in poor display.

[0113] In related technologies, refer to Figure 1d and Figure 1e Under the DDL technology architecture, in the winding area 13 surrounding the aperture 12 of the OLED display panel, adjacent data lines 5 are respectively set on two adjacent and sequentially stacked conductive layers. For example, any two adjacent data lines 5 are set on SD1 layer 14 and SD2 layer 15, respectively. This winding scheme around the wire area 13 surrounding the aperture 12 is the same as the winding design of the traditional single data line scheme. Since the distance between the two adjacent conductive layers is relatively close, and the number and density of data lines 5 around the wire area 13 surrounding the aperture 12 under the DDL architecture are twice that of the single data line scheme, the spacing between adjacent data lines 5 is the smallest (about 0.6μm). Therefore, the interference effect between adjacent data lines 5 in the wire area 13 surrounding the aperture 12 becomes more prominent. Especially under heavy load screen conditions, the voltage amplitude difference between adjacent data lines 5 is large, and mutual interference is more likely to show obvious display differences, and the risk of vertical bright bar mura is more likely to occur.

[0114] In addition, in related technologies, refer to Figure 1d Scan lines 11 are also distributed around the line region 13 around the opening 12, such as the first scan line 111 and the second scan line 112 located in different conductive layers of the SD1 layer 14 near the substrate 1.

[0115] To address the problems in the related art, in a first aspect, embodiments of this disclosure provide a display substrate, referring to... Figure 2a , Figure 2b and Figure 2cThe display substrate has a display area 100, a light-transmitting area 101, and a transition area 102. The transition area 102 surrounds the light-transmitting area 101, and the display area 100 surrounds the transition area 102. The display substrate includes a substrate 1, a first conductive layer 2, at least two intermediate conductive layers 3, and a second conductive layer 4, which are stacked sequentially on one side of the substrate 1. Multiple data lines 5 are arranged sequentially along a first direction X and extend from the display area 100 to the transition area 102. In any two adjacent data lines 5 in the transition area 102, one is located in the first conductive layer 2, and the other is located in the second conductive layer 4.

[0116] The light-transmitting area 101 can be a through-hole that penetrates the thickness of the display substrate or a blind hole that does not penetrate the thickness of the display substrate. The light-transmitting area 101 only needs to allow light to pass through so that functional components (such as cameras, sensors, etc.) located below the display substrate at the position corresponding to the light-transmitting area 101 can work. The transition area 102 is the transition area between the display area 100 and the light-transmitting area 101. In order to allow the traces that originally passed through the light-transmitting area 101 to bypass the light-transmitting area 101, a winding design is required in the transition area 102.

[0117] In this embodiment, an insulating layer 6 is provided between any two adjacent conductive layers, that is, at least three insulating layers 6 are provided between the first conductive layer 2 and the second conductive layer 4. Compared with the related technology, where the two adjacent data lines around the opening are respectively set on two adjacent conductive layers, the longitudinal distance between any two adjacent data lines 5 along the first direction X in the transition region 102 along the direction perpendicular to the substrate 1 is significantly increased in this embodiment. This can significantly reduce the coupling capacitance between any two adjacent data lines 5 along the first direction X, thereby reducing the signal interference between any two adjacent data lines 5 along the first direction X in the transition region 102. Ultimately, this improves or eliminates the vertical bright bar mura defect in the part of the display area 100 corresponding to the light-transmitting area 101 and the transition region 102, and improves the display effect of the display substrate.

[0118] In some embodiments, a plurality of insulating layers 6 are disposed between the first conductive layer 2 and the second conductive layer 4, and the total thickness of the plurality of insulating layers 6 ranges from 1.6 to 1.8 μm.

[0119] In some embodiments, refer to Figure 3a and Figure 3b The display substrate also includes multiple first signal lines 7, arranged sequentially along the first direction X, and extending from the display area 100 to the transition area 102 respectively; the first signal lines 7 are located in the intermediate conductive layer 3; any two adjacent data lines 5 in the transition area 102 correspond to at least one first signal line 7, the orthographic projection of the first signal line 7 on the substrate 1 is located between the orthographic projections of the two adjacent data lines 5 on the substrate 1, and the orthographic projections of the first signal line 7 and the data lines 5 on the substrate 1 do not overlap; the signal on the first signal line 7 is a constant voltage signal.

[0120] With this configuration, the first signal line 7 can shield the interference between any adjacent data lines 5 along the first direction X of the transition area 102, thereby further reducing the coupling effect between any adjacent data lines 5 along the first direction X of the transition area 102, and further improving or eliminating the vertical bright bar mura defect in the part of the display area 100 corresponding to the light-transmitting area 101 and the transition area 102, thus improving the display effect of the display substrate.

[0121] In some embodiments, refer to Figure 3a and Figure 3b In the transition zone 102, the orthographic projection of the first signal line 7 onto the substrate 1 is located at the midpoint of the distance between the orthographic projections of two adjacent data lines 5 onto the substrate 1. With this configuration, the first signal line 7 can shield the interference between two adjacent data lines 5 in a 45° direction, thereby further reducing the coupling effect between the two adjacent data lines 5. This further improves or eliminates the vertical bright bar mura defect appearing in the corresponding portion of the display area 100 in the light-transmitting zone 101 and the transition zone 102, thus enhancing the display effect of the display substrate.

[0122] In some embodiments, refer to Figure 4a and Figure 4b The display substrate also includes multiple first signal lines 7, which are arranged sequentially along the first direction X and extend from the display area 100 to the transition area 102 respectively; the first signal lines 7 are located in the intermediate conductive layer 3; any two adjacent data lines 5 in the transition area 102 correspond to at least one first signal line 7, and the orthographic projection of the first signal line 7 and one of the two adjacent data lines 5 on the substrate 1 at least partially overlaps; the signal on the first signal line 7 is a constant voltage signal.

[0123] Wherein, the orthographic projection of the first signal line 7 and one of the two adjacent data lines 5 on the substrate 1 at least partially overlaps means that at least part of the line width of the first signal line 7 and one of the data lines 5 overlaps.

[0124] This configuration reduces the load difference between any two adjacent data lines 5 in the transition zone 102, preventing significant differences in signals on adjacent data lines 5 due to large load differences. This improves or avoids horizontal stripe defects in the corresponding display areas 100 of the light-transmitting area 101 and the transition zone 102. The principle is that the orthographic projections of the first signal line 7 and one of the data lines 5 on the substrate 1 at least partially overlap, increasing the coupling capacitance between them. This increases the load on the data line 5 that overlaps with the first signal line 7, thereby reducing the load difference between two adjacent data lines 5.

[0125] In some embodiments, refer to Figure 4a and Figure 4bIn the transition region 102, the orthographic projections of the first signal line 7 and one of the two adjacent data lines 5 located in the second conductive layer 4 on the substrate 1 coincide. This configuration increases the capacitance of the data line 5 located in the second conductive layer 4, thereby increasing the load of the data line 5 located in the second conductive layer 4 that overlaps with the first signal line 7, and thus reducing the load difference between the two adjacent data lines 5.

[0126] In some embodiments, refer to Figure 4c and Figure 4d In the transition region 102, the orthographic projections of the first signal line 7 and one of the two adjacent data lines 5 located in the first conductive layer 2 on the substrate 1 coincide. This configuration increases the capacitance of the data line 5 located in the first conductive layer 2, thereby increasing the load of the data line 5 located in the first conductive layer 2 that overlaps with the first signal line 7, and thus reducing the load difference between the two adjacent data lines 5.

[0127] In some embodiments, refer to Figure 4e and Figure 4f The display substrate also includes a first signal line 7 extending from the display area 100 to the transition area 102; the first signal line 7 is located in the intermediate conductive layer 3; the orthographic projection of the first signal line 7 on the substrate 1 in the transition area 102 covers the orthographic projection of multiple data lines 5 on the substrate 1. With this configuration, the first signal line 7 can better shield the interference between any adjacent data lines 5 along the first direction X in the transition area 102, thereby further reducing the coupling effect between any adjacent data lines 5 along the first direction X in the transition area 102, and further improving or eliminating the vertical bright bar mura defect in the part of the display area 100 corresponding to the light-transmitting area 101 and the transition area 102; however, in this scheme, the overall load of the data lines 5 in the transition area 102 is increased by the first signal line 7.

[0128] In some embodiments, refer to Figure 4g The display substrate also includes a first signal line 7 extending from the display area 100 to the transition area 102; the first signal line 7 is located in the intermediate conductive layer 3 near the second conductive layer 4; the portion of the first signal line 7 located in the transition area 102 includes a first solid portion 71 and a first cutout portion 72, and the orthographic projection of the data line 5 located in the second conductive layer 4 in the transition area 102 on the substrate 1 is located within the orthographic projection of the first cutout portion 72 on the substrate 1; the orthographic projection of the first solid portion 71 on the substrate 1 covers the orthographic projection of the data line 5 located in the first conductive layer 2 on the substrate 1.

[0129] Figure 4gIn this embodiment, the orthographic projections of the first cutout portion 72 and the data line 5 located on the second conductive layer 4 onto the substrate 1 can coincide. The first cutout portion 72 is formed by hollowing out the portion of the first signal line 7 located in the transition region 102, and the first solid portion 71 can cover the areas within the transition region 102 other than the data line 5 located on the second conductive layer 4. With this configuration, the first signal line 7 can shield the data signal on the data line 5 located on the first conductive layer 2 within the transition region 102, thereby reducing crosstalk between the data line 5 located on the first conductive layer 2 and the data line 5 located on the second conductive layer 4, and thus improving or eliminating the vertical bright bar mura defect appearing in the corresponding portion of the display area 100 of the light-transmitting area 101 and the transition region 102.

[0130] In some embodiments, refer to Figure 4h The display substrate also includes a first signal line 7 extending from the display area 100 to the transition area 102; the first signal line 7 is located in the intermediate conductive layer 3 near the first conductive layer 2; the portion of the first signal line 7 located in the transition area 102 includes a first solid portion 71 and a first cutout portion 72, and the orthographic projection of the data line 5 located in the first conductive layer 2 on the substrate 1 within the transition area 102 is located within the orthographic projection of the first cutout portion 72 on the substrate 1; the orthographic projection of the first solid portion 71 on the substrate 1 covers the orthographic projection of the data line 5 located in the second conductive layer 4 on the substrate 1.

[0131] Figure 4h In this embodiment, the first cutout portion 72 and the orthographic projection of the data line 5 located on the first conductive layer 2 onto the substrate 1 can coincide. The first cutout portion 72 is formed by hollowing out the portion of the first signal line 7 located in the transition region 102, and the first solid portion 71 can cover the other areas within the transition region 102 except for the data line 5 located on the first conductive layer 2. With this configuration, the first signal line 7 can shield the data signal on the data line 5 located on the second conductive layer 4 within the transition region 102, thereby reducing crosstalk between the data line 5 located on the second conductive layer 4 and the data line 5 located on the first conductive layer 2, and thus improving or eliminating the vertical bright bar mura defect appearing in the corresponding portion of the display area 100 of the light-transmitting area 101 and the transition region 102.

[0132] In some embodiments, refer to Figure 4iThe intermediate conductive layer 3 includes a first intermediate conductive layer 31 and a second intermediate conductive layer 32, which are stacked sequentially away from the substrate 1. The display substrate also includes a first signal line 7 and a second signal line 16, both extending from the display area 100 to the transition area 102. The first signal line 7 is located in the first intermediate conductive layer 31, and the second signal line 16 is located in the second intermediate conductive layer 32. The portion of the first signal line 7 located in the transition area 102 includes a first solid portion 71 and a first hollow portion 72. The data line 5 located in the first conductive layer 2 within the transition area 102 is on the substrate 1. The orthographic projection of the data line 5 located on the substrate 1 is located within the orthographic projection of the first cutout portion 72 on the substrate 1; the orthographic projection of the first solid portion 71 on the substrate 1 covers the orthographic projection of the data line 5 located on the second conductive layer 4 on the substrate 1; the portion of the second signal line 16 located in the transition region 102 includes the second solid portion 161 and the second cutout portion 162, and the orthographic projection of the data line 5 located on the substrate 1 in the transition region 102 is located within the orthographic projection of the second cutout portion 162 on the substrate 1; the orthographic projection of the second solid portion 161 on the substrate 1 covers the orthographic projection of the data line 5 located on the first conductive layer 2 on the substrate 1.

[0133] Figure 4i In this embodiment, the first cutout portion 72 and the orthographic projection of the data line 5 located in the first conductive layer 2 onto the substrate 1 can coincide; the second cutout portion 162 and the orthographic projection of the data line 5 located in the second conductive layer 4 onto the substrate 1 can coincide. The first cutout portion 72 is formed by cutting out a portion of the first signal line 7 located in the transition region 102, and the first solid portion 71 can cover the other areas within the transition region 102 except for the data line 5 located in the first conductive layer 2. The second cutout portion 162 is formed by cutting out a portion of the second signal line 16 located in the transition region 102, and the second solid portion 161 can cover the other areas within the transition region 102 except for the data line 5 located in the second conductive layer 4. With this configuration, a double-layer shielding of the first signal line 7 and the second signal line 16 is formed between the data line 5 located in the first conductive layer 2 and the data line 5 located in the second conductive layer 4. The shielding of the first signal line 7 and the second signal line 16 can complement each other, thereby further reducing crosstalk between the data line 5 located in the first conductive layer 2 and the data line 5 located in the second conductive layer 4. At the same time, it can also reduce the load on the data line 5 located in the first conductive layer 2 and the load on the data line 5 located in the second conductive layer 4.

[0134] In some embodiments, the first signal line 7 includes a first voltage signal line, a second voltage signal line, or a reset signal line. The first voltage signal line is, for example, a VDD signal line; the second voltage signal line is, for example, a VSS signal line; and the reset signal line is, for example, a Vinit signal line, the signal on which can reset the anode of the light-emitting device.

[0135] In some embodiments, the second signal line 16 includes a first voltage signal line, a second voltage signal line, or a reset signal line. The first voltage signal line is, for example, a VDD signal line; the second voltage signal line is, for example, a VSS signal line; and the reset signal line is, for example, a Vinit signal line, where the signal on the Vinit signal line can reset the anode of the light-emitting device. Figure 4i In the example, the first signal line 7 is the Vinit signal line, and the second signal line 16 is the VDD signal line.

[0136] In some embodiments, refer to Figure 5 The display substrate also includes multiple sub-pixels 8 of different colors, located in the display area 100 and arranged in an array; the data line 5 includes a first segment 51 and a second segment 52, the first segment 51 being located in the display area 100 and the second segment 52 being located in the transition area 102; the first segment 51 and the second segment 52 are connected; in any two adjacent columns of sub-pixels 8, the odd-numbered rows of sub-pixels 8 in the first column are connected to the first segment 51 of the first data line 501, and the even-numbered rows of sub-pixels 8 are connected to the first segment 51 of the second data line 502; the odd-numbered rows of sub-pixels 8 in the second column are connected to the first segment 51 of the third data line 503, and the even-numbered rows of sub-pixels 8 are connected to the first segment 51 of the fourth data line 504; in the display area 100, the first segment 51 of the first data line 501 and the first segment 51 of the second data line 502... The first segment 51 of the third data line 503 and the first segment 51 of the fourth data line 504 are arranged sequentially along the first direction X; the first second segment 521, the second second segment 522, the third second segment 523 and the fourth second segment 524 in the transition region 102 are arranged sequentially along the first direction X; the first second segment 521 and the third second segment 523 are located in the first conductive layer 2, and the second second segment 522 and the fourth second segment 524 are located in the second conductive layer 4; the first segment 51 of the first data line 501 is connected to the first second segment 521; the first segment 51 of the second data line 502 is connected to the second second segment 522; the first segment 51 of the third data line 503 is connected to the third second segment 523; the first segment 51 of the fourth data line 504 is connected to the fourth second segment 524.

[0137] Among them, reference Figure 5 In the transition region 102, any two adjacent data lines 5 along the first direction X are located on different conductive layers.

[0138] In some embodiments, in the transition region 102, the second segment 52 of the data line 5 connecting sub-pixels 8 of the same color in the same row is located on the same layer; the second segment 52 of the data line 5 connecting sub-pixels 8 of the same color in adjacent rows is located on different layers.

[0139] In some embodiments, if the sub-pixels 8 of different colors include red sub-pixels 81, green sub-pixels 82, and blue sub-pixels 83, in the transition region 102, the data lines 5 connected to the red sub-pixels 81 in odd-numbered rows are located in the second conductive layer 4, and the data lines 5 connected to the red sub-pixels 81 in even-numbered rows are located in the first conductive layer 2. Similarly, the data lines 5 connected to the green sub-pixels 82 in odd-numbered rows are located in the second conductive layer 4, and the data lines 5 connected to the green sub-pixels 82 in even-numbered rows are located in the first conductive layer 2. The data lines 5 connected to the blue sub-pixels 83 in odd-numbered rows are located in the second conductive layer 4, and the data lines 5 connected to the blue sub-pixels 83 in even-numbered rows are located in the first conductive layer 2. With this configuration, in terms of image quality, brightness differences are likely to exist in the row direction of the sub-pixel 8 array, which may manifest as slight, fine horizontal stripes.

[0140] In some embodiments, refer to Figure 6a and Figure 6b The display substrate also includes multiple sub-pixels 8 of different colors, located in the display area 100 and arranged in an array; the data line 5 includes a first segment 51 and a second segment 52, the first segment 51 is located in the display area 100, and the second segment 52 is located in the transition area 102; the first segment 51 and the second segment 52 are connected; in any two adjacent columns of sub-pixels, the odd-numbered rows of sub-pixels 8 in the first column are connected to the first segment 51 of the first data line 501, and the even-numbered rows of sub-pixels 8 are connected to the first segment 51 of the second data line 502; the odd-numbered rows of sub-pixels 8 in the second column are connected to the first segment 51 of the third data line 503, and the even-numbered rows of sub-pixels 8 are connected to the first segment 51 of the fourth data line 504; in the display area 100, the first segments 51 of the first data line 501, the first segments 51 of the second data line 502, the first segments 51 of the third data line 503, and the first segments 51 of the fourth data line 504 are arranged sequentially along the first direction X; the first segment 51 in the transition area 102 is connected to the first data line 504. The second segment 521, the second segment 522, the third segment 523, and the fourth segment 524 are arranged sequentially along the first direction X; the first segment 521 and the third segment 523 are located in the first conductive layer 2, and the second segment 522 and the fourth segment 524 are located in the second conductive layer 4; it also includes a first jumper 9 and a second jumper 10, located in the transition region 102 and in different intermediate conductive layers 3; the first jumper 9 and the second jumper 10 spatially intersect; the first segment 51 of the first data line 501 is connected to the first segment 521; the first segment 51 of the second data line 502 is connected to one end of the first jumper 9, and the other end of the first jumper 9 is connected to the third segment 523; the first segment 51 of the third data line 503 is connected to one end of the second jumper 10, and the other end of the second jumper 10 is connected to the second segment 522; the first segment 51 of the fourth data line 504 is connected to the fourth segment 524.

[0141] Among them, reference Figure 6aIn the display area 100, any two adjacent data lines 5 along the first direction X are located on the same conductive layer in the transition area 102. With this configuration, the brightness difference in the row direction of the sub-pixel array 8 can be optimized to the best possible level in terms of image quality, effectively improving or eliminating [the issue]. Figure 5 The solution exhibits fine horizontal stripes; however, due to a small overlap between the first jumper 9 and the second jumper 10—approximately 2μm × 2μm—this small overlap results in a slight increase in interference between the first jumper 9 and the second jumper 10. Figure 5 Interference between adjacent data lines 5 in the middle scheme is negligible because the longitudinal distance between the first conductive layer 2 and the second conductive layer 4 along the direction perpendicular to the substrate 1 is large.

[0142] In some embodiments, refer to Figure 6a and Figure 6b In the transition area 102, the second segment 52 of the data line 5 connecting sub-pixels 8 of the same color in the same row is located on the same layer; the second segment 52 of the data line 5 connecting sub-pixels 8 of the same color in adjacent rows is located on the same layer.

[0143] In some embodiments, such as red sub-pixels 81, green sub-pixels 82 and blue sub-pixels 83, the second segment 52 of the data line 5 connected to the red sub-pixels 81 in adjacent rows is located in the second conductive layer 4; the second segment 52 of the data line 5 connected to the blue sub-pixels 83 in adjacent rows is located in the second conductive layer 4; and the second segment 52 of the data line 5 connected to the green sub-pixels 82 in adjacent rows is located in the first conductive layer 2.

[0144] In this embodiment, sub-pixel 8 can be an OLED light-emitting device.

[0145] In some embodiments, refer to Figure 5 , Figure 6a and Figure 6b The first segment 51 of the multiple data lines 5 is located in the second conductive layer 4.

[0146] In some embodiments, other data lines 5 that do not extend into the transition region 102 (i.e., data lines 5 that only extend within the display area 100) are located in the second conductive layer 4. That is, only the data lines 5 within the transition region 102 are designed with layered winding, while other data lines 5 that do not enter the transition region 102 are located in the same conductive layer.

[0147] In some embodiments, refer to Figure 7 The display substrate also includes multiple scan lines 11 located in the display area 100 and in the first conductive layer 2. The multiple scan lines 11 are arranged sequentially along the second direction Y, and the second direction Y intersects with the first direction X.

[0148] The multiple scan lines 11 can be driven by a bilateral driving method to scan each row of sub-pixels 8. The scan lines 11 are not distributed within the transition region 102, thereby avoiding cross-contact and short circuits between the scan lines 11 and data lines 5 located on the first conductive layer 2 within the transition region 102.

[0149] In some embodiments, refer to Figure 8a This is a circuit diagram of a sub-pixel driving circuit in an embodiment of this disclosure; the driving circuit of sub-pixel 8 can adopt a 7T1C (i.e., 7 thin-film transistors and 1 capacitor) circuit. Wherein, the first transistor T1 is the driving transistor, the second transistor T2 is the data writing transistor, the fifth and sixth transistors T6 are light-emitting control transistors, the third transistor T3 is the threshold voltage compensation transistor, and the fourth transistor T4 and the seventh transistor T7 are reset transistors; the capacitor Cst is the storage capacitor. Each transistor has a gate, a source (D), and a drain (S). The specific circuit connection relationship of the 7T1C circuit is as follows... Figure 8a This will not be elaborated upon here.

[0150] It should be noted that the display substrate can also use other relatively mature driving circuits such as 8T1C, 9T1C or 9T2C, which will not be elaborated here.

[0151] In some embodiments, refer to Figure 8b , for along Figure 2a A structural cross-sectional view of the middle II' section line; Figure 8b The diagram illustrates a driving transistor T1, a capacitor Cst, and a sub-pixel 8 located on one side of the substrate 1, away from the substrate 1. An encapsulation layer 17 is also provided on the side of the sub-pixel 8 away from the substrate 1. The sub-pixel 8 can be an OLED light-emitting device, which includes an anode 81, a light-emitting functional layer 82, and a cathode 83 stacked sequentially away from the substrate 1. The encapsulation layer 17 includes a first inorganic encapsulation layer 171, an organic encapsulation layer 172, and a second inorganic encapsulation layer 173 stacked sequentially away from the substrate 1.

[0152] In this embodiment, the first conductive layer 2 may be a gate 1 layer, and the second conductive layer 4 may be a second source / drain metal layer SD2; the intermediate conductive layer 3 includes a gate 2 layer and a first source / drain metal layer SD1. A planarization layer 18 and a pixel delimiting layer 19 are also provided between the second conductive layer 4 and the sub-pixel 8. An opening is provided in the pixel delimiting layer 19, and the sub-pixel 8 is located in the opening.

[0153] In some embodiments, refer to Figure 8c , for along Figure 2a Another structural sectional view of the section line II'; in Figure 8bBased on the display substrate structure, as an extension, when a light-shielding metal layer LS is provided below the driving transistor T1, the first conductive layer can be the light-shielding metal layer LS, and the second conductive layer can be the second source / drain metal layer SD2. As a further extension, the display substrate can also add a third source / drain metal layer SD3, located between the planarization layer 18 and the sub-pixel 8, in which case the second conductive layer can be the third source / drain metal layer SD3. All of the above extensions can achieve the purpose of reducing the coupling capacitance between adjacent data lines within the transition region 102.

[0154] The display substrate provided in this embodiment, by placing one of any two adjacent data lines in the transition region on the first conductive layer and the other on the second conductive layer, significantly increases the longitudinal distance between any two adjacent data lines in the transition region along the first direction perpendicular to the substrate direction. This significantly reduces the coupling capacitance between any two adjacent data lines along the first direction, thereby reducing signal interference between any two adjacent data lines in the transition region along the first direction. Ultimately, this improves or eliminates the vertical bright bar mura defect in the corresponding part of the display area in the light-transmitting area and the transition region, thus improving the display effect of the display substrate.

[0155] Secondly, embodiments of this disclosure also provide a display panel, including the display substrate described in the above embodiments.

[0156] By using the display substrate in the above embodiments, the vertical bright bar mura defect in the display area corresponding to the light-transmitting area and the transition area in the display panel can be improved or eliminated, thereby improving the display effect of the display panel.

[0157] The display panel provided in this embodiment can be any product or component with display function, such as an OLED panel, OLED TV, OLED billboard, monitor, mobile phone, or navigator.

[0158] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display substrate having a display area, a light-transmitting area, and a transition area, wherein the transition area surrounds the light-transmitting area, and the display area surrounds the transition area, wherein... The display substrate includes a substrate. A first conductive layer, at least two intermediate conductive layers, and a second conductive layer are sequentially stacked on one side of the substrate; Multiple data lines are arranged sequentially along a first direction and extend from the display area to the transition area respectively; In the transition region, one of any two adjacent data lines is located in the first conductive layer and the other is located in the second conductive layer.

2. The display substrate according to claim 1, wherein, It also includes multiple first signal lines, arranged sequentially along the first direction, and extending from the display area to the transition area respectively; The first signal line is located in the intermediate conductive layer; In the transition region, any two adjacent data lines correspond to at least one first signal line, the orthographic projection of the first signal line on the substrate is located between the orthographic projections of the two adjacent data lines on the substrate, and the orthographic projections of the first signal line and the data lines on the substrate do not overlap. The signal on the first signal line is a constant voltage signal.

3. The display substrate according to claim 2, wherein, In the transition region, the orthographic projection of the first signal line on the substrate is located at the midpoint of the distance between the orthographic projections of two adjacent data lines on the substrate.

4. The display substrate according to claim 1, wherein, It also includes multiple first signal lines, arranged sequentially along the first direction, and extending from the display area to the transition area respectively; The first signal line is located in the intermediate conductive layer; In the transition region, any two adjacent data lines correspond to at least one of the first signal lines, and the orthographic projections of the first signal line and one of the two adjacent data lines on the substrate at least partially overlap. The signal on the first signal line is a constant voltage signal.

5. The display substrate according to claim 4, wherein, In the transition region, the orthographic projections of the first signal line and one of the two adjacent data lines located in the second conductive layer on the substrate coincide. Alternatively, the orthographic projection of the first signal line and one of the two adjacent data lines located in the first conductive layer on the substrate coincides.

6. The display substrate according to claim 1, wherein, It also includes a first signal line extending from the display area to the transition area; The first signal line is located in the intermediate conductive layer; In the transition region, the orthogonal projection of the first signal line on the substrate covers the orthogonal projection of the plurality of data lines on the substrate.

7. The display substrate according to claim 1, wherein, It also includes a first signal line extending from the display area to the transition area; The first signal line is located in the intermediate conductive layer near the second conductive layer; The portion of the first signal line located in the transition region includes a first solid portion and a first cutout portion. The orthogonal projection of the data line located in the second conductive layer within the transition zone onto the substrate is located within the orthogonal projection of the first hollow portion onto the substrate. The orthographic projection of the first physical portion onto the substrate overlaps the orthographic projection of the data line located on the first conductive layer onto the substrate.

8. The display substrate according to claim 1, wherein, It also includes a first signal line extending from the display area to the transition area; The first signal line is located in the intermediate conductive layer near the first conductive layer; The portion of the first signal line located in the transition region includes a first solid portion and a first cutout portion. The orthogonal projection of the data line located in the first conductive layer within the transition zone onto the substrate is located within the orthogonal projection of the first hollow portion onto the substrate. The orthographic projection of the first solid portion on the substrate covers the orthographic projection of the data line located on the second conductive layer on the substrate.

9. The display substrate according to claim 1, wherein, The intermediate conductive layer includes a first intermediate conductive layer and a second intermediate conductive layer, which are stacked sequentially away from the substrate. The display substrate also includes a first signal line and a second signal line, both extending from the display area to the transition area; The first signal line is located in the first intermediate conductive layer; The second signal line is located in the second intermediate conductive layer; The portion of the first signal line located in the transition region includes a first solid portion and a first cutout portion. The orthogonal projection of the data line located in the first conductive layer within the transition zone onto the substrate is located within the orthogonal projection of the first hollow portion onto the substrate. The orthographic projection of the first solid portion onto the substrate covers the orthographic projection of the data line located on the second conductive layer onto the substrate; The portion of the second signal line located in the transition region includes a second solid portion and a second cutout portion. The orthographic projection of the data line located on the second conductive layer within the transition zone onto the substrate is located within the orthographic projection of the second cutout portion onto the substrate; The orthographic projection of the second physical portion onto the substrate overlaps the orthographic projection of the data line located on the first conductive layer onto the substrate.

10. The display substrate according to any one of claims 2-9, wherein, The first signal line includes a first voltage signal line, a second voltage signal line, or a reset signal line.

11. The display substrate according to claim 9, wherein, The second signal line includes a first voltage signal line, a second voltage signal line, or a reset signal line.

12. The display substrate according to claim 1, wherein, It also includes multiple sub-pixels of different colors, located in the display area and arranged in an array; The data cable includes a first segment and a second segment, the first segment being located in the display area and the second segment being located in the transition area; the first segment and the second segment are connected. In any two adjacent columns of sub-pixels, the odd-numbered rows of the first column of sub-pixels are connected to the first segment of the first data line, and the even-numbered rows of sub-pixels are connected to the first segment of the second data line; in the second column of sub-pixels, the odd-numbered rows of sub-pixels are connected to the first segment of the third data line, and the even-numbered rows of sub-pixels are connected to the first segment of the fourth data line. In the display area, the first segment of the first data line, the first segment of the second data line, the first segment of the third data line, and the first segment of the fourth data line are arranged sequentially along the first direction; The first, second, third, and fourth second segments within the transition zone are arranged sequentially along the first direction; The first and third second segments are located in the first conductive layer, and the second and fourth second segments are located in the second conductive layer; The first segment of the first data line is connected to the first second segment; The first segment of the second data line is connected to the second segment; The first segment of the third data line is connected to the third second segment; The first segment of the fourth data line is connected to the fourth second segment.

13. The display substrate according to claim 12, wherein, In the transition zone, the second segment of the data line connecting the sub-pixels of the same color in the same row is located on the same layer; the second segment of the data line connecting the sub-pixels of the same color in adjacent rows is located on different layers.

14. The display substrate according to claim 1, wherein, It also includes multiple sub-pixels of different colors, located in the display area and arranged in an array; The data cable includes a first segment and a second segment, the first segment being located in the display area and the second segment being located in the transition area; the first segment and the second segment are connected. In any two adjacent columns of sub-pixels, the odd-numbered rows of the first column of sub-pixels are connected to the first segment of the first data line, and the even-numbered rows of sub-pixels are connected to the first segment of the second data line; in the second column of sub-pixels, the odd-numbered rows of sub-pixels are connected to the first segment of the third data line, and the even-numbered rows of sub-pixels are connected to the first segment of the fourth data line. In the display area, the first segment of the first data line, the first segment of the second data line, the first segment of the third data line, and the first segment of the fourth data line are arranged sequentially along the first direction; The first, second, third, and fourth second segments within the transition zone are arranged sequentially along the first direction; The first and third second segments are located in the first conductive layer, and the second and fourth second segments are located in the second conductive layer; It also includes a first jumper and a second jumper, located in the transition region and in different intermediate conductive layers; the first jumper and the second jumper spatially intersect. The first segment of the first data line is connected to the first second segment; The first segment of the second data line is connected to one end of the first jumper, and the other end of the first jumper is connected to the third second segment; The first segment of the third data line is connected to one end of the second jumper, and the other end of the second jumper is connected to the second segment. The first segment of the fourth data line is connected to the fourth second segment.

15. The display substrate according to claim 14, wherein, In the transition zone, the second segment of the data line connecting the sub-pixels of the same color in the same row is located on the same layer; the second segment of the data line connecting the sub-pixels of the same color in adjacent rows is located on the same layer.

16. The display substrate according to claim 15, wherein, The sub-pixels of different colors include red sub-pixels, green sub-pixels, and blue sub-pixels; The second segment of the data line connecting the red sub-pixels in adjacent rows is located in the second conductive layer; The second segment of the data line connecting the blue sub-pixels in adjacent rows is located in the second conductive layer; The second segment of the data line connecting the green sub-pixels in adjacent rows is located in the first conductive layer.

17. The display substrate according to any one of claims 12-16, wherein, The first segment of the multiple data lines is located in the second conductive layer.

18. The display substrate according to claim 1, wherein, Multiple insulating layers are disposed between the first conductive layer and the second conductive layer. The total thickness of the plurality of insulating layers ranges from 1.6 to 1.8 μm.

19. The display substrate according to claim 1, wherein, It also includes multiple scan lines located in the display area and within the first conductive layer. The multiple scan lines are arranged sequentially along the second direction. The second direction intersects with the first direction.

20. A display panel, wherein, Includes the display substrate as described in any one of claims 1-19.

Images