Storage unit, manufacturing method thereof and storage array

Abstract

The invention discloses a storage unit and a manufacturing method thereof, and a storage array, and the storage unit comprises a substrate which is provided with an active region, and the active region is internally provided with a groove; the first floating gate structure and the second floating gate structure are located in the groove; a barrier layer located on the surfaces of the first floating gate structure and the second floating gate structure; the common source layer is located in a first region of the active region, and the first drain layer and the second drain layer are located in a second region of the active region; the word line layer is located in the groove and covers the first floating gate structure and the second floating gate structure; and the bit line layer is electrically connected with the first drain layer and the second drain layer. The first floating gate structure and the second floating gate structure are located in the groove, and the first floating gate structure and the second floating gate structure cover part of the side wall and part of the bottom surface of the groove, so that a channel correspondingly formed by the first floating gate structure and the second floating gate structure is of a cambered surface structure, and the size of a channel region is increased; therefore, the coupling effect of the word line layer on the channel is enhanced, and the writing and erasing efficiency is improved.

Description

Storage cells and their manufacturing methods, storage arrays Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a memory cell and its manufacturing method, and a memory array. Background Technology

[0002] With the rapid popularization of electronic products, flash memory has become the mainstream storage medium and its technology has developed very rapidly.

[0003] Flash memory is a type of non-volatile memory, meaning data is not lost when power is off, which has led to its widespread use. Flash memory includes NOR flash memory and NAND flash memory. NOR flash memory allows independent read and write operations on each of its storage cells, providing full random access functionality, and therefore can be used for non-volatile storage of executable programs.

[0004] However, existing NOR storage cells still have many problems. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a storage unit and its manufacturing method, as well as a storage array, to improve write and erase efficiency.

[0006] To address the aforementioned problems, the present invention provides a memory cell comprising: a substrate having an active region extending along a first direction, the active region including a first region and a second region located on the first region, the second region having a trench; a first floating gate structure and a second floating gate structure arranged along the first direction within the trench, the first floating gate structure and the second floating gate structure covering a portion of the sidewalls and a portion of the bottom surface of the trench; a barrier layer located on the surfaces of the first floating gate structure and the second floating gate structure; a common source layer located in the first region, and a first drain layer and a second drain layer located in the second region, the first drain layer and the common source layer located on both sides of the first floating gate structure, the second drain layer and the common source layer located on both sides of the second floating gate structure, the common source layer located between the first floating gate structure and the second floating gate structure, the first drain layer and the second drain layer located on both sides of the trench; a word line layer located within the trench, the word line layer covering the first floating gate structure and the second floating gate structure; and a bit line layer electrically connected to the first drain layer and the second drain layer.

[0007] Optionally, the word line layer is an integral structure; the word line layer extends along the second direction, and the word line layer simultaneously covers the first floating gate structure and the second floating gate structure, wherein the first direction is perpendicular to the second direction.

[0008] Optionally, the bit line layer has a split structure; the bit line layer includes: a first sub-bit line layer, the first sub-bit line layer extending along the first direction, the first sub-bit line layer being electrically connected to the first drain layer; and a second sub-bit line layer, the second sub-bit line layer extending along the first direction, the second sub-bit line layer being electrically connected to the second drain layer.

[0009] Optionally, the word line layer is a split structure; the word line layer includes: a first sub-word line layer, the first sub-word line layer extends along a second direction, the first sub-word line layer covers the first floating gate structure, the first direction is perpendicular to the second direction; and a second sub-word line layer, the second sub-word line layer extends along the second direction, the second sub-word line layer covers the second floating gate structure.

[0010] Optionally, the bit line layer is an integral structure; the bit line layer extends along the first direction, and the bit line layer is electrically connected to both the first drain layer and the second drain layer.

[0011] Optionally, the top surface of the word line layer is lower than the top surface of the second region.

[0012] Optionally, it further includes: a first conductive plug, which is electrically connected to the first drain layer; a second conductive plug, which is electrically connected to the second drain layer; a third conductive plug, which is electrically connected to the first conductive plug and the first sub-bit line layer respectively; and a fourth conductive plug, which is electrically connected to the second conductive plug and the second sub-bit line layer respectively.

[0013] Optionally, the first conductive plug has a first axis of symmetry extending along the first direction, the second conductive plug has a second axis of symmetry extending along the first direction, and the first axis of symmetry coincides with the second axis of symmetry; the third conductive plug is in partial contact with the first conductive plug; and the fourth conductive plug is in partial contact with the second conductive plug.

[0014] Optionally, the first conductive plug has a first axis of symmetry extending along the first direction, the second conductive plug has a second axis of symmetry extending along the first direction, and the first axis of symmetry and the second axis of symmetry do not coincide; the third conductive plug is in complete contact with the first conductive plug; and the fourth conductive plug is in complete contact with the second conductive plug.

[0015] Accordingly, the present invention also provides a method for fabricating a memory cell, comprising: providing a substrate having an active region extending along a first direction, the active region including a first region and a second region located on the first region, the second region having a trench; forming a first floating gate structure and a second floating gate structure arranged along the first direction in the trench, the first floating gate structure and the second floating gate structure covering part of the sidewalls and part of the bottom surface of the trench; forming a barrier layer on the surface of the first floating gate structure and the surface of the second floating gate structure; forming a common source layer in the first region and forming a first drain layer and a second drain layer in the second region, the first drain layer and the common source layer being located on both sides of the first floating gate structure, the second drain layer and the common source layer being located on both sides of the second floating gate structure, the common source layer being located between the first floating gate structure and the second floating gate structure, the first drain layer and the second drain layer being located on both sides of the trench; forming a word line layer in the trench, the word line layer covering the first floating gate structure and the second floating gate structure; forming a bit line layer, the bit line layer being electrically connected to the first drain layer and the second drain layer.

[0016] Optionally, the word line layer is an integral structure; the word line layer extends along the second direction, and the word line layer simultaneously covers the first floating gate structure and the second floating gate structure, wherein the first direction is perpendicular to the second direction.

[0017] Optionally, the bit line layer has a split structure; the bit line layer includes: a first sub-bit line layer, the first sub-bit line layer extending along the first direction, the first sub-bit line layer being electrically connected to the first drain layer; and a second sub-bit line layer, the second sub-bit line layer extending along the first direction, the second sub-bit line layer being electrically connected to the second drain layer.

[0018] Optionally, the word line layer is a split structure; the word line layer includes: a first sub-word line layer, the first sub-word line layer extends along a second direction, the first sub-word line layer covers the first floating gate structure, the first direction is perpendicular to the second direction; and a second sub-word line layer, the second sub-word line layer extends along the second direction, the second sub-word line layer covers the second floating gate structure.

[0019] Optionally, the bit line layer is an integral structure; the bit line layer extends along the first direction, and the bit line layer is electrically connected to both the first drain layer and the second drain layer.

[0020] Optionally, the top surface of the word line layer is lower than the top surface of the second region.

[0021] Optionally, the first floating gate structure and the second floating gate structure are formed simultaneously; the method for manufacturing the first floating gate structure and the second floating gate structure includes: forming a floating gate material layer on the trench; performing a self-aligned etching process on the floating gate material layer to form the first floating gate structure and the second floating gate structure.

[0022] Optionally, the method for electrically connecting the bit line layer to the first drain layer and the second drain layer includes: forming a first conductive plug and a second conductive plug, wherein the first conductive plug is electrically connected to the first drain layer and the second conductive plug is electrically connected to the second drain layer; forming a third conductive plug and a fourth conductive plug, wherein the third conductive plug is electrically connected to the first conductive plug and the first sub-bit line layer respectively, and the fourth conductive plug is electrically connected to the second conductive plug and the second sub-bit line layer respectively.

[0023] Optionally, the first conductive plug has a first axis of symmetry extending along the first direction, the second conductive plug has a second axis of symmetry extending along the first direction, and the first axis of symmetry coincides with the second axis of symmetry; the third conductive plug is in partial contact with the first conductive plug; and the fourth conductive plug is in partial contact with the second conductive plug.

[0024] Optionally, the first conductive plug has a first axis of symmetry extending along the first direction, the second conductive plug has a second axis of symmetry extending along the first direction, and the first axis of symmetry and the second axis of symmetry do not coincide; the third conductive plug is in complete contact with the first conductive plug; and the fourth conductive plug is in complete contact with the second conductive plug.

[0025] Accordingly, the present invention also provides a memory array, comprising: a plurality of memory groups arranged in parallel along a first direction, each memory group comprising a plurality of memory cells as described in any of the above technical solutions, the plurality of memory cells arranged along a second direction, the first direction being perpendicular to the second direction; wherein, in each memory group, the plurality of memory cells share the word line layer; in each memory group, the common source layer of the plurality of memory cells is electrically connected; adjacent memory groups are mirror-symmetrically distributed; adjacent memory groups share the first drain layer or the second drain layer; adjacent memory groups share the bit line layer.

[0026] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0027] In the storage unit of the present invention, the first floating gate structure and the second floating gate structure are located in the trench, and the first floating gate structure and the second floating gate structure cover part of the sidewall and part of the bottom surface of the trench, so that the trench formed by the first floating gate structure and the second floating gate structure is an arc surface structure, thereby increasing the size of the trench area, thereby enhancing the coupling effect of the word line layer to the trench, and thus improving the write and erase efficiency.

[0028] Furthermore, the word line layer is a monolithic structure; it extends along a second direction and simultaneously covers both the first and second floating gate structures. The first direction is perpendicular to the second direction, meaning adjacent first and second floating gate structures share a single word line layer. This provides the word line layer with greater formation space, thereby increasing its volume and effectively reducing its resistance. Additionally, the increased volume of the word line layer enhances control over the first and second floating gate structures, thus improving the coupling effect of the device structure.

[0029] Furthermore, the top surface of the word line layer is lower than the top surface of the second region. This increases the spacing between the word line layer and the conductive plugs formed on the first drain layer and the second drain layer, thereby reducing the coupling capacitance between the word line layer and the conductive plugs.

[0030] In the method for manufacturing the storage cell of the present invention, the first floating gate structure and the second floating gate structure are formed in the trench, and the first floating gate structure and the second floating gate structure cover part of the sidewall and part of the bottom surface of the trench, so that the channels formed by the first floating gate structure and the second floating gate structure are arc-shaped structures, thereby increasing the size of the channel area and enhancing the coupling effect of the word line layer to the channel, thereby improving the write and erase efficiency.

[0031] Furthermore, the word line layer is a monolithic structure; it extends along a second direction and simultaneously covers both the first and second floating gate structures. The first direction is perpendicular to the second direction, meaning adjacent first and second floating gate structures share a single word line layer. This provides the word line layer with greater formation space, thereby increasing its volume and effectively reducing its resistance. Additionally, the increased volume of the word line layer enhances control over the first and second floating gate structures, thus improving the coupling effect of the device structure.

[0032] Furthermore, the top surface of the word line layer is lower than the top surface of the second region. This increases the spacing between the word line layer and the conductive plugs formed on the first drain layer and the second drain layer, thereby reducing the coupling capacitance between the word line layer and the conductive plugs.

[0033] In the storage array of the present invention, the first floating gate structure and the second floating gate structure are formed in the trench, and the first floating gate structure and the second floating gate structure cover part of the sidewall and part of the bottom surface of the trench, so that the channels formed by the first floating gate structure and the second floating gate structure are arc-shaped structures, thereby increasing the size of the channel area and enhancing the coupling effect of the word line layer to the channel, thereby improving the write and erase efficiency. Attached Figure Description

[0034] Figure 1 is a schematic diagram of a storage cell structure;

[0035] Figure 2 is a schematic diagram of the cross section along line AA in Figure 1;

[0036] Figures 3 to 10 are schematic diagrams of the structure of each step in the method for manufacturing the storage unit in the embodiments of the present invention;

[0037] Figures 11 to 21 are schematic diagrams of the structure of each step of the method for manufacturing a storage unit in another embodiment of the present invention;

[0038] Figure 22 is a schematic diagram of the storage array in an embodiment of the present invention;

[0039] Figure 23 is a schematic diagram of the circuit structure of the storage array in an embodiment of the present invention;

[0040] Figure 24 is a schematic diagram of the structure of a storage array in another embodiment of the present invention;

[0041] Figure 25 is a schematic diagram of the circuit structure of the storage array in another embodiment of the present invention. Detailed Implementation

[0042] As described in the background section, existing NOR memory cells still have many problems. These will be explained in detail below with reference to the accompanying drawings.

[0043] Figure 1 is a schematic diagram of a storage cell structure; Figure 2 is a cross-sectional view along line AA in Figure 1.

[0044] Please refer to Figures 1 and 2. A memory cell includes: a substrate 100 having an active region 1001 extending along a first direction X; a first floating gate structure 101 and a second floating gate structure 102 arranged along the first direction X on the active region 1001; a barrier layer 103 located on the top surface of the first floating gate structure 101 and the top surface of the second floating gate structure 102; a common source layer 104, a first drain layer 105, and a second drain layer 106 located within the active region 1001, wherein the first drain layer 105 and the common source layer 104 are located on both sides of the first floating gate structure 101, and the second drain layer 106 and the common source layer 104 are located on both sides of the second floating gate structure 102. The common source layer 104 is located between the first floating gate structure 101 and the second floating gate structure 102; a first word line layer 107 is located on the substrate 100, extending along the second direction Y, and controlling the first floating gate structure 101, wherein the first direction X is perpendicular to the second direction Y; a second word line layer 108 is located on the substrate 100, extending along the second direction Y, and controlling the second floating gate structure 102; a bit line layer 109 extends along the first direction X, and is electrically connected to the first drain layer 105 and the second drain layer 106 respectively.

[0045] In this embodiment, the first floating gate structure 101 and the second floating gate structure 102 only cover part of the top surface of the active region 1001, so that the channel area formed by the first floating gate structure 101 and the second floating gate structure 102 is smaller, thereby weakening the coupling effect of the first word line layer 107 and the second word line layer 108 on the channel, thereby reducing the write and erase efficiency.

[0046] Based on this, the present invention provides a storage cell and its manufacturing method, and a storage array, wherein the first floating gate structure and the second floating gate structure are formed in the trench, and the first floating gate structure and the second floating gate structure cover part of the sidewall and part of the bottom surface of the trench, so that the channels formed by the first floating gate structure and the second floating gate structure are arc surface structures, thereby increasing the size of the channel area, thereby enhancing the coupling effect of the word line layer to the channel, and thus improving the write and erase efficiency.

[0047] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0048] Figures 3 to 10 are schematic diagrams of the structure of each step in the manufacturing method of the storage unit in the embodiments of the present invention.

[0049] Please refer to Figures 3 and 4. Figure 4 is a cross-sectional view along line BB in Figure 3. A substrate 200 is provided. The substrate 200 has an active region 2001 extending along a first direction X. The active region 2001 includes a first region I and a second region II located on the first region I. The second region II has a trench 2002.

[0050] In this embodiment, the substrate 200 is made of silicon.

[0051] In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium galliumide.

[0052] In this embodiment, channel ions are implanted in the active region 2001, and the channel ions can be N-type ions or P-type ions.

[0053] Please refer to Figures 5 and 6. Figure 6 is a cross-sectional view along line CC in Figure 5. A first floating grid structure 201 and a second floating grid structure 202 are formed in the trench 2002 along the first direction X. The first floating grid structure 201 and the second floating grid structure 202 cover part of the sidewall and part of the bottom surface of the trench 2002.

[0054] The first floating grid structure 201 and the second floating grid structure 202 are located within the trench 2002, and the first floating grid structure 201 and the second floating grid structure 202 cover part of the sidewall and part of the bottom surface of the trench 2002, so that the trenches formed by the first floating grid structure 201 and the second floating grid structure 202 are arc-shaped structures, thereby increasing the size of the trench area and enhancing the coupling effect of the subsequently formed word line layer on the trench, thereby improving the writing and erasing efficiency.

[0055] In this embodiment, the first floating gate structure 201 and the second floating gate structure 202 are formed simultaneously; the method for fabricating the first floating gate structure 201 and the second floating gate structure 202 includes: forming a floating gate material layer (not shown) on the substrate 200; and performing a self-aligned etching process on the floating gate material layer to form the first floating gate structure 201 and the second floating gate structure 202.

[0056] In this embodiment, the floating gate material layer includes a tunneling oxide material layer and a gate material layer located on the tunneling oxide material layer. The corresponding first floating gate structure 201 and second floating gate structure 202 both include a tunneling oxide layer (not shown) and a floating gate layer (not shown).

[0057] It should be noted that, in this embodiment, after forming the trench 2002, its surface is subjected to thermal oxidation to form an oxide layer, wherein the portion covered by the gate material layer serves as the tunneling oxide material layer. Only the gate material layer within the floating gate material layer undergoes self-aligned etching; the tunneling oxide material layer of the floating gate material layer is completely retained. Ultimately, the tunneling oxide material layer covered by the floating gate layer constitutes the tunneling oxide layer. Since the surface of the trench 2002 is not flat, and the gate material layer exhibits varying thicknesses, the self-aligned etching process can employ anisotropic dry etching, eliminating the need for a photomask process, effectively simplifying the manufacturing process and reducing production costs.

[0058] In this embodiment, the material of the tunneling oxide layer is silicon oxide, and the material of the floating gate layer is polycrystalline silicon.

[0059] Please refer to Figure 7. The view orientation of Figure 7 is the same as that of Figure 6. After the first floating gate structure 201 and the second floating gate structure 202 are formed, a common source layer 204 is formed in the first region I, and a first drain layer 205 and a second drain layer 206 are formed in the second region II. The first drain layer 205 and the common source layer 204 are located on both sides of the first floating gate structure 201, the second drain layer 206 and the common source layer 204 are located on both sides of the second floating gate structure 202, the common source layer 204 is located between the first floating gate structure 201 and the second floating gate structure 202, and the first drain layer 205 and the second drain layer 206 are located on both sides of the trench 2002.

[0060] In this embodiment, the method for fabricating the common source layer 204, the first drain layer 205, and the second drain layer 206 includes: using the first floating gate structure 201 and the second floating gate structure 202 as masks, injecting source and drain ions into the active region 2001 to form the common source layer 204, the first drain layer 205, and the second drain layer 206.

[0061] In this embodiment, the electrical type of the source / drain ions is opposite to that of the channel ions, that is, the source / drain ions can be P-type ions or N-type ions.

[0062] In this embodiment, it should be noted that after forming the common source layer 204, the first drain layer 205 and the second drain layer 206, it is necessary to form corresponding metal silicide layers or perform ion heavy doping (not shown) on the surface of the common source layer 204, the first drain layer 205 and the second drain layer 206 to reduce their contact resistance.

[0063] Please refer to Figure 8. After the common source layer 204, the first drain layer 205 and the second drain layer 206 are formed, a barrier layer 203 is formed on the sidewall and top surface of the first floating gate structure 201 and the sidewall and top surface of the second floating gate structure 202.

[0064] The barrier layer 203 is also formed on the top surface of the substrate 200, and the barrier layer 203 located on the top surface of the substrate 200 can be retained or removed.

[0065] In this embodiment, the barrier layer 203 located on the top surface of the substrate 200 is removed.

[0066] In this embodiment, the barrier layer 203 has a multilayer structure, that is, the barrier layer 203 includes: a first silicon oxide layer (not shown), a silicon nitride layer (not shown) located on the surface of the first silicon oxide layer, and a second silicon oxide layer (not shown) located on the surface of the silicon nitride layer.

[0067] By setting the barrier layer 203 as a multilayer structure, the dielectric constant of the barrier layer 203 is increased, thereby enhancing the electric field distributed to the tunneling oxide layer and thus strengthening the coupling effect of writing and erasing the device structure. In addition, the first silicon oxide layer and the second silicon oxide layer can bond well with the substrate, while the silicon nitride layer in the middle can block the extension of defects (such as pinholes). Therefore, the three-layer structure design can complement each other.

[0068] Please continue referring to Figure 8. In this embodiment, after forming the common source layer 204, the first drain layer 205, and the second drain layer 206, and before forming the barrier layer 203, a gate dielectric layer 213 needs to be formed. The gate dielectric layer 213 is located at the position corresponding to the word line layer and the channel region formed subsequently. Part of the gate dielectric layer 213 is the tunneling oxide material layer that has not been etched away, while the other part of the gate dielectric layer 213 needs to be formed through a deposition-then-etch process. Furthermore, to ensure device reliability, the tunneling oxide material layer between the first floating gate structure 201 and the second floating gate structure 202 needs to be thickened, i.e., this is done simultaneously with the addition of the gate dielectric layer 213.

[0069] Please refer to Figure 9. After the barrier layer 203 is formed, a word line layer is formed in the trench 2002, which covers the first floating gate structure 201 and the second floating gate structure 202.

[0070] In this embodiment, the character line layer is a split structure; the character line layer includes: a first sub-character line layer 207, which extends along a second direction (not shown) and covers the first floating gate structure 201, wherein the first direction X is perpendicular to the second direction; and a second sub-character line layer 208, which extends along the second direction and covers the second floating gate structure 202.

[0071] Before forming the word line layer, a gate dielectric layer (not shown) needs to be formed on the common source layer 204. The height of the gate dielectric layer cannot exceed the height of the barrier layer 203 located on the top surface of the first floating gate structure 201 and the second floating gate structure 202, and the height of the gate dielectric layer should be sufficient to ensure that there is no obvious coupling between the word line layer and the common source layer 204.

[0072] In this embodiment, the method for fabricating the word line layer includes: forming a word line material layer (not shown) on the substrate 200, the word line material layer covering the barrier layer 203, the first floating gate structure 201 and the second floating gate structure 202; and performing patterned etching on the word line material layer to form the first sub-word line layer 207 and the second sub-word line layer 208.

[0073] In this embodiment, the materials of the first sub-word line layer 207 and the second sub-word line layer 208 are polycrystalline silicon, silicon nitride, or other storage materials, with thinner materials being preferred while still meeting storage capacity requirements.

[0074] In this embodiment, the top surface of the word line layer (i.e., the first sub-word line layer 207 and the second sub-word line layer 208) is lower than the top surface of the second region II. This increases the spacing between the word line layer and the conductive plugs subsequently formed on the first drain layer 205 and the second drain layer 206, thereby reducing the coupling capacitance between the word line layer and the conductive plugs.

[0075] Please continue referring to Figure 9. In this embodiment, after forming the word line layer, the method further includes forming a metal contact layer 209 (i.e., a metal silicide layer) on the word line layer (i.e., the first sub-word line layer 207 and the second sub-word line layer 208). The metal contact layer 209 reduces the contact resistance between the conductive plug and the word line layer.

[0076] Please refer to Figure 10. After the word line layer is formed, a bit line layer 210 is formed. The bit line layer 210 is electrically connected to the first drain layer 205 and the second drain layer 206.

[0077] In this embodiment, the bit line layer 210 is an integral structure; the bit line layer 210 extends along the first direction X, and the bit line layer 210 is electrically connected to both the first drain layer 205 and the second drain layer 206.

[0078] The method of electrically connecting the bit line layer 210 to the first drain layer 205 and the second drain layer 206 respectively includes: forming a first conductive plug 211 and a second conductive plug 212, wherein the first conductive plug 211 is electrically connected to the first drain layer 205 and the bit line layer 210 respectively, and the second conductive plug 212 is electrically connected to the second drain layer 206 and the bit line layer 210 respectively.

[0079] It should be noted that, in this embodiment, during the formation of the first conductive plug 211, the second conductive plug 212 and the bit line layer 210, a corresponding interlayer dielectric layer (not shown) also needs to be formed on the substrate 200. The first conductive plug 211, the second conductive plug 212 and the bit line layer 210 are all formed by patterning and etching the interlayer dielectric layer and then filling it with metal.

[0080] Accordingly, this embodiment of the invention also provides a memory cell 20, please continue to refer to FIG10, including: a substrate 200, the substrate 200 having an active region 2001 extending along a first direction X, the active region 2001 including a first region I and a second region II located on the first region I, the second region II having a trench 2002; a first floating gate structure 201 and a second floating gate structure 202 arranged along the first direction X within the trench 2002, the first floating gate structure 201 and the second floating gate structure 202 covering part of the sidewalls and part of the bottom surface of the trench 2002; a barrier layer 203 located on the surface of the first floating gate structure 201 and the surface of the second floating gate structure 202; and a common source layer located within the first region I. 204, and a first drain layer 205 and a second drain layer 206 located in the second region II, wherein the first drain layer 205 and the common source layer 204 are located on both sides of the first floating gate structure 201, the second drain layer 206 and the common source layer 204 are located on both sides of the second floating gate structure 202, the common source layer 204 is located between the first floating gate structure 201 and the second floating gate structure 202, and the first drain layer 205 and the second drain layer 206 are located on both sides of the trench 2002; a word line layer located in the trench 2002, the word line layer covering the first floating gate structure 201 and the second floating gate structure 202; and a bit line layer 210 electrically connected to the first drain layer 205 and the second drain layer 206.

[0081] The first floating grid structure 201 and the second floating grid structure 202 are located within the trench 2002, and the first floating grid structure 201 and the second floating grid structure 202 cover part of the sidewall and part of the bottom surface of the trench 2002, so that the trenches formed by the first floating grid structure 201 and the second floating grid structure 202 are arc-shaped structures, thereby increasing the size of the trench area and enhancing the coupling effect of the word line layer to the trench, thereby improving the writing and erasing efficiency.

[0082] In this embodiment, the character line layer is a split structure; the character line layer includes: a first sub-character line layer 207, which extends along a second direction and covers the first floating gate structure 201, wherein the first direction X is perpendicular to the second direction; and a second sub-character line layer 208, which extends along the second direction and covers the second floating gate structure 202.

[0083] In this embodiment, the bit line layer 210 is an integral structure; the bit line layer 210 extends along the first direction X, and the bit line layer 210 is electrically connected to both the first drain layer 205 and the second drain layer 206.

[0084] In this embodiment, the top surface of the word line layer is lower than the top surface of the second region II. This increases the spacing between the word line layer and the conductive plugs formed on the first drain layer 205 and the second drain layer 206, thereby reducing the coupling capacitance between the word line layer and the conductive plugs.

[0085] Figures 11 to 21 are schematic diagrams of the steps in the manufacturing method of the storage unit in another embodiment of the present invention.

[0086] Please refer to Figures 11 and 12. Figure 12 is a cross-sectional view along line BB in Figure 11. A substrate 300 is provided, which has an active region 3001 extending along a first direction X. The active region 3001 includes a first region I and a second region II located on the first region I. The second region II has a trench 3002.

[0087] In this embodiment, the substrate 300 is made of silicon.

[0088] In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium galliumide.

[0089] In this embodiment, channel ions are implanted in the active region 3001, and the channel ions can be N-type ions or P-type ions.

[0090] Please refer to Figures 13 and 14. Figure 14 is a cross-sectional view along line CC in Figure 13. A first floating grid structure 301 and a second floating grid structure 302 are formed in the trench 3002 along the first direction X. The first floating grid structure 301 and the second floating grid structure 302 cover part of the sidewall and part of the bottom surface of the trench 3002.

[0091] The first floating grid structure 301 and the second floating grid structure 302 are located within the trench 3002, and the first floating grid structure 301 and the second floating grid structure 302 cover part of the sidewall and part of the bottom surface of the trench 3002, so that the trenches formed by the first floating grid structure 301 and the second floating grid structure 302 are arc-shaped structures, thereby increasing the size of the trench area and enhancing the coupling effect of the subsequently formed word line layer on the trench, thereby improving the writing and erasing efficiency.

[0092] In this embodiment, the first floating gate structure 301 and the second floating gate structure 302 are formed simultaneously; the method for fabricating the first floating gate structure 301 and the second floating gate structure 302 includes: forming a floating gate material layer (not shown) on the substrate 300; and performing a self-aligned etching process on the floating gate material layer to form the first floating gate structure 301 and the second floating gate structure 302.

[0093] In this embodiment, the floating gate material layer includes a tunneling oxide material layer and a gate material layer located on the tunneling oxide material layer. The corresponding first floating gate structure 301 and second floating gate structure 302 both include a tunneling oxide layer (not shown) and a floating gate layer (not shown).

[0094] It should be noted that, in this embodiment, after forming the trench 3002, its surface is subjected to thermal oxidation to form an oxide layer, wherein the portion covered by the gate material layer serves as the tunneling oxide material layer. Only the gate material layer within the floating gate material layer undergoes self-aligned etching; the tunneling oxide material layer of the floating gate material layer is completely retained. Ultimately, the tunneling oxide material layer covered by the floating gate layer constitutes the tunneling oxide layer. Since the surface of the trench 3002 is not flat, and the gate material layer exhibits varying thicknesses, the self-aligned etching process can employ anisotropic dry etching, eliminating the need for a photomask process, effectively simplifying the manufacturing process and reducing production costs.

[0095] In this embodiment, the material of the tunneling oxide layer is silicon oxide, and the material of the floating gate layer is polycrystalline silicon.

[0096] Please refer to Figure 15. The view orientation of Figure 15 is the same as that of Figure 14. After the first floating gate structure 301 and the second floating gate structure 302 are formed, a common source layer 304 is formed in the first region I, and a first drain layer 305 and a second drain layer 306 are formed in the second region II. The first drain layer 305 and the common source layer 304 are located on both sides of the first floating gate structure 301, the second drain layer 306 and the common source layer 304 are located on both sides of the second floating gate structure 302, the common source layer 304 is located between the first floating gate structure 301 and the second floating gate structure 302, and the first drain layer 305 and the second drain layer 306 are located on both sides of the trench 3002.

[0097] In this embodiment, the method for fabricating the common source layer 304, the first drain layer 305, and the second drain layer 306 includes: using the first floating gate structure 301 and the second floating gate structure 302 as masks, injecting source and drain ions into the active region 3001 to form the common source layer 304, the first drain layer 305, and the second drain layer 306.

[0098] In this embodiment, the electrical type of the source / drain ions is opposite to that of the channel ions, that is, the source / drain ions can be P-type ions or N-type ions.

[0099] In this embodiment, it should be noted that after forming the common source layer 304, the first drain layer 305 and the second drain layer 306, it is necessary to form corresponding metal silicide layers or perform ion heavy doping (not shown) on the surfaces of the common source layer 304, the first drain layer 305 and the second drain layer 306 to reduce their contact resistance.

[0100] Please refer to Figure 16. After the common source layer 304, the first drain layer 305 and the second drain layer 306 are formed, a barrier layer 303 is formed on the sidewall and top surface of the first floating gate structure 301 and the sidewall and top surface of the second floating gate structure 302.

[0101] The barrier layer 303 is also formed on the top surface of the substrate 300, and the barrier layer 303 located on the top surface of the substrate 300 can be retained or removed.

[0102] In this embodiment, the barrier layer 303 located on the top surface of the substrate 300 is removed.

[0103] In this embodiment, the barrier layer 303 has a multilayer structure, that is, the barrier layer 303 includes: a first silicon oxide layer (not shown), a silicon nitride layer (not shown) located on the surface of the first silicon oxide layer, and a second silicon oxide layer (not shown) located on the surface of the silicon nitride layer.

[0104] By configuring the barrier layer 303 as a multilayer structure, the dielectric constant of the barrier layer 303 is increased, thereby enhancing the electric field distributed to the tunneling oxide layer and thus strengthening the coupling effect of writing and erasing the device structure. In addition, the first silicon oxide layer and the second silicon oxide layer can bond well with the substrate, while the silicon nitride layer, located in the middle, can block the propagation of defects (such as pinholes). Therefore, the three-layer structure design can complement each other.

[0105] Please continue referring to Figure 16. In this embodiment, after forming the common source layer 304, the first drain layer 305, and the second drain layer 306, and before forming the barrier layer 303, a gate dielectric layer 315 needs to be formed. The gate dielectric layer 315 is located at the position corresponding to the word line layer and the channel region formed subsequently. Part of the gate dielectric layer 315 is the tunneling oxide material layer that has not been etched away, while the other part of the gate dielectric layer 315 needs to be formed through a deposition-then-etch process.

[0106] Please refer to Figure 17. After the barrier layer 303 is formed, a word line layer 307 is formed in the trench 3002. The word line layer 307 covers the first floating gate structure 301 and the second floating gate structure 302.

[0107] In this embodiment, the word line layer 307 is an integral structure. The word line layer 307 extends along a second direction (not shown) and simultaneously covers both the first floating gate structure 301 and the second floating gate structure 302. The first direction X is perpendicular to the second direction Y. That is, adjacent first floating gate structures 301 and second floating gate structures 302 share one word line layer 307, giving the word line layer 307 a larger forming space, thereby increasing its volume and effectively reducing its resistance. Furthermore, the increased volume of the word line layer 307 enhances its control over the first floating gate structure 301 and the second floating gate structure 302, thereby improving the coupling effect of the device structure.

[0108] In this embodiment, the height of the gate dielectric layer 315 shall not exceed the height of the barrier layer 303 located on the top surface of the first floating gate structure 301 and the second floating gate structure 302, and the height of the gate dielectric layer 315 shall be sufficient to ensure that there is no obvious coupling between the word line layer 307 and the common source layer 304.

[0109] In this embodiment, the word line layer 307 is made of polysilicon, silicon nitride, or other storage materials, with thinner materials being preferred while still meeting storage capacity requirements.

[0110] In this embodiment, the top surface of the word line layer 307 is lower than the top surface of the second region II. This increases the spacing between the word line layer 307 and the conductive plugs subsequently formed on the first drain layer 305 and the second drain layer 306, thereby reducing the coupling capacitance between the word line layer 307 and the conductive plugs.

[0111] In this embodiment, the method for fabricating the word line layer 307 includes: forming a word line material layer (not shown) on the substrate 300, the word line material layer covering the barrier layer 303, the first floating gate structure 301 and the second floating gate structure 302; and performing patterned etching on the word line material layer to form the word line layer 307.

[0112] Please continue referring to Figure 17. In this embodiment, after forming the word line layer 307, the method further includes forming a metal contact layer 308 (i.e., a metal silicide layer) on the word line layer 307. The metal contact layer 308 reduces the contact resistance between the conductive plug and the word line layer 307.

[0113] Please refer to Figures 18 to 20. Figure 18 is a top view of the device omitting the metal contact layer 308, the first conductive plug 311, and the second conductive plug 312. Figure 19 is a cross-sectional view along the DD line in Figure 18. Figure 20 is a cross-sectional view along the EE line in Figure 18. After the word line layer 307 is formed, a bit line layer is formed. The bit line layer is electrically connected to the first drain layer 305 and the second drain layer 306.

[0114] In this embodiment, the bit line layer is a split structure; the bit line layer includes: a first sub-bit line layer 309, which extends along the first direction X and is electrically connected to the first drain layer 305; and a second sub-bit line layer 310, which extends along the first direction X and is electrically connected to the second drain layer 306.

[0115] Please continue to refer to Figures 18 to 20, and in conjunction with Figure 21, in this embodiment, the method for electrically connecting the first bit line layer 309 to the first drain layer 305 and the second bit line layer 310 to the second drain layer 306 includes: forming a first conductive plug 311 and a second conductive plug 312, wherein the first conductive plug 311 is electrically connected to the first drain layer 305 and the second conductive plug 312 is electrically connected to the second drain layer 306; forming a third conductive plug 313 and a fourth conductive plug 314, wherein the third conductive plug 313 is electrically connected to the first conductive plug 311 and the first bit line layer 309 respectively, and the fourth conductive plug 314 is electrically connected to the second conductive plug 312 and the second bit line layer 310 respectively.

[0116] It should be noted that, in this embodiment, during the formation of the first conductive plug 311, the second conductive plug 312, the third conductive plug 313, the fourth conductive plug 314, the first bit line layer 309, and the second bit line layer 310, a corresponding interlayer dielectric layer (not shown) also needs to be formed on the substrate 300. The first conductive plug 311, the second conductive plug 312, the third conductive plug 313, the fourth conductive plug 314, the first bit line layer 309, and the second bit line layer 310 are all formed by patterning and etching the interlayer dielectric layer and then filling it with metal.

[0117] Please continue to refer to Figure 21. The first conductive plug 311 has a first axis of symmetry (not shown) extending along the first direction X, and the second conductive plug 312 has a second axis of symmetry (not shown) extending along the first direction X. The first axis of symmetry coincides with the second axis of symmetry. The third conductive plug 313 is in partial contact with the first conductive plug 311. The fourth conductive plug 314 is in partial contact with the second conductive plug 312.

[0118] In other embodiments, the first conductive plug has a first axis of symmetry extending along the first direction, the second conductive plug has a second axis of symmetry extending along the first direction, and the first axis of symmetry and the second axis of symmetry do not coincide; the third conductive plug is in complete contact with the first conductive plug; and the fourth conductive plug is in complete contact with the second conductive plug.

[0119] In this embodiment, the first bit line layer 309 and the second bit line layer 310 are formed simultaneously; the method for manufacturing the first bit line layer 309 and the second bit line layer 310 includes: forming a first bit line groove (not shown) and a second bit line groove (not shown); forming the first bit line layer 309 in the first bit line groove and forming the second bit line layer 310 in the second bit line groove.

[0120] It should be noted that, in this embodiment, both the first bit groove and the second bit groove are formed after etching the interlayer dielectric layer. If the exposure capability allows, the formation process of the first bit groove and the second bit groove can be based on direct exposure; if the exposure capability does not allow, the formation process of the first bit groove and the second bit groove can adopt a self-aligned double patterning (SADP) process.

[0121] Accordingly, this embodiment of the invention also provides a memory cell 30, please continue to refer to Figures 18 to 21, including: a substrate 300, the substrate 300 having an active region 3001 extending along a first direction X, the active region 3001 including a first region I and a second region II located on the first region I, the second region II having a trench 3002; a first floating gate structure 301 and a second floating gate structure 302 arranged along the first direction X within the trench 3002, the first floating gate structure 301 and the second floating gate structure 302 covering part of the sidewalls and part of the bottom surface of the trench 3002; a barrier layer 303 located on the surface of the first floating gate structure 301 and the surface of the second floating gate structure 302; and a barrier layer 303 located within the first region I. A common source layer 304, and a first drain layer 305 and a second drain layer 306 located in the second region II, wherein the first drain layer 305 and the common source layer 304 are located on both sides of the first floating gate structure 301, the second drain layer 306 and the common source layer 304 are located on both sides of the second floating gate structure 302, the common source layer 304 is located between the first floating gate structure 301 and the second floating gate structure 302, and the first drain layer 305 and the second drain layer 306 are located on both sides of the trench 3002; a word line layer 307 located in the trench 3002, the word line layer 307 covering the first floating gate structure 301 and the second floating gate structure 302; and a bit line layer electrically connected to the first drain layer 305 and the second drain layer 306.

[0122] The first floating grid structure 301 and the second floating grid structure 302 are located within the trench 3002, and the first floating grid structure 301 and the second floating grid structure 302 cover part of the sidewall and part of the bottom surface of the trench 3002, so that the trenches formed by the first floating grid structure 301 and the second floating grid structure 302 are arc-shaped structures, thereby increasing the size of the trench area and enhancing the coupling effect of the word line layer 307 to the trench, thereby improving the writing and erasing efficiency.

[0123] In this embodiment, the word line layer 307 is an integral structure. The word line layer 307 extends along the second direction Y, simultaneously covering both the first floating gate structure 301 and the second floating gate structure 302. The first direction X is perpendicular to the second direction Y. That is, adjacent first floating gate structures 301 and second floating gate structures 302 share one word line layer 307, giving the word line layer 307 a larger forming space, thereby increasing its volume and effectively reducing its resistance. Furthermore, the increased volume of the word line layer 307 enhances its control over the first floating gate structure 301 and the second floating gate structure 302, thereby improving the coupling effect of the device structure.

[0124] In this embodiment, the bit line layer is a split structure; the bit line layer includes: a first sub-bit line layer 309, which extends along the first direction X and is electrically connected to the first drain layer 305; and a second sub-bit line layer 310, which extends along the first direction X and is electrically connected to the second drain layer 306.

[0125] In this embodiment, it further includes: a first conductive plug 311, which is electrically connected to the first drain layer 305; a second conductive plug 312, which is electrically connected to the second drain layer 306; a third conductive plug 313, which is electrically connected to the first conductive plug 311 and the first bit line layer 309 respectively; and a fourth conductive plug 314, which is electrically connected to the second conductive plug 312 and the second bit line layer 310 respectively.

[0126] In this embodiment, the first conductive plug 311 has a first axis of symmetry extending along the first direction X, the second conductive plug 312 has a second axis of symmetry extending along the first direction X, and the first axis of symmetry coincides with the second axis of symmetry; the third conductive plug 313 is in partial contact with the first conductive plug 311; and the fourth conductive plug 314 is in partial contact with the second conductive plug 312.

[0127] In other embodiments, the first conductive plug has a first axis of symmetry extending along the first direction, the second conductive plug has a second axis of symmetry extending along the first direction, and the first axis of symmetry and the second axis of symmetry do not coincide; the third conductive plug is in complete contact with the first conductive plug; and the fourth conductive plug is in complete contact with the second conductive plug.

[0128] Figure 22 is a schematic diagram of the structure of the storage array in an embodiment of the present invention; Figure 23 is a schematic diagram of the circuit structure of the storage array in an embodiment of the present invention.

[0129] Accordingly, this embodiment of the invention also provides a memory array 40. Please continue to refer to FIG10, and in conjunction with FIG22 and FIG23, it includes: a plurality of memory groups 400 arranged in parallel along a first direction X, each memory group including a plurality of memory cells 20 as described in any of the above embodiments, the plurality of memory cells 20 being arranged along a second direction Y, the first direction X being perpendicular to the second direction Y; wherein, in each memory group 400, the plurality of memory cells 20 share the word line layer (i.e., the first sub-word line layer 207 and the second sub-word line layer 208); in each memory group 400, the common source layer 204 of the plurality of memory cells 20 is electrically connected; adjacent memory groups 400 are mirror-symmetrically distributed; adjacent memory groups 400 share the first drain layer 205 or the second drain layer 206; adjacent memory groups 400 share the bit line layer 210.

[0130] The first floating grid structure 201 and the second floating grid structure 202 are located within the trench 2002, and the first floating grid structure 201 and the second floating grid structure 202 cover part of the sidewall and part of the bottom surface of the trench 2002, so that the trenches formed by the first floating grid structure 201 and the second floating grid structure 202 are arc-shaped structures, thereby increasing the size of the trench area and enhancing the coupling effect of the subsequently formed word line layer on the trench, thereby improving the writing and erasing efficiency.

[0131] In this embodiment, each storage transistor in the memory array 40 can be read and written independently, providing full random access functionality.

[0132] Figure 24 is a schematic diagram of the structure of the storage array in another embodiment of the present invention; Figure 25 is a schematic diagram of the circuit structure of the storage array in another embodiment of the present invention.

[0133] Accordingly, this embodiment of the invention also provides a memory array 50. Please continue to refer to Figures 18 to 20, and in conjunction with Figures 24 and 25, it includes: a plurality of memory groups 500 arranged in parallel along a first direction X, each group of memory including a plurality of memory cells 30 as described in any of the above embodiments, the plurality of memory cells 30 being arranged along a second direction Y, the first direction X being perpendicular to the second direction Y; wherein, in each group of memory groups 500, the plurality of memory cells 30 share the word line layer 307; in each group of memory groups 500, the common source layer 304 of the plurality of memory cells 30 is electrically connected; adjacent memory groups 500 are mirror-symmetrically distributed; adjacent memory groups 500 share the first drain layer 305 or the second drain layer 306; adjacent memory groups 500 share the bit line layer (i.e., the first sub-bit line layer 309 and the second sub-bit line layer 310).

[0134] The first floating grid structure 301 and the second floating grid structure 302 are located within the trench 3002, and the first floating grid structure 301 and the second floating grid structure 302 cover part of the sidewall and part of the bottom surface of the trench 3002, so that the trenches formed by the first floating grid structure 301 and the second floating grid structure 302 are arc-shaped structures, thereby increasing the size of the trench area and enhancing the coupling effect of the word line layer 307 to the trench, thereby improving the writing and erasing efficiency.

[0135] Furthermore, the adjacent first floating gate structure 301 and second floating gate structure 302 share one word line layer 307, allowing the word line layer 307 to have a larger formation space, thereby increasing the volume of the word line layer 307 and effectively reducing its resistance. Additionally, the increased volume of the word line layer 307 enhances the control over the first floating gate structure 301 and the second floating gate structure 302, thereby improving the coupling effect of the device structure.

[0136] In this embodiment, each storage transistor in the memory array 50 can be read and written independently, providing full random access functionality.

[0137] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A storage unit, characterized in that, Includes: a substrate having an active region extending along a first direction, the active region including a first region and a second region located on the first region, the second region having a trench; A first floating grid structure and a second floating grid structure are arranged along the first direction within the trench, and the first floating grid structure and the second floating grid structure cover part of the sidewall and part of the bottom surface of the trench. A barrier layer located on the surface of the first floating grid structure and the surface of the second floating grid structure; a common source layer located in the first region, and a first drain layer and a second drain layer located in the second region, wherein the first drain layer and the common source layer are located on both sides of the first floating grid structure, the second drain layer and the common source layer are located on both sides of the second floating grid structure, the common source layer is located between the first floating grid structure and the second floating grid structure, and the first drain layer and the second drain layer are located on both sides of the trench; A word line layer located within the trench, the word line layer covering the first floating gate structure and the second floating gate structure; The bitline layer is electrically connected to the first drain layer and the second drain layer.

2. The storage unit as claimed in claim 1, characterized in that, The word line layer is an integral structure; the word line layer extends along the second direction, and the word line layer simultaneously covers the first floating gate structure and the second floating gate structure, with the first direction being perpendicular to the second direction.

3. The storage unit as described in claim 2, characterized in that, The bit line layer has a split structure; the bit line layer includes: a first sub-bit line layer, which extends along the first direction and is electrically connected to the first drain layer; and a second sub-bit line layer, which extends along the first direction and is electrically connected to the second drain layer.

4. The storage unit as claimed in claim 1, characterized in that, The word line layer has a split structure; the word line layer includes: a first sub-word line layer, which extends along a second direction and covers the first floating gate structure, the first direction being perpendicular to the second direction; and a second sub-word line layer, which extends along the second direction and covers the second floating gate structure.

5. The storage unit as described in claim 4, characterized in that, The bit line layer is an integral structure; the bit line layer extends along the first direction, and the bit line layer is electrically connected to both the first drain layer and the second drain layer.

6. The storage unit as claimed in claim 1, characterized in that, The top surface of the word line layer is lower than the top surface of the second area.

7. The storage unit as claimed in claim 3, characterized in that, Also includes: A first conductive plug, which is electrically connected to the first drain layer; The second conductive plug is electrically connected to the second drain layer; The third conductive plug is electrically connected to the first conductive plug and the first sub-bit line layer respectively; The fourth conductive plug is electrically connected to the second conductive plug and the second sub-bit line layer, respectively.

8. The storage unit as claimed in claim 7, characterized in that, The first conductive plug has a first axis of symmetry extending along the first direction, and the second conductive plug has a second axis of symmetry extending along the first direction, wherein the first axis of symmetry coincides with the second axis of symmetry. The third conductive plug is in partial contact with the first conductive plug; the fourth conductive plug is in partial contact with the second conductive plug.

9. The storage unit as claimed in claim 7, characterized in that, The first conductive plug has a first axis of symmetry extending along the first direction, the second conductive plug has a second axis of symmetry extending along the first direction, and the first axis of symmetry and the second axis of symmetry do not coincide; the third conductive plug is in complete contact with the first conductive plug; and the fourth conductive plug is in complete contact with the second conductive plug.

10. A method for manufacturing a storage unit, characterized in that, include: A substrate is provided having an active region extending along a first direction, the active region including a first region and a second region located on the first region, the second region having a trench; a first floating gate structure and a second floating gate structure arranged along the first direction are formed in the trench, the first floating gate structure and the second floating gate structure covering a portion of the sidewalls and a portion of the bottom surface of the trench; a barrier layer is formed on the surface of the first floating gate structure and the surface of the second floating gate structure; a common source layer is formed in the first region, and a first drain layer and a second drain layer are formed in the second region, the first drain layer and the common source layer being located on both sides of the first floating gate structure, the second drain layer and the common source layer being located on both sides of the second floating gate structure, the common source layer being located between the first floating gate structure and the second floating gate structure, and the first drain layer and the second drain layer being located on both sides of the trench; A word line layer is formed within the trench, the word line layer covering the first floating gate structure and the second floating gate structure; A bitline layer is formed, which is electrically connected to the first drain layer and the second drain layer.

11. The method for manufacturing a storage cell as described in claim 10, characterized in that, The word line layer is an integral structure; the word line layer extends along the second direction, and the word line layer simultaneously covers the first floating gate structure and the second floating gate structure, with the first direction being perpendicular to the second direction.

12. The method for manufacturing a storage cell as described in claim 11, characterized in that, The bit line layer has a split structure; the bit line layer includes: a first sub-bit line layer, which extends along the first direction and is electrically connected to the first drain layer; and a second sub-bit line layer, which extends along the first direction and is electrically connected to the second drain layer.

13. The method for manufacturing a storage cell as described in claim 10, characterized in that, The word line layer has a split structure; the word line layer includes: a first sub-word line layer, which extends along a second direction and covers the first floating gate structure, the first direction being perpendicular to the second direction; and a second sub-word line layer, which extends along the second direction and covers the second floating gate structure.

14. The method for manufacturing a storage cell as described in claim 13, characterized in that, The bit line layer is an integral structure; the bit line layer extends along the first direction, and the bit line layer is electrically connected to both the first drain layer and the second drain layer.

15. The method for manufacturing a storage cell as described in claim 10, characterized in that, The top surface of the word line layer is lower than the top surface of the second area.

16. The method for manufacturing a storage cell as described in claim 10, characterized in that, The first floating gate structure and the second floating gate structure are formed simultaneously; The method for fabricating the first floating gate structure and the second floating gate structure includes: forming a floating gate material layer on the trench; and performing a self-aligned etching process on the floating gate material layer to form the first floating gate structure and the second floating gate structure.

17. The method for manufacturing a storage cell as described in claim 12, characterized in that, The method for electrically connecting the bit line layer to the first drain layer and the second drain layer includes: forming a first conductive plug and a second conductive plug, wherein the first conductive plug is electrically connected to the first drain layer and the second conductive plug is electrically connected to the second drain layer; forming a third conductive plug and a fourth conductive plug, wherein the third conductive plug is electrically connected to the first conductive plug and the first sub-bit line layer respectively, and the fourth conductive plug is electrically connected to the second conductive plug and the second sub-bit line layer respectively.

18. The method for manufacturing a storage cell as described in claim 17, characterized in that, The first conductive plug has a first axis of symmetry extending along the first direction, and the second conductive plug has a second axis of symmetry extending along the first direction, wherein the first axis of symmetry coincides with the second axis of symmetry. The third conductive plug is in partial contact with the first conductive plug; the fourth conductive plug is in partial contact with the second conductive plug.

19. The method for manufacturing a storage cell as described in claim 17, characterized in that, The first conductive plug has a first axis of symmetry extending along the first direction, the second conductive plug has a second axis of symmetry extending along the first direction, and the first axis of symmetry and the second axis of symmetry do not coincide; the third conductive plug is in complete contact with the first conductive plug; and the fourth conductive plug is in complete contact with the second conductive plug.

20. A storage array, characterized in that, include: A plurality of memory groups are arranged in parallel along a first direction, each group comprising a plurality of memory cells as described in any one of claims 1 to 9, the plurality of memory cells being arranged along a second direction, the first direction being perpendicular to the second direction; wherein, in each group of memory groups, the plurality of memory cells share the word line layer; in each group of memory groups, the common source layer of the plurality of memory cells is electrically connected; adjacent memory groups are mirror-symmetrically distributed; adjacent memory groups share the first drain layer or the second drain layer; adjacent memory groups share the bit line layer.

Images