Display module and display device

Abstract

The application provides a display module and a display device, and relates to the technical field of display; the display module comprises an array layer and a light-emitting layer located on one side of the array layer; the array layer comprises a plurality of drive transistors, the drive transistors comprise a first transistor and a second transistor; the light-emitting layer comprises an anode layer, the anode layer comprises anode units corresponding to the drive transistors one by one; the anode units comprise a first type of anode unit and a second type of anode unit; the first type of anode unit is arranged in correspondence with the first transistor, and the second type of anode unit is arranged in correspondence with the second transistor; the second type of anode unit comprises a body unit and an extension unit; along the thickness direction of the display module, a first gate of the first transistor at least partially overlaps the first type of anode unit, and a second gate of the second transistor at least partially overlaps the extension unit; so that the gates of all the drive transistors can have almost the same overlapping area with the anode layer of the light-emitting layer arranged in correspondence, the capacitance difference is avoided, and the display effect is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, more particularly, to a display module and a display device. BACKGROUND

[0002] In the prior art, in an OLED (Organic Electroluminescence Display) product, a LTPS array (Low Temperature Poly-Silicon array) circuit is designed on the lower side of an OLED light-emitting area, and there is an overlapping area between the OLED anode and the array circuit in vertical projection. The anode corresponding to an OLED light-emitting sub-pixel overlaps with a signal line in the array circuit, and thus a parasitic capacitance is generated in the working process of the display module. When the overlapping area of the anodes of odd-numbered columns and even-numbered columns with a first node in the array circuit is different, the capacitances of the fourth node and the first node of the odd-numbered columns and the even-numbered columns are different, which leads to uneven display and causes a phenomenon similar to uneven vertical stripes. SUMMARY

[0003] Therefore, the present application provides a display module and a display device to improve the uneven display problem of the display device.

[0004] In a first aspect, the present application provides a display module, comprising an array layer and a light-emitting layer, wherein the light-emitting layer is located on the side of the array layer facing the light-out surface of the display module.

[0005] The array layer comprises a plurality of drive transistors, and the drive transistors comprise a first transistor and a second transistor.

[0006] The light-emitting layer comprises an anode layer, and the anode layer comprises anode units corresponding to the drive transistors one by one. The anode units comprise first-type anode units and second-type anode units. The first-type anode units are arranged corresponding to the first transistors, and the second-type anode units are arranged corresponding to the second transistors.

[0007] The second-type anode units comprise a body unit and an extension unit connected electrically.

[0008] In the thickness direction of the display module, the first gate of the first transistor at least partially overlaps with the first-type anode units, and the second gate of the second transistor at least partially overlaps with the extension units, and the second gate of the second transistor does not overlap with the body units.

[0009] In a second aspect, the present application provides a display device comprising the display module.

[0010] Compared with the prior art, the display module and the display device provided by the application at least achieve the following beneficial effects:

[0011] The application provides a display module and a display device. The first transistor and the second transistor in different columns are respectively arranged to correspond to the first type of anode unit and the second type of anode unit, and the second type of anode unit comprises a body unit and an extension unit connected in an electrically connected manner, so that the first gate of the first transistor and the corresponding first type of anode unit have a partial overlapping area, and the second gate of the second transistor and the extension unit of the corresponding second type of anode unit have a partial overlapping area. In this way, the gate of the driving transistor in different columns can have almost the same overlapping area with the anode layer in the corresponding light-emitting layer, avoiding the problem of the capacitance difference between the light-emitting layer arranged in different columns and the array circuit, thereby improving the display uniformity of the display device.

[0012] Of course, implementing any product of the application does not necessarily require all the technical effects described above.

[0013] Other features and advantages of the application will become apparent from the following detailed description of exemplary embodiments of the application with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0014] The accompanying drawings incorporated in and forming a part of the specification illustrate embodiments of the application and, together with the description, serve to explain the principles of the application.

[0015] Figure 1 A perspective view of a display module in the prior art is shown;

[0016] Figure 2 A perspective view of a display module provided by an embodiment of the application is shown;

[0017] Figure 3 A cross-sectional view of AA' in the display module provided by an embodiment of the application is shown; Figure 2

[0018] Figure 4 A cross-sectional view of BB' in the display module provided by an embodiment of the application is shown; Figure 2

[0019] A top view of the third metal piece and the first gate provided by an embodiment of the application is shown; Figure 5

[0020] A top view of the third metal piece and the second gate provided by an embodiment of the application is shown; Figure 6

[0021] ​​Figure 7 FIG. 4 shows another cross-sectional view of the AA' in the embodiment provided by the present application. Figure 2

[0022] Figure 8 FIG. 5 shows another cross-sectional view of the BB' in the embodiment provided by the present application. Figure 2

[0023] Figure 9 FIG. 6 shows a top view of the fourth metal member and the first gate in the embodiment provided by the present application.

[0024] Figure 10 FIG. 7 shows a top view of the fourth metal member and the second gate in the embodiment provided by the present application.

[0025] Figure 11 FIG. 8 shows a schematic view of the display device in the embodiment provided by the present application. DETAILED DESCRIPTION

[0026] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of the components and steps set forth in the examples, numerical expressions, and numerical values are not limiting to the scope of the present application unless otherwise specifically stated.

[0027] The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the scope of the application, its application, or uses.

[0028] Techniques, methods, and devices known to those of ordinary skill in the relevant art can not be discussed in detail herein. However, the techniques, methods, and devices should be considered part of the specification, if appropriate.

[0029] In all of the examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not limiting. Thus, other examples of the exemplary embodiments can have different values.

[0030] It should be noted that like numbers and letters refer to like items throughout the drawings, and once an item is defined in one drawing, that item does not need to be discussed further in subsequent drawings.

[0031] ​​In the prior art, in an OLED (Organic Electroluminescence Display) product, an LTPS array (Low Temperature Poly-Silicon array) circuit is designed on the lower side of an OLED light-emitting area, and the OLED anode and the array circuit are overlapped in vertical projection; the anode corresponding to an OLED light-emitting sub-pixel and the signal line in the array circuit are overlapped, and thus a parasitic capacitance is generated in the working process of the display module; when the coverage areas of the anodes of the odd-numbered columns and the even-numbered columns and the first nodes in the array circuit are different, the capacitances of the fourth nodes and the first nodes of the odd-numbered columns and the even-numbered columns are different, which causes uneven display and generates a vertical stripe defect.

[0032] Therefore, the present application provides a display module and a display device to improve the uneven display problem of the display device.

[0033] Figure 1 Fig. 1 shows a perspective view of a display module in the prior art, Figure 2 Fig. 2 shows a perspective view of a display module provided by the present application, Figure 3 Fig. 3 shows a sectional view of AA' in Fig. 2, Figure 2 Fig. 4 shows a sectional view of BB' in Fig. 2, please refer to Fig. 2, Figure 4 Fig. 5 shows a sectional view of CC' in Fig. 2, please refer to Fig. 2, Figure 2 Fig. 6 shows a sectional view of DD' in Fig. 2, please refer to Fig. 2, Figures 1-4 The present application provides a display module 100, which comprises an array layer 41 and a light-emitting layer 42, and the light-emitting layer 42 is located on the side of the light-emitting surface of the display module 100.

[0034] The array layer 41 comprises a plurality of driving transistors, and the driving transistors comprise a first transistor and a second transistor;

[0035] The light-emitting layer 42 comprises an anode layer, and the anode layer comprises anode units 10 corresponding to the driving transistors one by one; the anode units 10 comprise first-type anode units 11 and second-type anode units 12; the first-type anode units 11 are arranged corresponding to the first transistors, and the second-type anode units 12 are arranged corresponding to the second transistors;

[0036] The second-type anode units 12 comprise body units 121 and extension units 122 connected electrically;

[0037] In the thickness direction of the display module 100, the first gate 21 of the first transistor at least partially overlaps the first-type anode units 11, the second gate 22 of the second transistor at least partially overlaps the extension units 122, and the second gate 22 of the second transistor does not overlap the body units 121.

[0038] Specifically, such as Figure 1 As shown, in the prior art display module 01, among the multiple columns of sub-pixels arranged adjacent to each other along the first direction, the anode K of the sub-pixels in the odd-numbered column L1 and the corresponding gate G1 of the driving transistor have a relatively large overlap area. However, the anode K of the sub-pixels in the even-numbered column L2 and the corresponding gate G1 of the driving transistor have no overlap area or only a very small overlap area. Therefore, it is obvious that the overlap area of ​​the anode K of each sub-pixel in the prior art display module 01 with its corresponding gate G1 of the driving transistor is different. This will cause the coverage area of ​​the anode K of the odd-numbered column L1 and the even-numbered column L2 sub-pixels with the first node in the array circuit to be different. In turn, it will cause the capacitance of the fourth node and the first node in the pixel circuit of the odd-numbered column L1 and the even-numbered column L2 to be different. The capacitance difference between different pixel circuits electrically connected to different sub-pixels will cause the display effect of different sub-pixels to be uneven, resulting in a poor overall display effect of the corresponding display device, such as obvious vertical lines.

[0039] Therefore, as Figures 2-4 As shown, this application provides an optional configuration in which the display module 100 includes an array layer 41 and a light-emitting layer 42 located on the side of the array layer 41 facing the light-emitting surface of the display module 100. The display module 100 includes multiple light-emitting elements, the array layer 41 includes multiple driving transistors corresponding to each light-emitting element, and the anode layer in the light-emitting layer 42 includes multiple anode units 10 corresponding to each light-emitting element. This application classifies the driving transistors into first transistors and second transistors, and the anode units 10 into first-type anode units 11 and second-type anode units 12 for description. The first-type anode units 11 are corresponding to the first transistors, and the second-type anode units 12 are corresponding to the second transistors. The arrangement of the first-type anode units 11 and the first transistors corresponds to the arrangement of odd-numbered columns of sub-pixel anodes and their corresponding driving transistors in the prior art. The second-type anode unit 12 provided in this application includes an electrically connected body unit 121 and an extension unit 122. The arrangement of the body unit 121 and the second transistors corresponds to the arrangement of even-numbered columns of sub-pixel anodes and their corresponding driving transistors in the prior art.

[0040] Obviously, the display module 100 provided by the present application is different from the prior art in that the second anode unit 12 provided by the present application further comprises an extension unit 122 electrically connected to the body unit 121; therefore, the display module 100 can be arranged in such a manner that the first gate 21 of the first transistor at least partially overlaps the first anode unit 11, the second gate 22 of the second transistor at least partially overlaps the extension unit 122, and the second gate 22 of the second transistor does not overlap the body unit 121 along the thickness direction of the display module 100. The addition of the extension unit 122 of the second anode unit 12 makes the second gate 22 of the second transistor and the corresponding second anode unit 12 have a large enough overlapping area in the orthographic projection, so that the first anode unit 11 and the first gate 21 of the corresponding first transistor, and the second anode unit 12 and the second gate 22 of the corresponding second transistor, can have a similar overlapping area in the orthographic projection, so that the anode of all the sub-pixels in the display module 100 and the gate of the corresponding driving transistor have a similar overlapping area in the orthographic projection, avoiding the problem of large capacitance difference between the light-emitting layer 42 and the array circuit arranged in different columns, thereby improving the display uniformity of the display device.

[0041] Please continue to refer to Figures 2-4 As Figure 2 shown, the anode unit 10 shown in the figure has three different sizes, of which the smallest size may, for example, be the anode unit 10 corresponding to the red light-emitting unit 51, the middle size may, for example, be the anode unit 10 corresponding to the green light-emitting unit 52, and the largest size may, for example, be the anode unit 10 corresponding to the blue light-emitting unit 53. Alternatively, the light-emitting layer 42 comprises a plurality of light-emitting units, each of which comprises an anode unit 10.

[0042] The light-emitting unit comprises a green light-emitting unit 52; the anode unit 10 corresponding to the green light-emitting unit 52 is a second anode unit 12.

[0043] Specifically, the display module 100 provided by the present application comprises a plurality of light-emitting units in the light-emitting layer 42, and the display color of the light-emitting unit may, for example, comprise at least red, green and blue, i.e. red light-emitting unit 51, green light-emitting unit 52 and blue light-emitting unit 53; wherein each light-emitting unit has a corresponding anode unit 10.

[0044] Based on this, the application provides an alternative setting mode, that is, the anode unit 10 corresponding to the green light emitting unit 52 in the light emitting unit is the second type of anode unit 12. Since the display module 01 in the prior art includes at least red, green and blue light emitting units, for example, the green light emitting unit is generally the light emitting unit corresponding to the even column sub-pixel, that is, the green light emitting unit is most likely to have the problem that there is no overlapping area between the gate of the driving transistor arranged corresponding to the green light emitting unit, therefore, the application sets the second type of anode unit 12 corresponding to the green light emitting unit 52 has a body unit 121 and an extension unit 122, which can make the anode of all sub-pixels included in the display module 100 and the gate of the driving transistor arranged corresponding to the anode have a small difference in the positive projection overlapping area, avoiding the problem that the light emitting layer 42 arranged in different columns and the array circuit have a large capacitance difference, thereby improving the display uniformity of the display device.

[0045] Please continue to refer to Figures 2-4 Optionally, the array layer 41 includes a first metal layer M1, a second metal layer M2 and a third metal layer M3; the second metal layer M2 is located between the first metal layer M1 and the third metal layer M3;

[0046] The second gate 22 is located in the first metal layer M1;

[0047] The second metal layer M2 includes a plurality of second metal pieces 62 arranged corresponding to the second gate 22, and the third metal layer M3 includes a plurality of third metal pieces 63 arranged corresponding to the second gate 22;

[0048] At least part of the third metal piece 63 is electrically connected to the corresponding second gate 22 through the corresponding second metal piece 62.

[0049] Specifically, the application provides a structure of the array layer 41 in the display module 100, which includes, from bottom to top, a substrate Buffer, a first insulating layer GI1, a dielectric insulating layer IMD, a first interlayer insulating layer ILD1, a second insulating layer GI2, a third insulating layer GI3, a second interlayer insulating layer ILD2, a first planar layer PLN1, a second planar layer PLN2, and a BPL, and further includes a first metal layer M1, a second metal layer M2 and a third metal layer M3 arranged in sequence along the light emitting direction of the display module 100, wherein the first metal layer M1 can be arranged in the dielectric insulating layer IMD, the second metal layer M2 can be arranged in the first planar layer PLN1, and the third metal layer M3 can be arranged in the second planar layer PLN2.

[0050] The application provides an alternative setting mode, for example, Figure 3The second gate 22 of the second transistor is shown to be disposed in the first metal layer M1, and a plurality of second metal pieces 62 corresponding to the second gate 22 are disposed in the second metal layer M2, and a plurality of third metal pieces 63 corresponding to the second gate 22 are disposed in the third metal layer M3, and at least part of the third metal pieces 63 are electrically connected to the corresponding second gate 22 through the corresponding second metal pieces 62. That is, the third metal pieces 63 of the third metal layer M3 are used as the first node in the corresponding pixel circuit, and the third metal layer M3 and the corresponding second anode unit 12 have an overlapping area, so as to compensate for the problem of less or no overlapping area between the anode unit and the first node in the corresponding pixel circuit. Thus, the problem of large capacitance difference between the light-emitting layer 42 and the array circuit in different columns is avoided, so as to improve the display uniformity of the display device.

[0051] The first node metal involves the second metal piece 62 and the second gate 22, and the second gate 22 is generally below the plate of the capacitor 70 and cannot be directly connected, so the second metal piece 62 and the third metal piece 63 are conductive.

[0052] Please continue to refer to Figures 2-4 Optionally, the first gate 21 is located in the first metal layer M1.

[0053] The second metal layer M2 includes a plurality of second metal pieces 62 corresponding to the first gate 21, and the third metal layer M3 includes a plurality of third metal pieces 63 corresponding to the first gate 21.

[0054] At least part of the third metal pieces 63 are electrically connected to the corresponding first gate 21 through the corresponding second metal pieces 62.

[0055] Specifically, the first gate 21 in the first transistor and the second gate 22 in the second transistor can be located in the first metal layer M1, and the first gate 21 and the second gate 22 in the array layer 41 can be manufactured in the same film layer structure by the same process, which is beneficial to simplify the manufacturing process of the display module 100.

[0056] In addition, the application provides an alternative arrangement mode, that is, a plurality of second metal pieces 62 corresponding to the first gate 21 are arranged in the second metal layer M2, and a plurality of third metal pieces 63 corresponding to the first gate 21 are arranged in the third metal layer M3, and at least part of the third metal pieces 63 are electrically connected to the corresponding first gate 21 through the corresponding second metal piece 62; that is, the third metal pieces 63 in the third metal layer M3 are used as the first node in the corresponding pixel circuit, and the third metal layer M3 and the corresponding first anode unit 11 have an overlapping area. In combination with the arrangement that the third metal layer M3 and the corresponding second anode unit 12 have an overlapping area, the anode of all the sub-pixels in the display module 100 and the gate of the driving transistor arranged correspondingly have a small difference in the positive projection overlapping area, which avoids the problem that the light-emitting layer 42 arranged in different columns and the array circuit have a large difference in capacitance, thereby improving the display uniformity of the display device.

[0057] In the first node metal, the metal includes the second metal piece 62 and the second gate 22, and the second gate 22 is generally below the plate of the capacitor 70 and cannot be directly connected, so the second metal piece 62 and the third metal piece 63 are in conduction.

[0058] Figure 5 FIG. 6 shows a top view of the third metal piece and the first gate provided by the application, Figure 6 FIG. 7 shows a top view of the third metal piece and the second gate provided by the application, please refer to Figures 2-6 Optionally, the array layer 41 further includes a substrate Buffer located on the side of the first metal layer M1 away from the second metal layer M2.

[0059] The positive projection area of the third metal piece 63 on the plane of the substrate Buffer is S1, and the positive projection area of the first gate 21 or the second gate 22 on the plane of the substrate Buffer is S2, and S1 < S2.

[0060] Specifically, since the third metal layer M3 where the third metal piece 63 is located is closer to the anode unit 10 (the first anode unit 11 and the second anode unit 12), the capacitance is larger, and therefore the area of the extended third metal piece 63 can be set to be smaller than the area of the corresponding first gate 21 or second gate 22. That is, the positive projection area of the third metal piece 63 corresponding to the first gate 21 on the plane of the substrate Buffer can be set to be smaller than the positive projection area of the first gate 21 on the plane of the substrate Buffer, and the positive projection area of the third metal piece 63 corresponding to the second gate 22 on the plane of the substrate Buffer can be set to be smaller than the positive projection area of the second gate 22 on the plane of the substrate Buffer.

[0061] In addition, the shape of the third metal piece 63 is not limited in the present application, and can be designed according to actual wiring requirements.

[0062] Figure 7 Fig. 4 shows another cross-sectional view of the AA' in the embodiment provided by the present application, Figure 2 Fig. 5 shows another cross-sectional view of the BB' in the embodiment provided by the present application, and Figure 8 Fig. 6 shows another cross-sectional view of the CC' in the embodiment provided by the present application, Figure 2 Fig. 7 shows another cross-sectional view of the DD' in the embodiment provided by the present application, and Figure 2 Figure 7 Figure 8 Optionally, the array layer 41 comprises a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4; the second metal layer M2 is located between the first metal layer M1 and the third metal layer M3, and the fourth metal layer M4 is located on a side of the third metal layer M3 away from the second metal layer M2.

[0063] The second gate 22 is located in the first metal layer M1.

[0064] The second metal layer M2 comprises a plurality of second metal pieces 62 arranged correspondingly to the second gate 22, and the fourth metal layer M4 comprises a plurality of fourth metal pieces 64 arranged correspondingly to the second gate 22.

[0065] At least part of the fourth metal pieces 64 are electrically connected to the second gate 22 through the correspondingly arranged second metal pieces 62.

[0066] Specifically, the present application further provides a structure of an array layer 41 in a display module 100, comprising a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4 arranged in sequence along the light-emitting direction of the display module 100; the second gate 22 of the second transistor is made in the first metal layer M1, a plurality of second metal pieces 62 arranged correspondingly to the second gate 22 are made in the second metal layer M2, and a plurality of fourth metal pieces 64 arranged correspondingly to the second gate 22 are made in the fourth metal layer M4; at least part of the fourth metal pieces 64 are electrically connected to the second gate 22 through the correspondingly arranged second metal pieces 62. That is, the fourth metal pieces 64 of the fourth metal layer M4 are used as the first node in the corresponding pixel circuit, and the fourth metal layer M4 is arranged to have an overlapping area with the corresponding second anode unit 12, so as to compensate for the problem of less or no overlapping area between the anode unit 10 and the first node in the corresponding pixel circuit.

[0067] ​​In the existing FIAA (fanout in aa) product design, there is a fourth metal layer M4, and the fourth metal piece 64 provided in the fourth metal layer M4 is used as the first node of the corresponding pixel circuit to overlap with the corresponding anode unit 10, so as to compensate for the problem of small or no overlapping area between the anode unit 10 and the first node of the corresponding pixel circuit.

[0068] The first node metal involves the second metal piece 62 and the second gate 22, and the second gate 22 is generally below the plate of the capacitor 70 and is not directly connected, so the second metal piece 62 is conductive with the fourth metal piece 64.

[0069] Please continue to refer to Figure 2 、 Figures 5-8 Optionally, the first gate 21 is located on the first metal layer M1.

[0070] The second metal layer M2 includes a plurality of second metal pieces 62 corresponding to the first gate 21, and the fourth metal layer M4 includes a plurality of fourth metal pieces 64 corresponding to the first gate 21.

[0071] At least part of the fourth metal piece 64 is electrically connected to the corresponding first gate 21 through the corresponding second metal piece 62.

[0072] Specifically, the first gate 21 in the first transistor and the second gate 22 in the second transistor can be located on the first metal layer M1, and at this time, the first gate 21 and the second gate 22 in the array layer 41 can be made together in the same film layer structure by using the same process, which is beneficial to simplify the manufacturing process of the display module 100.

[0073] In addition, an optional setting mode is provided, that is, a plurality of second metal pieces 62 corresponding to the first gate 21 are made on the second metal layer M2, and a plurality of fourth metal pieces 64 corresponding to the first gate 21 are made on the fourth metal layer M4, and at least part of the fourth metal piece 64 is electrically connected to the corresponding first gate 21 through the corresponding second metal piece 62; that is, by using the fourth metal piece 64 of the fourth metal layer M4 as the first node in the corresponding pixel circuit, the fourth metal layer M4 is provided to have an overlapping area with the corresponding first type anode unit 11. In combination with the foregoing setting of the fourth metal layer M4 to have an overlapping area with the corresponding second type anode unit 12, the anode of all sub-pixels included in the display module 100 and the gate of the driving transistor corresponding thereto can have a small difference in the orthographic projection overlapping area, so as to avoid the problem of large capacitance difference between the light-emitting layer 42 and the array circuit arranged in different columns, thereby improving the display uniformity of the display device.

[0074] The first node metal involves the second metal piece 62 and the second gate 22, and the second gate 22 is generally below the plate of the capacitor 70 and cannot be directly connected, and thus can be connected by the second metal piece 62 and the fourth metal piece 64.

[0075] Figure 9 Fig. 4 is a top view of the fourth metal piece and the first gate according to an embodiment of the present application, Figure 10 Fig. 5 is a top view of the fourth metal piece and the second gate according to an embodiment of the present application, and Figure 2 、 Figures 7-10 Optionally, the array layer 41 further includes a substrate Buffer located on a side of the first metal layer M1 away from the second metal layer M2.

[0076] The fourth metal piece 64 has a projection area S3 on the plane of the substrate Buffer, and the first gate 21 or the second gate 22 has a projection area S2 on the plane of the substrate Buffer, and S3 < S2.

[0077] Specifically, since the fourth metal layer M4 where the fourth metal piece 64 is located is closer to the anode unit 10 (the first type of anode unit 11 and the second type of anode unit 12), the capacitance is larger, and thus the area of the extended fourth metal piece 64 can be set to be smaller than the area of the corresponding first gate 21 or second gate 22. That is, the projection area of the fourth metal piece 64 corresponding to the first gate 21 on the plane of the substrate Buffer can be set to be smaller than the projection area of the first gate 21 on the plane of the substrate Buffer, and the projection area of the fourth metal piece 64 corresponding to the second gate 22 on the plane of the substrate Buffer can be set to be smaller than the projection area of the second gate 22 on the plane of the substrate Buffer.

[0078] In addition, the shape of the fourth metal piece 64 is not limited in the present application, and can be designed according to actual wiring requirements.

[0079] Fig. 4 is a top view of the fourth metal piece and the first gate according to an embodiment of the present application, Figures 2-10 Optionally, the array layer 41 includes a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4; the second metal layer M2 is located between the first metal layer M1 and the third metal layer M3, and the fourth metal layer M4 is located on a side of the third metal layer M3 away from the second metal layer M2.

[0080] The second gate 22 is located on the first metal layer M1.

[0081] The second metal layer M2 includes a plurality of second metal pieces 62 corresponding to the second gate 22, the third metal layer M3 includes a plurality of third metal pieces 63 corresponding to the second gate 22, and the fourth metal layer M4 includes a plurality of fourth metal pieces 64 corresponding to the second gate 22.

[0082] At least part of the third metal piece 63 is electrically connected to the corresponding second gate 22 through the corresponding second metal piece 62, and at least part of the fourth metal piece 64 is electrically connected to the corresponding second gate 22 through the corresponding second metal piece 62.

[0083] Specifically, the display module 100 can be selectively arranged in the following manner: the array layer 41 includes a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4, which are sequentially stacked in the light-out direction of the display module 100; the second gate 22 of the second transistor is formed in the first metal layer M1; a plurality of second metal pieces 62 corresponding to the second gate 22 are formed in the second metal layer M2; a plurality of third metal pieces 63 corresponding to part of the second gate 22 are formed in the third metal layer M3; and a plurality of fourth metal pieces 64 corresponding to part of the second gate 22 are formed in the fourth metal layer M4, wherein the same second gate 22 is provided with only one third metal piece 63 or one fourth metal piece 64; at least part of the third metal piece 63 is electrically connected to the corresponding second gate 22 through the corresponding second metal piece 62, and at least part of the fourth metal piece 64 is electrically connected to the corresponding second gate 22 through the corresponding second metal piece 62; that is, the third metal piece 63 of part of the third metal layer M3 and / or the fourth metal piece 64 of part of the fourth metal layer M4 are used as the first node in the corresponding pixel circuit, and the third metal piece 63 and the fourth metal piece 64 are arranged to overlap with the corresponding second anode unit 12, thereby compensating for the problem of less or no overlap between the anode unit 10 and the first node in the corresponding pixel circuit. Thus, the problem of large capacitance difference between the light-emitting layer 42 and the array circuit arranged in different columns is avoided, and the display uniformity of the display device is improved.

[0084] Please continue to refer to Figures 2-10 Optionally, the first gate 21 is located in the first metal layer M1.

[0085] The second metal layer M2 includes a plurality of second metal pieces 62 corresponding to the first gate 21, the third metal layer M3 includes a plurality of third metal pieces 63 corresponding to the first gate 21, and the fourth metal layer M4 includes a plurality of fourth metal pieces 64 corresponding to the first gate 21.

[0086] At least part of the third metal piece 63 is electrically connected to the corresponding first gate 21 through the corresponding second metal piece 62, and at least part of the fourth metal piece 64 is electrically connected to the corresponding first gate 21 through the corresponding second metal piece 62.

[0087] Specifically, by the same reason, the first gate 21 of the first transistor can also be made in the first metal layer M1, and then a plurality of second metal pieces 62 corresponding to the first gate 21 are made in the second metal layer M2, and a plurality of third metal pieces 63 corresponding to part of the first gate 21 are made in the third metal layer M3, and a fourth metal piece 64 corresponding to part of the first gate 21 is made in the fourth metal layer M4, wherein the same first gate 21 is only provided with one third metal piece 63 or one fourth metal piece 64; and then at least part of the third metal piece 63 is electrically connected to the corresponding first gate 21 through the corresponding second metal piece 62, and at least part of the fourth metal piece 64 is electrically connected to the corresponding first gate 21 through the corresponding second metal piece 62; that is, the third metal piece 63 of part of the third metal layer M3 and / or the fourth metal piece 64 of part of the fourth metal layer M4 are used as the first node in the corresponding pixel circuit, and the third metal piece 63 and the fourth metal piece 64 are arranged to have an overlapping area with the corresponding first anode unit 11. In combination with the above-mentioned arrangement of the third metal piece 63 and / or the fourth metal piece 64 having an overlapping area with the corresponding second anode unit 12, the anode of all sub-pixels included in the display module 100 and the gate of the driving transistor arranged corresponding thereto can have a positive projection overlapping area with little difference, avoiding the problem of large capacitance difference between the light-emitting layer 42 arranged in different columns and the array circuit, thereby improving the display uniformity of the display device.

[0088] Among them, the first node metal involves the second metal piece 62 and the second gate 22, and the second gate 22 is generally below the lower plate of the capacitor 70 and cannot be directly connected, so it can be conducted by the second metal piece 62 and the third metal piece 63 or the fourth metal piece 64.

[0089] Please continue to refer to Figures 2-10 Optionally, the array layer 41 further includes a substrate Buffer located on the side of the first metal layer M1 away from the second metal layer M2.

[0090] The positive projection area of the third metal piece 63 in the substrate Buffer is S1, the positive projection area of the first gate 21 or the second gate 22 in the substrate Buffer is S2, and the positive projection area of the fourth metal piece 64 in the substrate Buffer is S3, S1 < S2 and S3 < S2.

[0091] Specifically, since the third metal piece 63 is located in the third metal layer M3, and the fourth metal piece 64 is located in the fourth metal layer M4, which are closer to the anode unit 10 (the first type of anode unit 11, the second type of anode unit 12), the capacitance is larger, and thus the area of the extended third metal layer M3 piece or the fourth metal piece 64 can be set to be smaller than the area of the corresponding first gate 21 and second gate 22. That is, the area of the third metal piece 63 or the fourth metal piece 64 corresponding to the first gate 21 in the normal projection plane of the substrate Buffer can be set to be smaller than the area of the first gate 21 in the normal projection plane of the substrate Buffer, and the area of the third metal piece 63 or the fourth metal piece 64 corresponding to the second gate 22 in the normal projection plane of the substrate Buffer can be set to be smaller than the area of the second gate 22 in the normal projection plane of the substrate Buffer.

[0092] In addition, the shape of the third metal piece 63 and the fourth metal piece 64 is not limited in the present application, and can be designed according to actual wiring needs.

[0093] Please continue to refer to Figures 2-10 Optionally, the third metal piece 63 and the fourth metal piece 64 do not overlap in the thickness direction of the display module 100.

[0094] Specifically, it should be noted that only one first node metal is provided corresponding to the gate of one transistor, and thus when the third metal piece 63 is provided corresponding to the gate (the first gate 21, the second gate 22), the corresponding fourth metal piece 64 does not need to be provided; similarly, when the fourth metal piece 64 is provided corresponding to the gate (the first gate 21, the second gate 22), the corresponding third metal piece 63 does not need to be provided; thus, the present application provides an optional setting mode, that is, the normal projection of the third metal piece 63 in the substrate Buffer and the normal projection of the fourth metal piece 64 in the substrate Buffer do not overlap in the thickness direction of the display module 100.

[0095] Figure 11 The figure shows a schematic diagram of a display device provided by an embodiment of the present application. Please refer to Figures 1-10 Refer to Figure 11 Based on the same inventive concept, the present application also provides a display device 200, which comprises a display module 100 provided by the present application.

[0096] It should be noted that the embodiments of the display device 200 provided by the present application can refer to the embodiments of the display module 100 described above, and repeated descriptions are not repeated. The display device 200 provided by the present application can be: mobile phones, tablet computers, televisions, notebook computers, navigation devices, and other products and components.

[0097] It can be known by the above embodiments that the display module and the display device provided by the present application at least achieve the following beneficial effects:

[0098] The present application provides a display module and a display device, by setting the first transistor and the second transistor in different columns to correspond to the first type of anode unit and the second type of anode unit respectively, and setting the second type of anode unit to include the body unit and the extension unit connected in an electric way, so that the first gate of the first transistor has a partial overlapping area with the corresponding first type of anode unit, and the second gate of the second transistor has a partial overlapping area with the extension unit of the corresponding second type of anode unit; by such setting, the driving transistor in different columns can have almost the same overlapping area with the anode layer in the corresponding set light emitting layer, avoiding the problem of capacitance difference between the light emitting layer set in different columns and the array circuit, thereby improving the display uniformity of the display device.

[0099] Although some specific embodiments of the present application have been described in detail by examples, those skilled in the art should understand that the above examples are only for illustration, not for limiting the scope of the present application. Those skilled in the art should understand that the above embodiments can be modified without departing from the scope and spirit of the present application. The scope of the present application is defined by the appended claims.

Claims

1. A display module, characterized by The display module comprises an array layer and a light-emitting layer, and the light-emitting layer is located on the side of the array layer facing the light-emitting surface of the display module. The array layer comprises a plurality of drive transistors, and the drive transistors comprise a first transistor and a second transistor. The light-emitting layer comprises an anode layer, and the anode layer comprises anode units arranged one-to-one with the drive transistors; the anode units comprise first-type anode units and second-type anode units; the first-type anode units are arranged in correspondence with the first transistors, and the second-type anode units are arranged in correspondence with the second transistors. The second-type anode units comprise body units and extension units electrically connected. In the thickness direction of the display module, a first gate of the first transistor at least partially overlaps the first-type anode units, and a second gate of the second transistor at least partially overlaps the extension units and does not overlap the body units. The first-type anode units are located in odd-numbered columns, and the body units of the second-type anode units are located in even-numbered columns. The array layer comprises a first metal layer, a second metal layer and a third metal layer; the second metal layer is located between the first metal layer and the third metal layer. The second gate is located on the first metal layer. The second metal layer comprises a plurality of second metal pieces arranged in correspondence with the second gates, and the third metal layer comprises a plurality of third metal pieces arranged in correspondence with the second gates. At least part of the third metal pieces are electrically connected with the corresponding second gates through the corresponding second metal pieces. The first gate is located on the first metal layer. The second metal layer comprises a plurality of second metal pieces arranged in correspondence with the first gates, and the third metal layer comprises a plurality of third metal pieces arranged in correspondence with the first gates. At least part of the third metal pieces are electrically connected with the corresponding first gates through the corresponding second metal pieces. The third metal pieces of the third metal layer serve as first nodes in corresponding pixel circuits, the third metal layer has an overlapping area with the corresponding second-type anode units, and the third metal layer has an overlapping area with the corresponding first-type anode units.

2. The display module of claim 1, wherein The light-emitting layer comprises a plurality of light-emitting units, and each light-emitting unit comprises an anode unit. The light-emitting units comprise green light-emitting units, and the anode units arranged in correspondence with the green light-emitting units are second-type anode units.

3. The display module of claim 1, wherein The array layer further comprises a substrate located on the side of the first metal layer away from the second metal layer. The third metal pieces have a projection area S1 on the plane of the substrate, and the first gates or the second gates have a projection area S2 on the plane of the substrate, and S1 < S2.

4. The display module of claim 1, wherein The array layer further comprises a fourth metal layer, and the fourth metal layer is located on the side of the third metal layer away from the second metal layer. The fourth metal layer comprises a plurality of fourth metal pieces arranged correspondingly to the second gate electrodes; At least part of the fourth metal pieces are electrically connected to the second gate electrodes through the second metal pieces arranged correspondingly.

5. The display module of claim 4, wherein The fourth metal layer comprises a plurality of fourth metal pieces arranged correspondingly to the first gate electrodes; At least part of the fourth metal pieces are electrically connected to the first gate electrodes through the second metal pieces arranged correspondingly.

6. The display module of claim 5, wherein The array layer further comprises a substrate located on a side of the first metal layer away from the second metal layer; A projected area of the fourth metal pieces on a plane where the substrate is located is S3, a projected area of the first gate electrodes or the second gate electrodes on the plane where the substrate is located is S2, and S3 < S2.

7. The display module of claim 1, wherein The array layer further comprises a fourth metal layer located on a side of the third metal layer away from the second metal layer; The fourth metal layer comprises a plurality of fourth metal pieces arranged correspondingly to the second gate electrodes; At least part of the third metal pieces are electrically connected to the second gate electrodes through the second metal pieces arranged correspondingly, and at least part of the fourth metal pieces are electrically connected to the second gate electrodes through the second metal pieces arranged correspondingly.

8. The display module of claim 7, wherein The fourth metal layer comprises a plurality of fourth metal pieces arranged correspondingly to the first gate electrodes; At least part of the third metal pieces are electrically connected to the first gate electrodes through the second metal pieces arranged correspondingly, and at least part of the fourth metal pieces are electrically connected to the first gate electrodes through the second metal pieces arranged correspondingly.

9. The display module of claim 8, wherein The array layer further comprises a substrate located on a side of the first metal layer away from the second metal layer; A projected area of the third metal pieces on a plane where the substrate is located is S1, a projected area of the first gate electrodes or the second gate electrodes on the plane where the substrate is located is S2, and a projected area of the fourth metal pieces on the plane where the substrate is located is S3, S1 < S2 and S3 < S2.

10. The display module of claim 7 or 8, wherein The third metal pieces and the fourth metal pieces do not overlap along a thickness direction of the display module.

11. A display device comprising: A display module as claimed in any one of claims 1-10.

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