Semiconductor devices and electronic devices

Abstract

This application provides a semiconductor device and an electronic device. The semiconductor device includes an insulating substrate, a first insulating layer and an active layer disposed on the insulating substrate. The first insulating layer has a groove, and the active layer is disposed in the groove. The active layer includes a first semiconductor layer, an active segment and a second semiconductor layer stacked on the insulating substrate. The orthographic projection of the first semiconductor layer on the insulating substrate and the orthographic projection of the second semiconductor layer on the insulating substrate partially overlap, thereby forming a semiconductor device with a vertical channel thin film transistor. This can significantly improve the aperture ratio, enhance the integration of the semiconductor device, and is beneficial for developing high PII, high refresh rate products and realizing some IC functions.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a semiconductor device and an electronic device. Background Art

[0002] Currently, flat panel display devices such as liquid crystal display (LCD) panels and organic light-emitting diode (OLED) mobile terminals are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, digital cameras, laptops, and desktop computers due to their advantages such as high image quality, power saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] In existing technologies, it is known that integrating integrated circuits (ICs) such as pixels, drivers, multiplexers, control, and logic onto a system-on-glass (SOG) substrate can improve the integration density of semiconductor devices and reduce dependence on IC chips. To achieve SOG, it is necessary to improve the integration density, maximum operating frequency, and current density of existing thin-film transistors (TFTs). Since the electrical performance of a TFT when it is conducting is related to the portion of the active layer corresponding to the source and drain (i.e., the channel length of the active layer), achieving the above effects requires a shorter channel length and a smaller volume. However, traditional TFTs are typically planar, consisting of a stacked active layer, gate, source, and drain. Because metal materials can block light and hinder light transmission, TFTs inevitably occupy a certain pixel area, resulting in a decrease in the effective display area of ​​the pixel, i.e., a decrease in aperture ratio, which limits light utilization. Therefore, how to reduce the area occupied by TFTs in the entire display panel while ensuring normal operation of the TFT device is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] This application provides a semiconductor device and an electronic device to alleviate the shortcomings of related technologies.

[0005] To achieve the above functions, the technical solutions provided in this application are as follows:

[0006] This application provides a semiconductor device, including...

[0007] Insulating substrate:

[0008] A thin-film transistor layer is located on the insulating substrate, the thin-film transistor layer comprising:

[0009] A first insulating layer is disposed on the insulating substrate, and the first insulating layer has a groove formed thereon;

[0010] An active layer is disposed within the groove. The active layer includes a first semiconductor layer, an active segment, and a second semiconductor layer stacked together, wherein the orthographic projection of the first semiconductor layer on the insulating substrate and the orthographic projection of the second semiconductor layer on the insulating substrate partially overlap.

[0011] In the semiconductor device provided in the embodiments of this application, the first insulating layer includes steps disposed on both sides of the groove, and the active layer includes a first portion located in the groove and a second portion extending from the groove to the upper surface of the steps.

[0012] In the semiconductor device provided in the embodiments of this application, the semiconductor device includes a gate located on the side of the active layer away from the insulating substrate, the gate being insulated from the active layer, and the active layer including a side surface located on the upper surface of the step;

[0013] The gate is disposed on at least one side of the side surface, and the orthogonal projection of the gate on the side surface covers the active segment.

[0014] In the semiconductor device provided in the embodiments of this application, the gate is disposed around the active layer.

[0015] In the semiconductor device provided in the embodiments of this application, the angle between the side surface and the upper surface of the step is greater than or equal to 30 degrees and less than or equal to 80 degrees.

[0016] In the semiconductor device provided in the embodiments of this application, the semiconductor device layer further includes a source and a drain stacked together;

[0017] In this configuration, one of the source and the drain is located on the side of the active layer closer to the insulating substrate, and the other of the source and the drain is located on the side of the active layer away from the insulating substrate. The orthographic projection of the source on the insulating substrate at least coincides with the orthographic projection of a portion of the drain on the insulating substrate.

[0018] In the semiconductor device provided in the embodiments of this application, the source is located on the side of the active layer close to the insulating substrate and is connected to the first semiconductor layer, the drain is located on the side of the active layer away from the insulating substrate and is connected to the second semiconductor layer, and the orthogonal projection of the source on the insulating substrate covers the orthogonal projection of the active layer on the insulating substrate.

[0019] In the semiconductor device provided in the embodiments of this application, the semiconductor device further includes a gate insulating layer located between the gate and the active layer, an interlayer insulating layer located on the side of the gate away from the insulating substrate, and a first via disposed above the active layer;

[0020] The first via passes through the interlayer insulating layer and the gate insulating layer, the drain passes through the first via and is connected to the second semiconductor layer, and the first semiconductor layer passes through the groove and is connected to the source.

[0021] In the semiconductor device provided in the embodiments of this application, the semiconductor device further includes a second insulating layer located on the side of the drain away from the insulating substrate, and an electrode layer located on the side of the second insulating layer away from the drain. The second insulating layer has a second via located above the active layer, and the electrode layer passes through the second via and is connected to the drain.

[0022] Wherein, the centerline of the first through hole coincides with the centerline of the groove, the centerline of the second through hole coincides with the centerline of the first through hole, and the diameter of the second through hole is smaller than the diameter of the first through hole.

[0023] This application provides an electronic device, which includes any of the semiconductor devices described above.

[0024] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide a semiconductor device and an electronic device. The semiconductor device includes an insulating substrate, a first insulating layer and an active layer disposed on the insulating substrate. The first insulating layer forms a groove, and the active layer is disposed in the groove. The active layer includes a first semiconductor layer, an active segment and a second semiconductor layer stacked on the insulating substrate. The orthographic projection of the first semiconductor layer on the insulating substrate and the orthographic projection of the second semiconductor layer on the insulating substrate partially overlap, thereby forming a semiconductor device with a vertical channel thin film transistor. This can significantly improve the aperture ratio and enhance the integration of the semiconductor device, which is beneficial for developing high PII, high refresh rate products and realizing some IC functions. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a cross-sectional schematic diagram of an existing display panel;

[0027] Figure 2 This is a cross-sectional schematic diagram of the semiconductor device provided in an embodiment of this application;

[0028] Figure 3 for Figure 2 Enlarged view of point A in the middle;

[0029] Figure 4 This is a top cross-sectional view of the semiconductor device provided in the embodiments of this application;

[0030] Figure 5 A flowchart illustrating the method for fabricating the semiconductor device provided in the embodiments of this application;

[0031] Figures 6A to 6H for Figure 5 A flowchart illustrating the fabrication process of semiconductor devices. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0033] This application provides a semiconductor device and an electronic device. These will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0034] This application provides a semiconductor device and a mobile terminal. Detailed descriptions are provided below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0035] Please see Figures 2 to 6H This application provides a semiconductor device and an electronic device, wherein the semiconductor device 2 includes:

[0036] Insulating substrate 10:

[0037] A first insulating layer 30 is disposed on the insulating substrate 10, and the first insulating layer 30 is formed with a groove 301;

[0038] An active layer 41 is disposed within the groove 301. The active layer 41 includes a first semiconductor layer 41A, an active segment 41B, and a second semiconductor layer 41C stacked together. The orthographic projection of the first semiconductor layer 41A onto the insulating substrate 10 and the orthographic projection of the second semiconductor layer 41C onto the insulating substrate 10 partially overlap.

[0039] Understandably, please refer to Figure 1 This is a schematic diagram of the structure of an existing display panel.

[0040] An existing display panel 1 includes an insulating substrate 10, and a light-shielding layer 20, a first insulating layer 30, a thin-film transistor layer 40, a planarization layer 51, a common electrode 61, a passivation layer 52, and a pixel electrode 62 stacked on the insulating substrate 10. The thin-film transistor layer 40 includes an active layer 41, a gate insulating layer 42, a gate 43, an interlayer insulating layer 44, a source electrode 45A, and a drain electrode 45B stacked sequentially on the insulating substrate 10. The thin-film transistor layer 40 includes a plurality of thin-film transistors 40A arranged in a matrix, with each thin-film transistor 40A corresponding to a sub-pixel region. In the prior art, since the thin-film transistors 40A are usually opaque and have a light-shielding effect, the thin-film transistors 40A inevitably occupy a certain pixel area, resulting in a decrease in the effective display area of ​​the pixel, i.e., a decrease in the aperture ratio, which limits the light utilization rate.

[0041] It is understood that, in this embodiment of the application, a groove 301 is formed by setting the first insulating layer 30, and the active layer 41 is disposed in the groove 301. The active layer 41 includes a first semiconductor layer 41A, an active segment 41B and a second semiconductor layer 41C stacked on the insulating substrate 10. The orthographic projection of the first semiconductor layer 41A on the insulating substrate 10 and the orthographic projection of the second semiconductor layer 41C on the insulating substrate 10 partially overlap, thereby forming a semiconductor device with a vertical channel thin film transistor. This can significantly improve the aperture ratio and enhance the integration of the semiconductor device 2, which is beneficial for developing high PII, high refresh rate products and realizing some IC functions.

[0042] The technical solution of this application will now be described in conjunction with specific embodiments.

[0043] In one embodiment, please refer to Figure 2 and Figure 3 ;in, Figure 2 This is a first cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this application; Figure 3 for Figure 2 Enlarged view of point A in the middle.

[0044] This embodiment provides a semiconductor device 2, which includes an insulating substrate 10 and a first insulating layer 30 and an active layer 41 located on the insulating substrate 10. The insulating substrate 10 may include a rigid substrate or a flexible substrate. This embodiment does not impose specific limitations on the material of the insulating substrate 10.

[0045] The first insulating layer 30 forms a groove 301, and the active layer 41 is disposed in the groove 301. The active layer 41 includes a first semiconductor layer 41A, an active segment 41B and a second semiconductor layer 41C stacked together. The orthographic projection of the first semiconductor layer 41A on the insulating substrate 10 and the orthographic projection of the second semiconductor layer 41C on the insulating substrate 10 partially overlap.

[0046] Furthermore, the material of the active layer 41 includes, but is not limited to, amorphous silicon, polycrystalline silicon, or oxide semiconductor material. Preferably, the first semiconductor layer 41A and the second semiconductor layer 42C are both polycrystalline silicon made of silicide with a high concentration of n-type impurities doped. The doping ion concentration of the second semiconductor layer 42C is less than that of the first semiconductor layer 41A. One side of the active segment 41B is connected to the first semiconductor layer 41A, and the other side of the active segment 41B is connected to the second semiconductor layer 41C. Moreover, the shapes of the first semiconductor layer 41A, the active segment 41B, and the second semiconductor layer 41C are the same.

[0047] It is understood that in this embodiment, a groove 301 is formed by setting the first insulating layer 30, and the active layer 41 is disposed in the groove 301. The active layer 41 includes a first semiconductor layer 41A, an active segment 41B and a second semiconductor layer 41C stacked on the insulating substrate 10. The orthographic projection of the first semiconductor layer 41A on the insulating substrate 10 and the orthographic projection of the second semiconductor layer 41C on the insulating substrate 10 partially overlap, thereby forming a semiconductor device with a vertical channel thin film transistor. This can significantly improve the aperture ratio and enhance the integration of the semiconductor device 2, which is beneficial for developing high PII, high refresh rate products and realizing some IC functions.

[0048] Further, in this embodiment, the first insulating layer 30 includes steps 302 disposed on both sides of the groove 301, and the active layer 41 includes a first portion 411 located in the groove 301 and a second portion 412 extending from the groove 301 to the upper surface 302A of the step 302; specifically, the first portion 411 is located at the bottom and side of the groove 301, the second portion 412 is located on the upper surface 302A of the step 302, and the second portion 412 covers the upper surface 302A of the step 302.

[0049] In this embodiment, the semiconductor device 2 includes a gate 43 located on the side of the active layer 41 away from the insulating substrate 10. The gate 43 is insulated from the active layer 41. The active layer 41 includes a side surface 413 located on the upper surface 302A of the step 302. The gate 43 is at least disposed on one side of the side surface 413, and the orthographic projection of the gate 43 on the side surface 413 covers the active segment 41B.

[0050] It is understood that in this embodiment, by setting the gate 43 to be disposed at least on one side of the side surface 413, the orthogonal projection of the gate 43 on the side surface 413 covers the active segment 41B, thereby enabling the gate 43 to regulate the current of the channel P of the active layer 41.

[0051] It should be noted that, in this embodiment, the side surface 413 is an inclined side surface, and the included angle α between the side surface 413 and the upper surface 302A of the step 302 is greater than or equal to 30 degrees and less than or equal to 80 degrees; the included angle α is preferably 30 degrees, 45 degrees, 60 degrees or 80 degrees.

[0052] Furthermore, please combine Figure 4 This is a top cross-sectional view of the semiconductor device provided in the embodiments of this application.

[0053] In this embodiment, the gate 43 is disposed around the active layer 41. The orthographic projection of the gate 43 on the insulating substrate 10 is annular. The orthographic projection of the gate 43 on the insulating substrate 10 overlaps with the four sides of the orthographic projection of the active segment 41B on the insulating substrate 10. That is, an annular channel P region is formed on the active segment 41B, thereby controlling the width of the channel P region and further adjusting the channel P current of the active layer 41.

[0054] In this embodiment, the semiconductor device 2 further includes a source 45A and a drain 45B stacked together; wherein, one of the source 45A and the drain 45B is located on the side of the active layer 41 close to the insulating substrate 10, and the other of the source 45A and the drain 45B is located on the side of the active layer 41 away from the insulating substrate 10, and the gate 43 is located on the side of the active layer 41 away from the insulating substrate 10, and the orthographic projection of the source 45A on the insulating substrate 10 coincides at least with the orthographic projection of a portion of the drain 45B on the insulating substrate 10.

[0055] Preferably, in this embodiment, the source electrode 45A is located on the side of the active layer 41 close to the insulating substrate 10 and is connected to the first semiconductor layer 41A, the drain electrode 45B is located on the side of the active layer 41 away from the insulating substrate 10 and is connected to the second semiconductor layer 41C, and the orthographic projection of the source electrode 45A on the insulating substrate 10 covers the orthographic projection of the active layer 41 on the insulating substrate 10.

[0056] It is understood that in this embodiment, the semiconductor device 2 includes a plurality of thin-film transistors 40A arranged in a matrix. The thin-film transistors 40A include a source 45A, an active layer 41, a gate 43, and a drain 45B stacked together. The active layer 41 includes a first semiconductor layer 41A, an active segment 41B, and a second semiconductor layer 41C stacked on the insulating substrate 10. In this embodiment, by setting the source 45A to be located on the side of the active layer 41 closer to the insulating substrate 10 and connected to the first semiconductor layer 41A, and the drain 45B to be located on the side of the active layer 41 away from the insulating substrate 10 and connected to the second semiconductor layer 41C, a semiconductor device 2 with vertical channel thin-film transistors 40A is formed. This can significantly improve the pixel aperture ratio and the integration of the semiconductor device 2, which is beneficial for developing high PII and high refresh rate products. At the same time, since the semiconductor device 2 provided in this embodiment has the characteristics of small size and high integration, it can also realize IC data storage, voltage conversion, and other functions.

[0057] Furthermore, in this embodiment, the active layer 41 includes a first semiconductor layer 41A, an active segment 41B, and a second semiconductor layer 41C stacked on the insulating substrate 10. Therefore, the length of the channel P can be controlled by controlling the thickness of the active segment 41B and the angle α between the side surface 413 and the upper surface 302A of the step 302. That is, the length of the channel P can be controlled independently of the exposure equipment.

[0058] In addition, it is understandable that, combined Figure 1In the prior art, a light-shielding layer 20 is usually provided between the insulating substrate 10 and the active layer 41. The light-shielding layer 20 can block the light incident on the active layer 41, thereby reducing the increase in leakage current caused by photogenerated carriers generated by light irradiating the active layer 41, and thus maintaining the stability of the active layer 41 during operation. Compared with the prior art, this embodiment sets the orthographic projection of the source electrode 45A on the insulating substrate 10 to cover the orthographic projection of the active layer 41 on the insulating substrate 10, so that the source electrode 45A can play the role of the light-shielding layer 20 in the prior art, saving engineering processes and reducing the manufacturing cost of the semiconductor device 2; and by setting the orthographic projection of the drain electrode 45B on the insulating substrate 10 to overlap at least part of the orthographic projection of the source electrode 45A on the insulating substrate 10, wiring space is saved.

[0059] In this embodiment, the semiconductor device 2 further includes a gate insulating layer 42 located between the gate 43 and the active layer 41, an interlayer insulating layer 44 located on the side of the gate 43 away from the insulating substrate 10, and a first via 400A disposed above the active layer 41; wherein the first via 400A passes through the interlayer insulating layer 44 and the gate insulating layer 43, the drain 45B passes through the first via 400A and is connected to the second semiconductor layer 41C, and the first semiconductor layer 41A passes through the groove 301 and is connected to the source 45A.

[0060] Specifically, the material of the first insulating layer 30 includes, but is not limited to, monolayer silicon nitride (Si3N4), monolayer silicon dioxide (SiO2), and monolayer silicon oxynitride (SiON). x (or a double-layer structure of the above film layers), wherein the groove 301 is formed in the first insulating layer 30 to extend onto the source electrode 45A; it is understood that the first insulating layer 30 is disposed around the source electrode 45A, thereby blocking water and oxygen from the source electrode 45A.

[0061] Both the gate insulating layer 42 and the interlayer insulating layer 44 have strong water and oxygen barrier capabilities and insulation capabilities. The materials of the gate insulating layer 42 and the interlayer insulating layer 44 include, but are not limited to, silicon oxide (SiO2). X ), silicon nitride (SiN) XThe first via 400A is formed in the gate insulating layer 42 and the interlayer insulating layer 44 to extend onto the active layer 41. It is understood that the gate insulating layer 42 is disposed around the active layer 41, thereby blocking water and oxygen and providing insulation for the active layer 41, and the interlayer insulating layer 44 is disposed around the gate 43, thereby blocking water and oxygen and providing insulation for the gate 43.

[0062] In this embodiment, the semiconductor device 2 further includes a second insulating layer 50 located on the side of the drain 45B away from the insulating substrate 10, and an electrode layer 70 located on the side of the second insulating layer 50 away from the drain 45B. The second insulating layer 50 has a second via 40B located above the active layer 41. The electrode layer 70 passes through the second via 40B and connects to the drain 45B. The center line W1 of the first via 400A coincides with the center line W2 of the groove 301, and the center line W3 of the second via 40B coincides with the center line W1 of the first via 400A. The diameter of the second via 40B is smaller than the diameter of the first via 400A. Within the first via 400A, the second insulating layer 50 covers the inner wall of the drain 45B, thereby blocking water and oxygen and providing insulation for the drain 45B.

[0063] Specifically, in this embodiment, the second insulating layer 50 includes a planarization layer 51 located on the drain electrode 45B and a passivation layer 52 located on the planarization layer 51 away from the drain electrode 45B. The electrode layer 60 includes a first electrode 61 and a second electrode 62. The first electrode 61 is located between the planarization layer 51 and the passivation layer 52, and the second electrode 62 is located on the side of the passivation layer 52 away from the planarization layer 51. The material of the electrode layer 60 includes a metal oxide material, which includes, but is not limited to, indium gallium zinc oxide (IGZO). The first electrode 61 is a common electrode 61, and the second electrode 62 is a pixel electrode 62.

[0064] Specifically, the planarization layer 51 has a first sub-hole 51A that exposes a portion of the drain electrode 45B, and the passivation layer 52 has a second sub-hole 52A that exposes a portion of the drain electrode 45B. The pixel electrode 62 is connected to the drain electrode 45B through the first sub-hole 51A and the second sub-hole 52A. In the direction perpendicular to the insulating substrate 10, the aperture of the second sub-hole 52A is smaller than the aperture of the first sub-hole 51A. Within the first sub-hole 51A, the passivation layer 52 covers the inner wall of the planarization layer 51, thereby providing a barrier against water and oxygen and an insulating effect to the planarization layer 51.

[0065] The center line W5 of the second sub-hole 52A, the center line W4 of the first sub-hole 51A, and the center line W1 of the first via 400A coincide with each other. The diameter of the first sub-hole 51A is smaller than the diameter of the first via 400A. Within the first via 400A, the planarization layer 51 covers the inner wall of the drain electrode 45B, thereby blocking water and oxygen and providing insulation for the drain electrode 45B.

[0066] It should be noted that the first electrode 61 is a common electrode 61, and the second electrode 62 is a pixel electrode 62, which are only used for illustrative purposes. In another embodiment, the semiconductor device 2 further includes a planarization layer, a bridging layer, a passivation layer, a light-emitting device layer, and an encapsulation layer located on the side of the drain 45B away from the insulating substrate 10. The light-emitting device layer includes an electrode layer, a light-emitting layer, and a cathode stacked on the passivation layer, wherein the electrode layer 60 includes an anode.

[0067] This application also provides a method for fabricating a semiconductor device. Please refer to the embodiments thereof. Figure 5 and Figures 6A to 6H ;in, Figure 5 A flowchart illustrating the method for fabricating the semiconductor device provided in the embodiments of this application; Figures 6A to 6H for Figure 5 A structural process flow diagram of semiconductor devices.

[0068] In this embodiment, the manufacturing method includes the following steps:

[0069] Step S100: Provide an insulating substrate 10.

[0070] When the insulating substrate 10 is a rigid substrate, the material can be metal or glass. When the insulating substrate 10 is a flexible substrate, the material can include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane-based resin, cellulose resin, siloxane resin, polyimide-based resin, and polyamide-based resin.

[0071] Step S200: A first insulating layer 30 and an active layer 41 are sequentially formed on the insulating substrate 10. The first insulating layer 30 forms a groove 301, and the active layer 41 is disposed in the groove 301. The active layer 41 includes a first semiconductor layer 41A, an active segment 41B, and a second semiconductor layer 41C stacked together. The orthographic projection of the first semiconductor layer 41A on the insulating substrate 10 and the orthographic projection of the second semiconductor layer 41C on the insulating substrate 10 partially overlap.

[0072] Specifically, in this embodiment, before step S200, the method for manufacturing the semiconductor device further includes the following steps:

[0073] Step S110: Form a source electrode 45A on the insulating substrate 10, such as Figure 6A As shown.

[0074] The source electrode 45A is made of materials including but not limited to metals or opaque non-metals. In this embodiment, the source electrode 45A is preferably made of a metal material, which includes but is not limited to one or more alloys of molybdenum (Mo), titanium (Ti), and nickel (Ni). Specifically, in this embodiment, a metal material layer is deposited on the insulating substrate 10, and the metal material layer is patterned by wet etching using a photolithography process to form a source electrode 45A pattern that has the functions of wiring and light shielding.

[0075] In step S200, the method for fabricating the semiconductor device further includes the following steps:

[0076] Step S201: A first insulating layer 30 is formed on the source electrode 45A. A photomask process is used to create a groove 301 on the first insulating layer 30 to expose a portion of the source electrode 45A, such as... Figure 6B As shown.

[0077] The material of the first insulating layer 30 includes, but is not limited to, monolayer silicon nitride (Si3N4), monolayer silicon dioxide (SiO2), and monolayer silicon oxynitride (SiON). x The first insulating layer 30 may be a double-layer structure of the above films. The fabrication method of the first insulating layer 30 includes, but is not limited to, plasma-enhanced chemical vapor deposition (PECVD). Preferably, photolithography and dry etching are used to pattern the first insulating layer 30 to form the groove 301.

[0078] Step S202: An active layer 41 is formed on the side of the first insulating layer 30 away from the insulating substrate 10, and the active layer 41 is connected to the source electrode 45A through the groove 301.

[0079] Specifically, step S202 includes: sequentially forming a first semiconductor layer 41A, an active segment 41B, and a second semiconductor layer 41C on the side of the active layer 41 away from the first insulating layer 30, such as... Figure 6CAs shown; wherein, the first semiconductor layer 41A and the second semiconductor layer 42C are both made of polycrystalline silicon with a high concentration of n-type impurities doped by silicide, the doping ion concentration of the second semiconductor layer 42C is less than the doping ion concentration of the first semiconductor layer 41A, one side of the active segment 41B is connected to the first semiconductor layer 41A, the other side of the active segment 41B is connected to the second semiconductor layer 41C, and the shapes of the first semiconductor layer 41A, the active segment 41B, and the second semiconductor layer 41C are the same.

[0080] The first insulating layer 30 includes steps 302 disposed on both sides of the groove 301, and the active layer 41 includes a first portion 411 located in the groove 301 and a second portion 412 extending from the groove 301 to the upper surface 302A of the step 302. Specifically, the first portion 411 is located at the bottom and side of the groove 301, and the second portion 412 is located on the upper surface 302A of the step 302, and the second portion 412 covers the upper surface 302A of the step 302.

[0081] It should be noted that, in this embodiment, the side surface 413 is an inclined side surface, and the included angle α between the side surface 413 and the upper surface 302A of the step 302 is greater than or equal to 30 degrees and less than or equal to 80 degrees; the included angle α is preferably 30 degrees, 45 degrees, 60 degrees or 80 degrees.

[0082] It is understood that in this embodiment, a groove 301 is formed by setting the first insulating layer 30, and the active layer 41 is disposed in the groove 301. The active layer 41 includes a first semiconductor layer 41A, an active segment 41B and a second semiconductor layer 41C stacked on the insulating substrate 10. The orthographic projection of the first semiconductor layer 41A on the insulating substrate 10 and the orthographic projection of the second semiconductor layer 41C on the insulating substrate 10 partially overlap, thereby forming a semiconductor device with a vertical channel thin film transistor. This can significantly improve the aperture ratio and enhance the integration of the semiconductor device 2, which is beneficial for developing high PII, high refresh rate products and realizing some IC functions.

[0083] In this embodiment, the method for manufacturing the semiconductor device further includes the following steps:

[0084] Step S300: A gate insulating layer 42 and a gate 43 are sequentially formed on the side of the active layer 41 away from the first insulating layer 30, wherein the orthogonal projection of the gate insulating layer 42 on the insulating substrate 10 covers the orthogonal projection of the active layer 41 on the insulating substrate 10, and the active layer 41 includes a side surface 413 located on the upper surface 302A of the step 302; wherein the gate 43 is at least disposed on one side of the side surface 413, and the orthogonal projection of the gate 43 on the side surface 413 covers the active segment 41B, such as... Figure 6D As shown.

[0085] The material of the gate insulating layer 42 includes, but is not limited to, silicon oxide (SiO2). X ), silicon nitride (SiN) X The gate 43 may be made of silicon oxynitride (SiNO) or a layer thereof, and the material of the gate 43 may include, but is not limited to, at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta) and tungsten (W). This embodiment does not impose specific limitations on these materials.

[0086] Specifically, the gate 43 is disposed around the active layer 41, and the orthographic projection of the gate 43 on the insulating substrate 10 is annular. The orthographic projection of the gate 43 on the insulating substrate 10 overlaps with the four sides of the orthographic projection of the active segment 41B on the insulating substrate 10, that is, an annular channel P region is formed on the active segment 41B, thereby controlling the width of the channel P region and further adjusting the channel P current of the active layer 41.

[0087] Step 400: An interlayer insulating layer 44 is formed on the side of the gate 43 away from the gate insulating layer 42. A first via 400A is formed on the interlayer insulating layer 44 and the gate insulating layer 42 to expose a portion of the active layer 41, as shown in the photomask process. Figure 6E As shown.

[0088] The material of the interlayer insulating layer 44 includes, but is not limited to, silicon oxide (SiO2). X ), silicon nitride (SiN) X The material can be silicon oxynitride (SiNO) or a layer thereof, but this embodiment does not impose specific limitations on this; preferably, photolithography and dry etching are used to pattern the interlayer insulating layer 44 and the gate insulating layer 42 to form the first via 400A, and the center line W1 of the first via 400A coincides with the center line W2 of the groove 301.

[0089] Step S500: A drain 45B is formed on the side of the interlayer insulating layer 44 away from the gate 43. The drain 45B is connected to the active layer 41 through the first via 400A, such as... Figure 6F As shown.

[0090] The material of the drain electrode 45B includes, but is not limited to, one or more alloys of molybdenum (Mo), titanium (Ti), and nickel (Ni). Specifically, in this embodiment, a metal material layer is deposited on the side of the interlayer insulating layer 44 away from the gate 43, and the metal material layer is patterned by wet etching using a photolithography process to form a drain electrode 45B pattern with wiring and light-shielding functions. The source electrode 45A is connected to the second semiconductor layer 41C through the first via 400A.

[0091] Step S600: A planarization layer 51 and a first electrode 61 are sequentially formed on the side of the drain electrode 45B away from the interlayer insulating layer 44.

[0092] Step S600 further includes creating a first sub-hole 51A on the planarization layer 51 to expose a portion of the drain electrode 45B through a photomask process. The center line W4 of the first sub-hole 51A coincides with the center line W1 of the first via 400A. The diameter of the first sub-hole 51A is smaller than the diameter of the first via 400A. Within the first via 400A, the planarization layer 51 covers the inner wall of the drain electrode 45B, thereby providing insulation and preventing water and oxygen from entering the drain electrode 45B. Figure 6G As shown.

[0093] Step S700: A passivation layer 52 and a second electrode 62 are sequentially formed on the side of the planarization layer 51 away from the drain electrode 45B.

[0094] Step S700 further includes creating a second sub-hole 52A on the passivation layer 70 to expose a portion of the drain electrode 45B through a photomask process. The second electrode 62 is connected to the drain electrode 45B through the second sub-hole 52A and the first sub-hole 51A. The center line W5 of the second sub-hole 52A, the center line W4 of the first sub-hole 51A, and the center line W1 of the first via 400A coincide with each other. The diameter of the second sub-hole 52A is smaller than the diameter of the first sub-hole 51A. Within the first sub-hole 51A, the passivation layer 52 covers the inner wall of the planarization layer 51, thereby providing water and oxygen barrier and insulation for the planarization layer 51. Figure 6H As shown.

[0095] Furthermore, the materials of the first electrode 61 and the second electrode 62 both include metal oxide materials, including but not limited to indium gallium zinc oxide (IGZO). The first electrode 61 is a common electrode 61, and the second electrode 62 is a pixel electrode 62.

[0096] It is understood that, in this embodiment, by setting the source 45A to be located on the side of the active layer 41 closer to the insulating substrate 10, the drain 45B to be located on the side of the active layer 41 away from the insulating substrate 10, and the gate 43 to be located between the drain 45B and the active layer 41, and with the orthographic projection of the gate 43 on the insulating substrate 10 at least partially overlapping the orthographic projection of the active layer 41 on the insulating substrate 10, a semiconductor device 2 with a vertical channel thin-film transistor 40A is formed. This significantly improves the pixel aperture ratio and the integration density of the semiconductor device 2, which is beneficial for developing high PII and high refresh rate products. Furthermore, since the semiconductor device 2 provided in this embodiment has the characteristics of small size and high integration density, it can also realize IC data storage, voltage conversion, and other functions.

[0097] Meanwhile, compared with the prior art, this embodiment places the source electrode 45A on the side of the active layer 41 close to the insulating substrate 10, and the orthographic projection of the source electrode 45A on the insulating substrate 10 covers the orthographic projection of the active layer 41 on the insulating substrate 10, so that the source electrode 45A plays the role of the light-shielding layer 20 in the prior art. This embodiment saves a photomask and reduces an etching process, thereby simplifying the process and saving production costs.

[0098] This embodiment provides an electronic device, which includes a terminal body and the semiconductor device described in any of the above embodiments.

[0099] It is understood that the semiconductor device has been described in detail in the above embodiments, and will not be repeated here.

[0100] In specific applications, the electronic device can be a display screen for devices such as smartphones, tablets, laptops, smart bracelets, smartwatches, smart glasses, smart helmets, desktop computers, smart TVs, or digital cameras, and can even be applied to electronic devices with flexible displays.

[0101] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0102] The above provides a detailed description of a semiconductor device and electronic device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, include: Insulating substrate: A thin-film transistor layer is located on the insulating substrate, the thin-film transistor layer comprising: A first insulating layer is disposed on the insulating substrate, the first insulating layer having a groove, and the first insulating layer including steps disposed on both sides of the groove; An active layer is disposed within the groove. The active layer includes a first semiconductor layer, an active segment, and a second semiconductor layer stacked together, wherein the orthographic projection of the first semiconductor layer on the insulating substrate and the orthographic projection of the second semiconductor layer on the insulating substrate partially overlap. The semiconductor device includes a gate located on the side of the active layer away from the insulating substrate, the gate being insulated from the active layer, and the active layer including a side surface located on the upper surface of the step; the gate is disposed on at least one side of the side surface, and the orthographic projection of the gate on the side surface covers the active segment.

2. The semiconductor device according to claim 1, characterized in that, The active layer includes a first portion located within the groove and a second portion extending from the groove toward the upper surface of the step.

3. The semiconductor device according to claim 1, characterized in that, The gate is disposed around the active layer.

4. The semiconductor device according to claim 1, characterized in that, The angle between the side surface and the upper surface of the step is greater than or equal to 30 degrees and less than or equal to 80 degrees.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor device layer further includes a source and a drain electrode stacked together; In this configuration, one of the source and the drain is located on the side of the active layer closer to the insulating substrate, and the other of the source and the drain is located on the side of the active layer away from the insulating substrate. The orthographic projection of the source on the insulating substrate at least coincides with the orthographic projection of a portion of the drain on the insulating substrate.

6. The semiconductor device according to claim 5, characterized in that, The source electrode is located on the side of the active layer closer to the insulating substrate and is connected to the first semiconductor layer. The drain electrode is located on the side of the active layer away from the insulating substrate and is connected to the second semiconductor layer. The orthogonal projection of the source electrode on the insulating substrate covers the orthogonal projection of the active layer on the insulating substrate.

7. The semiconductor device according to claim 6, characterized in that, The semiconductor device further includes a gate insulating layer located between the gate and the active layer, an interlayer insulating layer located on the side of the gate away from the insulating substrate, and a first via disposed above the active layer; The first via passes through the interlayer insulating layer and the gate insulating layer, the drain passes through the first via and is connected to the second semiconductor layer, and the first semiconductor layer passes through the groove and is connected to the source.

8. The semiconductor device according to claim 7, characterized in that, The semiconductor device further includes a second insulating layer located on the side of the drain away from the insulating substrate, and an electrode layer located on the side of the second insulating layer away from the drain. The second insulating layer has a second via located above the active layer, and the electrode layer passes through the second via to connect to the drain. Wherein, the center line of the first through hole coincides with the center line of the groove, the center line of the second through hole coincides with the center line of the first through hole, and the diameter of the second through hole is smaller than the diameter of the first through hole.

9. An electronic device, characterized in that, The electronic device includes the semiconductor device according to any one of claims 1-8.

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