A gain boosting amplifier with cross conductance and desensitizing inductance

Abstract

The application belongs to the technical field of wireless communication, and relates to an amplifier in a wireless communication system, and particularly provides a gain-boosting amplifier with cross conductance and desensitizing inductance, which is used to solve the problem of low maximum available gain G ma Still low. The application introduces desensitizing inductance (L D1 , L D2 ) and cross conductance (G CC ) to form a U-boosting network on the basis of a conventional differential common-source amplifier, effectively boosts the Mason's U of the amplifier, i.e. increases the upper limit value G ma of the maximum available gain G ma_upper_limit , and then matches the LLREN so that the maximum available gain G ma of the amplifier is significantly improved; and at high frequencies, the U-boosting structure with the desensitizing inductance can effectively reduce the sensitivity of the gain boosting to the process deviation and model uncertainty achieved by the cross conductance; and finally the power gain of the amplifier is significantly improved.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication technology and relates to amplifiers in wireless communication systems. Specifically, it provides a gain boost amplifier with cross-conductance and desensitized inductor for improving power gain. Background Technology

[0002] Millimeter wave and terahertz bands offer abundant spectrum resources and provide large communication capacity, attracting considerable attention; however, the extremely high operating frequencies pose challenges to the design of wireless RF front-end systems. As one of the most crucial modules in an RF front-end system, the intrinsic gain of transistors in amplifiers decreases rapidly with increasing operating frequencies, making the power gain achievable by the amplifier extremely limited.

[0003] To improve the power gain of an amplifier, traditional methods utilize LLREN (Linear, lossless, and reciprocal embedding network) to maximize the available gain G. ma (Maximum available gain) is increased to its maximum value G. ma_upper_limit G ma_upper_limit Defined as:

[0004]

[0005] Where U stands for Mason's U; and G... ma Defined as the power gain when the amplifier achieves simultaneous input-output conjugate matching, and the expression for U is:

[0006]

[0007] Among them, Y 11 Y 12 Y 21 and Y 22 These are the admittance Y matrix parameters of the two-port network.

[0008] Building upon this, the paper "A 173GHz Amplifier With a 18.5dB Power Gain in a 130nm SiGe Process: A Systematic Design of High-Gain Amplifiers Above f" maxThe paper " / 2" (H. Khatibiet al., IEEE TMTT, vol. 66, no. 1, pp. 201-214, 2018) and the paper "A High-Gain mm-Wave Amplifier Design: An Analytical Approach to Power Gain Boosting" (H. Bameri, O. Momeni, IEEE JSSC, vol. 52, no. 2, pp. 357-370, 2017) respectively propose the use of... Figure 1 The Y / Z-LLREN shown, such as Figure 2 The Y / PreZ-LLREN gain-boosting architecture shown enables G ma Can reach the upper limit value G ma_upper_limit This effectively improves power gain. However, both structures share a common drawback: as the amplifier's operating frequency gradually increases and approaches the highest oscillation frequency f... max When U drops sharply, that is, G ma_upper_limit A sharp decline; even G ma Able to reach G ma_upper_limit Maximum available gain G ma It remains low. Summary of the Invention

[0009] The purpose of this invention is to improve the maximum usable gain upper limit G of existing Y / Z-LLREN and Y / PreZ-LLREN structure gain boost amplifiers. ma_upper_limit To address the persistent issue of low gain, this invention provides a gain-boosting amplifier with cross-conductance and a desensitizing inductor. Building upon the traditional differential common-source amplifier, this invention introduces a desensitizing inductor and cross-conductance to form a U-boosting network, effectively increasing the amplifier's Mason's U, i.e., increasing the maximum usable gain G. ma The upper limit of G ma_upper_limit This, in turn, matches the LLREN to maximize the amplifier's usable gain G. ma Significantly improved.

[0010] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0011] A gain boost amplifier with cross-conductance and desensitized inductor, comprising: a differential common-source transistor pair consisting of transistor M1 and transistor M2; characterized in that the gain boost amplifier further comprises: a U-boost network; the U-boost network is composed of two identical U-boost sub-networks, the U-boost sub-networks being composed of a desensitized inductor L D1 Desensitizing inductor L D2 With cross conductance G CC Composition; In the first group of U-lifting sub-networks, the desensitized inductor L D1The gate of the differential common-source transistor M1 is connected to the differential input terminal V. in+ Between, desensitizing inductor L D2 The drain of the differential common-source transistor M1 is connected to the differential output terminal V. out+ Between, cross conductance G CC Connected to the differential input terminal V in+ With differential output terminal V out- Between; in the second group of U-lift subnetworks, the desensitized inductor L D1 The gate of the differential common-source transistor M2 is connected to the differential input terminal V. in- Between, desensitizing inductor L D2 The drain of the differential common-source transistor M2 is connected to the differential output terminal V. out- Between, the cross conductance G CC Connected to the differential input terminal V in- With differential output terminal V out+ Between; the sources of differential common source transistor M1 and differential common source transistor M2 are connected to a common ground terminal.

[0012] Furthermore, transistors M1 and M2 are field-effect transistors or bipolar junction transistors (BJTs); the emitter of the BJT corresponds to the source of the BJT, the collector of the BJT corresponds to the drain of the BJT, and the base of the BJT corresponds to the gate of the BJT.

[0013] Furthermore, the cross conductance G CC The range of values ​​for is:

[0014]

[0015] Among them, Y 11_D Y 12_D Y 21_D and Y 22_D Add a desensitizing inductor L to the differential common-source transistor pair D1 With L D2 The parameters of the two-port Y matrix.

[0016] The beneficial effects of this invention are as follows:

[0017] This invention provides a gain boost amplifier with cross-conductance and desensitizing inductor. Based on the traditional differential common-source amplifier, a desensitizing inductor and cross-conductance are introduced to form a U-boost network, effectively boosting the amplifier's Mason's U, that is, increasing the maximum usable gain G. ma The upper limit of G ma_upper_limit This, in turn, matches LLREN (to maximize the available gain G). ma Increase to its upper limit value G ma_upper_limit This makes the amplifier's maximum usable gain G maThe gain gain is significantly improved; moreover, at high frequencies, the U-boost structure with desensitized inductor can effectively reduce the sensitivity of the gain boost to process deviations and model uncertainties in the implementation of cross conductance, avoiding the impact of process sensitivity and model inaccuracy on the gain boost in the implementation of cross conductance; finally, the power gain of the amplifier is significantly improved. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the existing gain boost amplifier with Y / Z-LLREN.

[0019] Figure 2 This is a schematic diagram of the existing gain boost amplifier with Y / PreZ-LLREN.

[0020] Figure 3 This is a schematic diagram of the gain boost amplifier with cross-conductance and desensitizing inductor in this invention.

[0021] Figure 4 This is the equivalent admittance Y-parameter model of the U-lifting network in this invention.

[0022] Figure 5 The U-lifting network in this invention is used in different desensitizing inductors L D1 L D2 U follows G CC The curve showing the change.

[0023] Figure 6 This is a schematic diagram of the gain boost amplifier with U-boosting network and Y / Z-LLREN in an embodiment of the present invention.

[0024] Figure 7 This is a circuit schematic of a gain boost amplifier with a U-boosting network and a Y / Z-LLREN in an embodiment of the present invention.

[0025] Figure 8 The G in this embodiment of the invention is a gain boost amplifier with a U-boosting network and a Y / Z-LLREN. ma Curve showing the change with frequency.

[0026] Figure 9 The S-parameter test results are for the gain boost amplifier with U-boosting network and Y / Z-LLREN in the embodiment of the present invention.

[0027] Figure 10 This is a performance comparison chart of the gain boost amplifier with U-boosting network and Y / Z-LLREN in this embodiment of the invention and the comparative example. Detailed Implementation

[0028] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. The specific embodiments described below are merely illustrative examples of this invention.

[0029] This embodiment provides an amplifier with cross-conductance and desensitizing inductor for improving power gain, the structure of which is as follows: Figure 3 As shown, it consists of two parts: the first part is a differential common-source transistor pair (M1 and M2), and the second part is a U-lift network; wherein, the U-lift network is composed of two identical U-lift sub-networks, and the U-lift sub-network is composed of a desensitized inductor L. D1 Desensitizing inductor L D2 With cross conductance G CC Composition; In the first group of U-lifting sub-networks, the desensitized inductor L D1 The gate of the differential common-source transistor M1 is connected to the differential input terminal V. in+ Between, desensitizing inductor L D2 The drain of the differential common-source transistor M1 is connected to the differential output terminal V. out+ Between, cross conductance G CC Connected to the differential input terminal V in+ With differential output terminal V out- Between; in the second group of U-lift subnetworks, the desensitized inductor L D1 The gate of the differential common-source transistor M2 is connected to the differential input terminal V. in- Between, desensitizing inductor L D2 The drain of the differential common-source transistor M2 is connected to the differential output terminal V. out- Between, the cross conductance G CC Connected to the differential input terminal V in- With differential output terminal V out+ Between; the sources of differential common source transistor M1 and differential common source transistor M2 are connected to a common ground terminal.

[0030] In terms of working principle:

[0031] For the U-lift network, a desensitizing inductor L is added to the differential common-source transistor pair. D1 L D2 With cross conductance G CC The principle of U-lifting is analyzed from the perspective of the equivalent model of admittance Y parameter.

[0032] The equivalent Y-parameter model of the U-lifting network is as follows: Figure 4 As shown, for the entire U-lifting network, the terms of the Y parameter matrix are... 11_U Y 12_U Y 21_U and Y 22_U as follows:

[0033]

[0034] Among them, Y 11_D Y 12_D Y 21_D and Y 22_D Add a desensitizing inductor L to the differential common-source transistor pair (M1 and M2) D1 and L D2 Two-port Y matrix parameters:

[0035]

[0036] Among them, Y 11_DIFF Y 12_DIFF Y 21_DIFF and Y 22_DIFF These are the two-port Y-matrix parameters of the differential common-source transistor pair, where ω is the angular frequency;

[0037] Starting from the expression for U, the entire U-lifting network's U... boosted for:

[0038]

[0039] It can be observed that when cross-conductance G is added... CC After that, regarding U boosted The molecule, due to Y 21_D and Y 12_D G will be added at the same time CC Therefore, U boosted The numerator remains unchanged; while for the denominator, the following condition must be met:

[0040] Re[Y 11_D ]+Re[Y 22_D ]-Re[Y 12_D ]-Re[Y 21_D <0

[0041] U boosted Will follow G CC Increases with the increase of; G CC The range of values ​​for is:

[0042]

[0043] In addition, for adding different desensitizing inductors L D1 and L D2 Y was obtained 11_D Y 12_D Y 21_D and Y 22_D They are also different, which will lead to U boosted With G CC The slopes of the ascents are also different; for example... Figure 5 The figure shows the U-lifting network with different desensitizing inductors L. D1 L D2 U follows G CC The curve showing the change of L is shown in the figure. D1 and L D2 The increase of U boosted Will follow G CC The slope of the growth curve can also be reduced, which has the benefit of reducing the impact on G. CC The impact of model inaccuracies and process deviations caused by process implementation.

[0044] This embodiment uses the aforementioned U-boosting network to improve the amplifier's Mason's U, i.e., to boost the upper limit value G. ma_upper_limit Based on this, LLREN is typically used to maximize the available gain G. ma Increase to its upper limit value G ma_upper_limit Therefore, this embodiment further employs Y-type LLREN and Z-type LLREN, such as... Figure 6 As shown, it should be noted that LLREN is existing technology in this field, and its specific structure and topology will not be described in detail in this invention.

[0045] Furthermore, such as Figure 6 The specific circuit schematic of the amplifier shown is as follows: Figure 7 As shown, the cross conductance G CC From resistor R CC Series capacitor C CC Implementation, C CC It serves to block DC current, ensuring that the drain bias of the transistor does not affect the gate bias; the Y / Z type LLREN includes a Y-type LLREN and a Z-type LLREN, with the Z-type LLREN being a capacitive element, specifically a capacitor C connected in series between the source and ground of the transistor. z Furthermore, a 90° transmission line is used to provide a DC bias point; the Y-type LLREN is a capacitive element, specifically a capacitor C connected in a cross configuration. y .

[0046] In this embodiment, the design process used is CMOS 65nm process, the gate length of transistor M1 is 60nm, the gate width is 700nm, and the cross-index is 12; in this embodiment, the amplifier operates at a frequency of 190GHz, and the inductor L... D1 and L D2 The values ​​are all 4.4 pH, the gate voltage of transistors M1 and M2 is 0.8 V, and the drain voltage V DD 1V; R CC It is 1.2kΩ, C CC 80fF, C Y 5.6fF, CZ It is 46.5fF.

[0047] The gain boost amplifier described in this embodiment was simulated and tested, such as... Figure 8 The image shows G. ma As shown in the figure, with the frequency variation, at 190 GHz, compared to a differential common-source amplifier without any technology, the gain boost amplifier in this embodiment has a higher G value. ma It improved from 5.9dB to 16dB, an increase of nearly 10.1dB.

[0048] Meanwhile, based on the gain-boosting amplifier described in this embodiment, a cascaded structure is used to implement a three-stage amplifier, and chip testing is performed on the three-stage amplifier; such as Figure 9 The figure shows the S-parameters of the three-stage amplifier. As can be seen from the figure, the three-stage amplifier achieves a high gain of 32.1 dB at 189 GHz. This is consistent with the literature "A 173 GHz Amplifier With a 18.5 dB Power Gain in a 130 nm SiGe Process: A Systematic Design of High-Gain Amplifiers Above..." max The paper “ / 2” (H. Khatibiet al., IEEE TMTT, vol. 66, no. 1, pp. 201-214, 2018) and the paper “A High-Gain mm-Wave Amplifier Design: An Analytical Approach to Power Gain Boosting” (H. Bameri, O. Momeni, IEEE JSSC, vol. 52, no. 2, pp. 357-370, 2017) are used as Comparative Examples 1 and 2, respectively. The performance of the three-stage amplifier in this embodiment is compared with that of the comparative examples, and the results are shown in Figure 10. As can be seen from the figure, the amplifier in this embodiment has the highest FoM (Figure of Merit) value. Specifically:

[0049]

[0050] Where Gain is the amplifier gain, n is the number of stages in the amplifier, and f is the operating frequency. max This is the highest oscillation frequency of the transistor; this FoM value is widely used to compare and evaluate the effectiveness of gain enhancement techniques under different processes and frequencies.

[0051] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A gain boost amplifier with cross-conductance and desensitized inductor, comprising: A differential common-source transistor pair consisting of transistor M1 and transistor M2; characterized in that the gain boost amplifier further includes: U Improve the network; the aforementioned U The boost network consists of two identical sets U Improve the subnetwork structure, the U The boost subnetwork is made up of desensitized inductor L D1 Desensitizing inductor L D2 With cross conductance G CC Composition; Group 1 U In the boost subnetwork, the desensitized inductor L D1 The gate of the differential common-source transistor M1 is connected to the differential input terminal V. in+ Between, desensitizing inductor L D2 The drain of the differential common-source transistor M1 is connected to the differential output terminal V. out+ Between, cross conductance G CC Connected to the differential input terminal V in+ With differential output terminal V out- Between; the second group U In the boost subnetwork, the desensitized inductor L D1 The gate of the differential common-source transistor M2 is connected to the differential input terminal V. in- Between, desensitizing inductor L D2 The drain of the differential common-source transistor M2 is connected to the differential output terminal V. out- Between, the cross conductance G CC Connected to the differential input terminal V in- With differential output terminal V out+ Between; the sources of differential common source transistor M1 and differential common source transistor M2 are connected to a common ground terminal.

2. The gain boost amplifier with cross-conductance and desensitizing inductor as described in claim 1, characterized in that, The transistors M1 and M2 are field-effect transistors or triodes.

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