Dual-passive noise shaping correction method applied to high-precision successive approximation ADC

Abstract

This invention discloses a dual passive noise shaping and correction method for high-precision successive approximation ADCs. It combines noise shaping technology with a correction algorithm. Within a short period after chip power-on, using a limited correction DAC capacitor array and noise shaping technology, it achieves higher-precision correction codes for SAR ADC capacitor mismatch and comparator offset voltage. In normal operating mode, this invention again incorporates noise shaping technology, adding the correction codes to the main DAC in analog form, reducing the impact of non-ideal factors. This invention reuses sampling integration capacitors, resulting in a simple structure. With minimal power consumption, it significantly improves correction accuracy and increases the overall signal-to-noise ratio and spurious-free dynamic range, thereby enhancing the overall efficiency of the SAR ADC.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a dual passive noise shaping and correction method for high-precision successive approximation ADCs. Background Technology

[0002] In recent years, the rapid development of communication technology, sensors, computers, and healthcare has driven the formation of the "Internet of Everything" era, and the Internet of Things (IoT) is changing people's lives. To more accurately collect analog information from the real world, in addition to high-performance sensors, stringent requirements are placed on one of the core modules: the analog-to-digital converter (ADC). Higher resolution, faster speed, and lower power consumption are needed to better digitize sensors with high dynamic range. Among various ADCs, Delta-Sigma ADCs and SAR ADCs are generally the preferred architectures for high-resolution applications.

[0003] Delta-sigma ADCs use noise shaping techniques to move noise out of the passband and change the spectral shape, thereby effectively improving the in-band signal-to-noise ratio (SNR). However, this architecture generally requires a high-performance operational transconductance amplifier (OTA) to build the active integrator, which consumes more power and is not easy to scale, thus limiting its applications.

[0004] SAR ADCs achieve a good balance in power consumption, speed, and accuracy, and are widely used in high-precision, low-power, and small-size applications, such as wearable devices, spectrum analyzers, and data acquisition units. They are also easily expandable, highly compatible with advanced processes, and can achieve 14-bit accuracy and above, sampling rates of hundreds of MSPS, and power consumption as low as nW, demonstrating significant advantages in both power consumption and efficiency. However, during CMOS manufacturing, comparator offset and capacitor mismatch are introduced. These variations cause an overall shift in the ADC's output value and introduce nonlinearity issues into the DAC, affecting the comparator's output. Errors caused by these non-ideal factors reduce the overall performance of the ADC. On the other hand, comparator noise is also a limiting factor in the design of high-resolution SAR ADCs.

[0005] To improve the nonlinearity of the DAC in SAR ADCs, calibration is the most common method. Calibration can generally be divided into analog front-end calibration, analog back-end calibration, digital front-end calibration, and digital back-end calibration. Analog front-end calibration obtains the capacitance deviation of the capacitor array after the chip powers on but before normal analog-to-digital conversion. During normal operation, the capacitance of the capacitor array is changed to achieve encoding correction. Analog back-end calibration adds extra cycles during normal chip operation to correct deviations caused by non-ideal factors such as process conditions, temperature, and voltage fluctuations in real time. Digital front-end calibration calculates and stores the actual weight of each capacitor after the chip powers on but before normal analog-to-digital conversion. During normal operation, the SAR ADC output code is ANDed with the actual weight to obtain the final output code. Digital back-end calibration obtains an ideal value through an accurate reference ADC during normal operation and compares it with the actual DAC quantization result. The resulting error is then used to adjust the weight of the current capacitor bit in real time, reducing the impact of non-ideal factors.

[0006] For high-precision successive approximation analog-to-digital converters (ADCs), noise limits their sampling accuracy, primarily stemming from sampling noise and comparator noise. To achieve sufficient sampling noise and meet capacitor mismatch requirements, high-precision successive approximation ADCs typically employ large unit capacitors. However, large capacitor arrays generate significant second-order effects and increase overall power consumption. Conversely, low-noise comparators often require large currents to meet speed and accuracy requirements. Common methods for reducing comparator noise include averaging comparator noise by making multiple decisions from oversampling at the cost of additional cycles, and employing a two-stage pipelined successive approximation ADC. However, these methods do not necessarily result in significant performance improvements.

[0007] In recent years, noise shaping technology in Delta-Sigma ADCs has been gradually applied to successive approximation analog-to-digital converters. Combined with oversampling, it can move the in-band noise of successive approximation ADCs to outside the passband, greatly improving the accuracy of the ADC. However, it is currently mainly used in low-to-medium precision scenarios to achieve high signal-to-noise ratio with low-to-medium precision successive approximation ADCs, but it cannot solve the problems of comparator offset and capacitor mismatch.

[0008] As can be seen from the above, comparator misalignment, capacitor mismatch, sampling noise, and comparator noise are the main problems limiting high-precision successive approximation analog-to-digital converters. Neither individual corrections nor noise shaping can completely solve all the problems. Summary of the Invention

[0009] In view of the above, the present invention provides a dual passive noise shaping correction method for high-precision successive approximation ADCs, which integrates passive noise shaping technology into the correction technology and reuses sampling integration capacitors. The structure is simple, and the accuracy of correction is significantly improved with less power consumption. It also increases the overall signal-to-noise ratio and spurious-free dynamic range, thereby improving the overall efficiency of SARADC.

[0010] A dual passive noise shaping and correction method for high-precision successive approximation ADCs firstly modifies the structure of the successive approximation ADC by changing its dual-ended input comparator to a four-ended input comparator, and adds a correction DAC and two pairs of sampling and integrating capacitors to the main DAC in the digital-to-analog converter; the correction method includes:

[0011] Correction Phase: The offset voltage code of the comparator and the mismatch code of each capacitor in the main DAC are obtained by switching the corresponding switches in the digital-to-analog converter. During this process, after each conversion of the comparator offset voltage or the mismatch of one capacitor, the resulting residual voltage after conversion is sampled, integrated, and proportionalized, and then added to the input signal of the comparator for the next conversion to achieve feedforward passive noise shaping. Then, the offset voltage code of the comparator and the mismatch code of each capacitor in the main DAC are combined and calculated to obtain the correction code of the comparator offset voltage (in this coding method, it is equal to the offset voltage code) and the correction code of the mismatch of each capacitor in the main DAC.

[0012] During normal operation: The corresponding correction code is added to the correction DAC to achieve offset compensation and mismatch compensation. After each complete analog-to-digital conversion, the residual voltage generated after the analog-to-digital conversion is directly integrated by reusing part of the sampling integration capacitor. The integration result is then added to the original input signal of the comparator after proportional operation to achieve passive noise shaping.

[0013] Furthermore, the original digital-to-analog converter included a main DAC, which consisted of two rows of differential capacitor arrays (P-type and N-type). The modified digital-to-analog converter added a correction DAC, which had the same structure as the main DAC. The upper plates of the P-type and N-type capacitor arrays in the correction DAC were connected in parallel with the upper plates of the P-type and N-type capacitor arrays in the main DAC via bridge capacitors. Additionally, two pairs of sampling and integrating capacitors C were added. C,P and C C,N And C W,P and C W,N C C,P and C C,N During the calibration phase, it performs sampling and integration functions, and during the normal operation phase, it performs sampling functions, while C... W,P and C W,NIt only performs integration functions during normal operation; the number of bits in the capacitor array of the main DAC is n+1, and the number of bits in the capacitor array of the correction DAC is m+1, where n is the number of bits in the successive approximation ADC and m is a self-defined natural number.

[0014] Furthermore, the comparator's offset voltage encoding is obtained during the correction phase through the following process;

[0015] A1. Initialize the main DAC, correction DAC, and sampling integration capacitors: Connect the upper and lower plates of all capacitors in the main DAC and correction DAC to a common-mode voltage V. CM , so that capacitor C C,P C C,N C W,P and C W,N Both the upper and lower plates are grounded;

[0016] A2. Disconnect the upper plates of all capacitors in the main DAC and correction DAC from V. CM The connection allows all the lower plates of the capacitors in the N-pole capacitor array of the calibration DAC to be connected to the reference voltage V. REF ;

[0017] A3. Perform SAR logic conversion on the correction DAC. The resulting code is the offset voltage code of the comparator and is stored. The highest bit is the sign bit. A sign bit of 0 indicates that the offset voltage is negative and a sign bit of 1 indicates that the offset voltage is positive.

[0018] A4. Disconnect capacitor C C,P and C C,N The connection between the upper plate and ground makes C C,P The upper plate is connected to the upper plate of the P-type capacitor array in the main DAC, making C C,N The upper plate is connected to the upper plate of the N-pole capacitor array in the main DAC to collect the voltage margin.

[0019] Furthermore, the mismatch code for each capacitor in the main DAC is obtained during the correction phase through the following process:

[0020] B1. Disconnect capacitor C C,P The upper plate is connected to the upper plate of the P-type capacitor array in the main DAC, and C C,P The upper plate is connected to the newly added non-inverting input port of the comparator; capacitor C is disconnected. C,N The upper plate is connected to the upper plate of the N-pole capacitor array in the main DAC, and C C,N The upper plate is connected to the newly added inverting input port of the comparator; this connection method is used to achieve noise shaping.

[0021] B2. For the k-th capacitor in the main DAC, where k is a natural number and 1≤k≤n, ensure that the lower plate of the (k+1)th to (n+1)th capacitors in the P-type and N-type capacitor arrays of the main DAC is always connected to the common-mode voltage V. CM ;

[0022] B3. Initially, connect the upper plates of all capacitors in the main DAC and the correction DAC to V. CM ;

[0023] In the main DAC, the lower plate of the k-th capacitor in the P-type capacitor array is grounded, and the lower plate of the k-th capacitor in the N-type capacitor array is connected to V. REF The lower plates of capacitors at positions 1 to k-1 of the P-type capacitor array are connected to V. REF The lower plates of capacitors 1 to k-1 in the N-pole capacitor array are grounded. At this time, the voltage on the upper plate of the capacitor in the main DAC is weighted and summed with the residual voltage generated in the previous conversion, then fed into a comparator for judgment. The comparator output reflects whether the deviation between the k-th capacitor in the main DAC and the capacitors 1 to k-1 is positive or negative. If the comparator output is 0, it indicates a negative deviation. The lower plate of the m-th capacitor in the P-pole capacitor array of the correction DAC is grounded, and the lower plate of the m-th capacitor in the N-pole capacitor array of the correction DAC is connected to V... REF If the comparator output is 1, it indicates that the deviation is positive, and the state of the capacitor in the correction DAC remains unchanged.

[0024] B4. Perform SAR logic conversion on the correction DAC to obtain the mismatch code of the k-th capacitor in the main DAC.

[0025] Furthermore, in the correction stage, the correction code for each capacitor mismatch in the main DAC is calculated through the following process;

[0026] B5. For the k-th capacitor in the main DAC, subtract the mismatch code of the capacitor from the comparator offset voltage code;

[0027] B6. Calculate the correction code for the k-th capacitor mismatch in the main DAC according to the following formula;

[0028]

[0029] Where: x k The correction code for the k-th bit capacitor mismatch in the main DAC, x k+1 The correction code for capacitor mismatch at bit k+1 in the main DAC, Exp k The result of subtracting the mismatch code of the k-th capacitor in the main DAC from the comparator offset voltage code is Exp. k+1 The result is the subtraction of the mismatch code of the (k+1)th capacitor in the main DAC and the comparator offset voltage code.

[0030] B7. For each complete SAR logic conversion of the DAC, capacitor C... C,P and C C,N Then, the voltage of the upper plates of the P-type and N-type capacitor array in the main DAC is sampled once to achieve noise shaping.

[0031] Furthermore, by traversing from the most significant bit in steps B1 to B7, the correction code for capacitor mismatch in each bit of the main DAC can be obtained.

[0032] Furthermore, during the normal operation phase, the corresponding correction code is added to the correction DAC through the following process;

[0033] C1. Initially, connect the upper plates of all capacitors in the main DAC and the correction DAC to the common-mode voltage V. CM In the main DAC, the lower plate of the P-type capacitor array is connected to the positive input voltage V. INP In the main DAC, the lower plate of the N-stage capacitor array is connected to the inverting input voltage V. INN The lower plate of all capacitors in the calibration DAC is connected to V. CM Capacitor C C,P C C,N C W,P and C W,N Both the upper and lower plates are grounded;

[0034] C2. In DAC calibration, disconnect all capacitor upper plates from V. CM The connections and corresponding connections of all lower plates of the capacitors are established, and the upper plate of the highest-position capacitor in the P-type capacitor array is connected to the reference voltage V. REF The upper plates of the remaining capacitors are grounded; the upper plate of the highest-ranking capacitor in the N-pole capacitor array is grounded, and the upper plates of the remaining capacitors are connected to V. REF ;

[0035] C3. The correction DAC is logically controlled based on the sum of the symbol code z0 and the offset voltage code. Specifically, if the sum of the codes for a given bit is 0, the lower plate of the capacitor for that bit in the correction DAC is grounded; if the sum of the codes for a given bit is 1, the lower plate of the capacitor for that bit in the correction DAC is connected to V. REF The symbol encoding z0 has m bits, where the highest bit is 1 and the remaining bits are 0.

[0036] C4. The main DAC enters normal operating mode and performs SAR logic conversion operations starting from the most significant bit. When the k-th bit transitions, the correction code x for the capacitor mismatch at the k-th bit in the main DAC is applied. k The code z is calculated using the following formula. k And then according to the encoding z k The correction DAC is controlled by logic, where k is a natural number and 1≤k≤n, and n is the number of bits of the successive approximation ADC;

[0037] z k =z0+s+x k

[0038] Where: s is the offset voltage code;

[0039] C5. After the SAR logic conversion operation of the DAC in the (a-1)th cycle is completed, the capacitor C... C,P and C C,N The upper plates of the capacitors are connected to the upper plates of the P-type and N-type capacitor arrays in the main DAC, respectively.

[0040] After the (a-1)th cycle ends and before the sampling of the ath cycle begins, make capacitor C... W,P and C W,N Both the upper and lower plates are connected to ground to remove residual voltage; then C is connected... W,P The upper plate of the capacitor and the upper plate of the P-type capacitor array in the main DAC, as well as the C-type capacitor... C,P The upper plates are connected together, and C W,N The upper plate of the capacitor and the upper plate of the N-pole capacitor array in the main DAC, as well as the C C,N The upper plates are connected together to collect the residual voltage generated after the main DAC logic conversion;

[0041] During the a-th period, the capacitance C W,P and C W,N The upper plate is connected to the newly added positive and negative input ports of the comparator, respectively, and then the signals are weighted and summed with the signals of the other two input ports of the comparator, where a is a natural number greater than 1.

[0042] The correction method of this invention belongs to analog front-end correction. It combines noise shaping technology with correction algorithms. Within a certain period after the chip is powered on, it can obtain higher-precision correction codes for SAR ADC capacitor mismatch and comparator offset voltage through a limited correction DAC capacitor array and noise shaping technology. In normal operating mode, this invention again combines noise shaping technology to add the correction code to the main DAC in the form of an analog quantity, reducing the impact of non-ideal factors. Therefore, this invention has the following beneficial technical effects:

[0043] 1. The correction method of this invention employs noise shaping technology twice and reuses the sampling integration capacitor, achieving higher accuracy analog-to-digital conversion with a smaller capacitor array area, improving capacitor utilization, and demonstrating more significant advantages in correction effect and final analog-to-digital conversion result compared to traditional correction algorithms.

[0044] 2. The correction method of the present invention does not require complex changes to the traditional SAR ADC, but only requires increasing the size of the capacitor array and the number of comparator input interfaces. Furthermore, the switching logic of this method is consistent with the logic of the traditional SAR ADC and is easy to implement.

[0045] 3. The correction method of the present invention does not have high requirements for the accuracy and matching degree of the capacitor of the correction DAC, and can be adapted and adjusted according to the size of the main DAC capacitor array, making it highly portable.

[0046] 4. The correction method of the present invention does not increase additional static power consumption, and can enhance the matching of the capacitors of the main DAC and the correction DAC through appropriate layout, effectively reduce sampling noise, and improve the signal-to-noise ratio and spurious-free dynamic range of the SAR ADC.

[0047] 5. The correction method of the present invention can collect deviation values ​​multiple times during the correction stage, thereby enhancing the effect of noise shaping, and can take the average value of the correction code value to further improve the correction effect. Attached Figure Description

[0048] Figure 1 This is a schematic diagram of the principle architecture of a novel first-order noise shaping circuit.

[0049] Figure 2 This is a schematic diagram of the new first-order noise shaping signal process.

[0050] Figure 3 This is a schematic diagram of the first-order feedforward noise shaping principle architecture.

[0051] Figure 4 This is a schematic diagram of the first-order feedforward noise shaping signal flow.

[0052] Figure 5 This is a schematic diagram of the complete circuit architecture of the SAR ADC of the present invention.

[0053] Figure 6 This is a schematic diagram illustrating the dynamic performance of a 13-bit correction DAC.

[0054] Figure 7 This is a schematic diagram of the dynamic performance of a 16-bit SAR ADC after applying the correction method of the present invention. Detailed Implementation

[0055] To describe the present invention in more detail, the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0056] This invention relates to a dual passive noise shaping and correction method for high-precision successive approximation analog-to-digital converters (ADCs). It requires structural modifications to the traditional successive approximation ADC, including adding a pair of correction DACs, two pairs of sampling and integrating capacitors, and changing the comparator's two-terminal input to a four-terminal input. The correction DACs are connected to the main DAC via bridge capacitors, and the sampling and integrating capacitors are connected to the main DAC via a switch. The correction DACs calculate and store the deviation information of capacitor mismatch and comparator offset, while the sampling and integrating capacitors shape the noise, achieving higher-precision ADC conversion with a limited capacitor array.

[0057] The correction method of this invention includes two working stages: a correction stage and a normal operating stage. In the correction stage, the comparator's offset voltage and the capacitance mismatch of the main DAC are reflected by the correction DAC and stored in a register in encoded form. Then, a correction code is obtained through calculation. Furthermore, a novel first-order noise shaping technique is applied during this process to improve the encoding accuracy of the correction DAC. In the normal operating stage, the corresponding deviation information is added to the main DAC through the correction DAC. The capacitance mismatch of the correction DAC has little impact on the quantization process, therefore, it is assumed that the capacitance of the correction DAC is accurate. On the other hand, in the normal operating stage, first-order feedforward noise shaping is employed, in which the sampling integration capacitor is reused, further improving the conversion accuracy of the ADC.

[0058] like Figure 1 and Figure 2 As shown, the novel first-order noise shaping, compared to traditional noise shaping, uses only one capacitor to handle both sampling and integration, reducing signal attenuation and the gain required by subsequent comparators. Its specific working principle is as follows:

[0059] After the (a-1)th cycle of the SAR ADC conversion is completed, switch φ1 closes, and the remaining voltage is sampled onto capacitor C1. This voltage is then integrated with the voltage on the upper plate of C1 from the previous cycle. Assume C1 = 4C. DAC Then the voltage of C1 is:

[0060] V int1 (a) = 4 / 5·V int1 (a-1)+1 / 5·V res (a-1)

[0061] Disconnect φ1, and assume g1 = 4, then V in and V int1 The comparators use a 1:4 weighted summation method, and the sum determines the comparator's output. After the SAR ADC conversion is completed in the a-th cycle, the final digital output is:

[0062] D out (a)=V in (a)+4Vint1 (a)+Q(a)

[0063] And because of V res (a)=V in (a)-D out Therefore, the final system transfer function is:

[0064] D out (z)=V in (z)+(1-0.8z -1 )Q(z)

[0065] This noise shaping structure pushes the NTF zero to z=0.8, reducing the attenuation of the input signal path and achieving -13dB noise suppression, with a two-bit increase in ENOB. The integration of this architecture requires additional sampling cycles, but since the comparison of the last SAR ADC conversion is completed and the DAC needs to be established, the integration of this architecture can be embedded into the last SAR ADC. Furthermore, because the clock reference speed during the correction phase is relatively slow, the noise shaping effect is significant.

[0066] like Figure 3 and Figure 4 As shown, the first-order feedforward passive noise shaping circuit acquires the feedforward signal (voltage margin) through switching, integrates it, and then adds the integrated feedforward signal to the input signal to achieve noise shaping. The specific working principle is as follows:

[0067] After the (a-1)th cycle of SAR ADC conversion is completed, switch φ3 closes, and the residual voltage is sampled onto capacitor C0. Assume C0 = C DAC / 3, the voltage margin collected is:

[0068] V CO (a-1)=3 / 4·V res (a-1)

[0069] Then disconnect φ3 and close φ1, and integrate the collected residual value across C1. At this time, the voltage of C1 is:

[0070] V int1 (a) = 3 / 4·V int1 (a-1)+1 / 4·3 / 4·V res (a-1)

[0071] Assuming g1 = 4, Vin and Vint1 are added together by a comparator with a weighted ratio of 1:4. The result of this addition determines the comparator's output. After the SAR ADC conversion is completed in the a-th cycle, the final digital output is:

[0072] D out (a)=V in(a)+4V int1 (a)+Q(a)

[0073] And because of V res (a)=V in (a)-D out Therefore, the final system transfer function is:

[0074] D out (z)=V in (z)+(1-0.75z -1 )Q(z)

[0075] This noise shaping structure pushes the NTF zero point to z=0.75, reducing the attenuation of the input signal path and avoiding a 6dB signal-to-noise ratio loss compared to a feedback architecture. When z=1, the NTF=0.25, achieving -12dB in-band noise suppression capability (ENOB increases by approximately 2 bits). The structure is simple, easy to implement, and highly effective.

[0076] During the calibration phase, when the offset voltage information of the comparator is obtained, the influence of the main DAC capacitor array is shielded. The offset voltage information of the comparator is represented by the calibrated DAC and stored in the register in the form of an encoding for subsequent calculation with the capacitor deviation information.

[0077] During the calibration phase, when obtaining capacitance deviation information, assuming the ADC has N bits, it actually contains N+1 equivalent capacitance bits (due to redundant bits). n (n=1) * (1, ..., N) represents the weight of the nth element, where 1 * This represents a redundant bit, which measures the equivalent capacitance C of the nth bit. n The proportion of the total equivalent capacitance of the DAC. Ideally, w n =2 n-1 However, in reality, the weight of each element is biased. The unit equivalent capacitance is defined as:

[0078]

[0079] This yields the actual weight of each capacitor:

[0080]

[0081] The weight deviation of the nth position is:

[0082] w εn =w n -2 n-1 (n=1) * ,1,…,N)

[0083] Taking the Nth capacitor as an example, we assume wN With w 1* ~w N-1 The deviation of the sum is expressed as Exp using the capacitor array of the correction DAC. N The total weight is w T Based on the previous analysis, it is necessary to ensure that the change in the capacitor array during the Nth bit transition is w. T / 2, then the capacitor array of the DAC needs to be corrected in conjunction with the Nth bit to make the transition. Assume that the corresponding bypass array's encoded value is x at this time. N Then we can obtain the following three relations:

[0084]

[0085]

[0086] w N +k·x N =w T / 2

[0087] Based on the above relationship, we can obtain:

[0088]

[0089] It is important to note that due to the presence of bridge capacitors connecting the correction DAC and the main DAC, the weights represented by the correction DAC capacitor array encoding differ from the weights w of the main capacitor array. n While there is a fixed coefficient k, since the addition and subtraction operations of the correction code are all performed on the bypass array, the existence of coefficient k does not affect the accuracy of subsequent correction.

[0090] Similarly, analyzing the N-1 capacitance yields three similar relationships:

[0091]

[0092]

[0093] w N-1 +k*x N-1 =w T / 4

[0094] Based on the above relationship, we can obtain:

[0095]

[0096] Following this logic, we can obtain the formula for the capacitance deviation of each bit:

[0097]

[0098] To facilitate iterative circuit design, Exp is preset.N+1 =0, x N+1 =0, so the above formula can be rewritten as:

[0099]

[0100] Based on the above calculation process, the mismatch information of each capacitor in the main DAC can be obtained and stored in the register.

[0101] During normal operation, each switch reads the capacitor mismatch information from the corresponding register and adds it to the calibration DAC to compensate for the corresponding deviation, completing the entire calibration process. It's important to note that the capacitor mismatch information obtained during this process includes the comparator's offset voltage; therefore, the actual capacitor mismatch information stored in the register needs to be reduced by the comparator's offset voltage information. During normal operation, the comparator's offset voltage information is first added to the calibration capacitor array, and this is only done at the beginning of a complete A / D conversion. Subsequently, each time the main DAC's capacitor array switch changes, the corresponding capacitor's deviation information is added through the calibration DAC to correct the current main DAC's capacitors.

[0102] The SAR ADC structure in this embodiment of the invention is as follows: Figure 5 As shown, it consists of a main DAC, a correction DAC, and two pairs of sampling and integrating capacitors. The main DAC adopts a bridge capacitor structure, which is composed of a high 8-bit capacitor array and a low 8-bit capacitor array connected in series through a bridge capacitor. The correction DAC also adopts a bridge capacitor structure, which is composed of a high 7-bit capacitor array and a low 6-bit capacitor array connected in series through a bridge capacitor. The correction DAC is also connected in series with the main DAC through a bridge capacitor.

[0103] The comparator offset voltage correction operation steps are as follows: throughout the process, the capacitors of the main DAC are connected to the capacitor array, but do not participate in the operation.

[0104] (1) Initialize the states of the main DAC and the correction DAC. Connect the upper plates of the capacitors of both the main DAC and the correction DAC to the common-mode voltage V. CM Correcting the DAC capacitor's lower plate connected to V CM .

[0105] (2) Disconnect all capacitor upper plates from V CM The connection was corrected by reconnecting the lower plate of the N-terminal capacitor array of the DAC to the reference voltage V. REF .

[0106] (3) Perform SAR logic operation on the correction DAC. The code obtained from the correction DAC is the offset voltage information of the comparator, which is stored in the corresponding register. The highest bit is the sign bit, where "0" indicates that the offset voltage is negative and "1" indicates that the offset voltage is positive.

[0107] (4) Disconnect CC The connection between the upper electrode plate and the ground. C C,P Connected to the upper plate of the P terminal of the main DAC capacitor array, C C,N Connect to the upper plate at the N-terminal of the main DAC capacitor array to collect the voltage margin.

[0108] The steps for capacitor mismatch correction are as follows, taking the correction of the k-th capacitor of the main DAC as an example.

[0109] (1) Disconnect C C The connection to the upper plate of the main DAC, and the connection to the newly added input interface after the modification, namely C C,P The upper electrode plate connects to the newly added interface at the P end, C C,P The upper plate is connected to the newly added interface at the N terminal. Through this connection, the residual voltage from the previous conversion is added to the correction process for obtaining the capacitor correction code, thus performing noise shaping.

[0110] (2) The lower plates of the P and N terminals of the k+1 to 16 bits of the main DAC capacitor array are always connected to V. CM .

[0111] (3) Initially, connect the upper plates of all capacitors in the main DAC and correction DAC arrays to V. CM In the main DAC, the lower plate of the k-th capacitor in the P-terminal capacitor array is grounded, and the lower plate of the k-th capacitor in the N-terminal capacitor array is connected to V. REF The lower plates of capacitors at positions 1 to k-1 of the P-terminal capacitor array are connected to V. REF The lower plates of capacitors 1 to k-1 in the N-terminal capacitor array are grounded. At this time, the voltage on the upper plate of the main DAC is weighted and added to the residual voltage from the previous conversion. This sum is then fed into a comparator for judgment. The comparator output reflects whether the deviation between the k-th capacitor and the capacitors 1 to k-1 in the main DAC is positive or negative. If the comparator output is 0, it indicates a negative deviation. The lower plate of the m-th capacitor in the P-terminal capacitor array of the correction DAC is grounded, and the lower plate of the m-th capacitor in the N-terminal capacitor array is connected to V. REF If the comparator output is 1, it indicates that the deviation is positive, and the state of the capacitor in the correction DAC remains unchanged.

[0112] (4) Perform SAR logic conversion on the correction DAC, subtract the code obtained from the correction DAC from the offset voltage code of the comparator, and obtain the result Exp. k .

[0113] (5) Calculate the correction code x of the k-th capacitor in the main DAC according to the following formula. k :

[0114]

[0115] Where: xk+1 The correction encoding of the (k+1)th capacitor in the main DAC, Exp k+1 This is the result of subtracting the comparator offset voltage code from the code obtained from the calibration DAC for the (k+1)th bit capacitor in the main DAC through steps B1 to B4.

[0116] (5) Finally, according to the formula Obtain the correction code for the current bit capacitance, which is used for correction during normal operation.

[0117] In normal operating mode, the steps for adding correction coding and SAR logical conversion are as follows:

[0118] (1) Initially, connect the upper plates of all capacitors in the capacitor arrays of the main DAC and the correction DAC to the common-mode voltage V. CM All capacitors in the P-terminal capacitor array of the main DAC have their lower plates connected to the non-inverting input voltage V. INP All capacitors in the N-terminal capacitor array have their lower plates connected to an inverting input voltage V. INN In the capacitor array of the calibration DAC, the lower plate of all capacitors is connected to V. CM Sampling integration capacitor C C C W Both the upper and lower plates are grounded.

[0119] (2) In DAC calibration, disconnect the upper plates of all capacitors from V. CM The connections of the capacitors and the lower plates of all capacitors are as follows: the highest bit of the P-terminal capacitor array is connected to V. REF The remaining capacitors are grounded; the highest bit of the N-terminal capacitor array is grounded, and the remaining capacitors are connected to V. REF .

[0120] (3) The correction DAC is logically controlled based on the result of adding the symbol code z0 and the offset voltage code. That is, if the code of a certain bit is 0, the lower plate of the capacitor of that bit is grounded; if the code of a certain bit is 1, the lower plate of the capacitor of that bit is connected to the reference voltage V. REF .

[0121] (4) The main DAC enters normal working state and performs SAR logic conversion operation starting from the most significant bit. When the k-th bit transitions, the correction code x of the capacitor at that bit is used. k The code z is calculated using the following formula. k According to the code z k Perform logic control on the calibration DAC;

[0122] z k =z0+s+x k

[0123] Where: the symbol code z0 has m bits, the highest bit is 1, and the rest are 0, and s is the offset voltage code.

[0124] (5) After the SAR logic conversion operation in the (a-1)th cycle is completed, C C,P and C C,N It is connected to the upper plate of the main DAC capacitor array.

[0125] After the (a-1)th cycle ends and before the sampling of the ath cycle begins, C W,P C W,N Both the upper and lower plates are connected to ground to remove residual voltage; then C is connected... W,P C W,N Upper plate and main DAC and C C,P C C,N The upper plates are connected together to collect the residual voltage after the SAR logic conversion is completed.

[0126] In the a-th SAR conversion period, C W,P C W,N The upper plate is connected to the newly added input interface of the modified comparator, and performs weighted calculations with the other two input interfaces of the comparator.

[0127] Through dual passive noise shaping technology, the corrected DAC can achieve near 15-bit analog-to-digital conversion with a 13-bit capacitor array, such as... Figure 6 As shown, the overall 16-bit SAR ADC shows a significant improvement in dynamic performance. Within a certain bandwidth, the effective bits can reach 18-bit, with a marked improvement in spurious-free dynamic range and signal-to-noise ratio, such as... Figure 7 As shown.

[0128] The above description of the embodiments is provided to enable those skilled in the art to understand and apply the present invention. It will be apparent to those skilled in the art that various modifications can be made to the above embodiments, and the general principles described herein can be applied to other embodiments without inventive effort. Therefore, the present invention is not limited to the above embodiments, and any improvements and modifications made to the present invention by those skilled in the art based on the disclosure thereof should be within the scope of protection of the present invention.

Claims

1. A dual passive noise shaping and correction method applied to a high-precision successive approximation ADC, characterized in that: First, the successive approximation ADC is structurally modified by changing its dual-input comparator to a four-input comparator, and a correction DAC and two pairs of sampling integration capacitors are added to the main DAC in the digital-to-analog converter. The correction method includes: Correction Phase: The offset voltage code of the comparator and the mismatch code of each capacitor in the main DAC are obtained by switching the corresponding switches in the digital-to-analog converter. During this process, after each conversion of the comparator offset voltage or the mismatch of one capacitor, the resulting residual voltage after conversion is sampled, integrated, and proportionalized, and then added to the input signal of the comparator for the next conversion to achieve feedforward passive noise shaping. Then, the offset voltage code of the comparator and the mismatch code of each capacitor in the main DAC are combined and calculated to obtain the correction code of the comparator offset voltage and the correction code of the mismatch of each capacitor in the main DAC. Normal operation phase: The corresponding correction code is added to the correction DAC to achieve offset compensation and mismatch compensation. After each complete analog-to-digital conversion, the residual voltage generated after analog-to-digital conversion is directly integrated by reusing part of the sampling integration capacitor. The integration result is then added to the original input signal of the comparator after proportional operation to achieve passive noise shaping. The original digital-to-analog converter (DAC) consisted of a main DAC, which was composed of two rows of differential capacitor arrays (P-type and N-type). The upgraded DAC added a correction DAC, which had the same structure as the main DAC. The upper plates of the P-type and N-type capacitor arrays in the correction DAC were connected in parallel with the upper plates of the P-type and N-type capacitor arrays in the main DAC via bridge capacitors. Additionally, two pairs of sampling and integrating capacitors C were added. C,P and C C,N And C W,P and C W,N C C,P and C C,N During the calibration phase, it performs sampling and integration functions, and during the normal operation phase, it performs sampling functions, while C... W,P and C W,N It only performs integration during normal operation; the capacitor array in the main DAC has a bit depth of [number missing]. n +1, the number of bits in the capacitor array of the correction DAC is... m +1, n For the number of bits in a successive approximation ADC, m It is a natural number that is set by the user.

2. The dual passive noise shaping and correction method according to claim 1, characterized in that: The comparator offset voltage encoding is obtained during the correction phase through the following process: A1. Initialization of main DAC, correction DAC and sampling integration capacitors: the upper and lower plates of all capacitors in the main DAC and correction DAC are connected to the common mode voltage V CM , the upper and lower plates of the capacitors C C,P , C C,N , C W,P and C W,N are connected to ground; A2. Disconnect the upper plates of all capacitors in the main DAC and correction DAC from V. CM The connection allows all the lower plates of the capacitors in the N-pole capacitor array of the calibration DAC to be connected to the reference voltage V. REF ; A3. Perform SAR logic conversion on the correction DAC. The resulting code is the offset voltage code of the comparator and is stored. The highest bit is the sign bit. A sign bit of 0 indicates that the offset voltage is negative and a sign bit of 1 indicates that the offset voltage is positive. A4. Disconnect capacitor C C,P and C C,N The connection between the upper plate and ground makes C C,P The upper plate is connected to the upper plate of the P-type capacitor array in the main DAC, making C C,N The upper plate is connected to the upper plate of the N-pole capacitor array in the main DAC to collect voltage margin.

3. The dual passive noise shaping and correction method according to claim 1, characterized in that: The mismatch code for each capacitor in the main DAC is obtained during the correction phase through the following process: B1. Disconnect capacitor C C,P The upper plate is connected to the upper plate of the P-type capacitor array in the main DAC, and C C,P The upper plate is connected to the newly added non-inverting input port of the comparator; capacitor C is disconnected. C,N The upper plate is connected to the upper plate of the N-stage capacitor array in the main DAC, and C C,N The upper plate is connected to the newly added inverting input port of the comparator; this connection method is used to achieve noise shaping. B2. For the first in the main DAC k Position capacitor. k It is a natural number and 1≤ k ≤ n This makes the first of the P-type and N-type capacitor arrays in the main DAC... k +1~ n The lower plate of the +1 capacitor is always connected to the common-mode voltage V. CM ; B3. Initially, connect the upper plates of all capacitors in the main DAC and the correction DAC to V. CM ; In the main DAC, the first P-type capacitor array k The lower plate of the capacitor is grounded, and the first capacitor in the N-pole capacitor array... k The lower plate of the capacitor is connected to V. REF The first of the P-type capacitor array k -1 capacitor lower plate connected to V REF The first of the N-pole capacitor array k -1. The lower plate of the capacitor is grounded; at this time, the voltage on the upper plate of the capacitor in the main DAC is weighted and summed with the residual voltage generated in the previous conversion, and then fed into the comparator for judgment. The output of the comparator reflects the voltage of the capacitor in the main DAC. k The capacitance and the first~ k The deviation of the -1 capacitor is determined by whether it is positive or negative. If the comparator output is 0, it indicates that the deviation is negative, and the deviation of the -1 capacitor in the DAC will be corrected. m The lower plate of the capacitor is grounded, which will correct the N-pole capacitor array in the DAC. m The lower plate of the capacitor is connected to V. REF If the comparator output is 1, it indicates that the deviation is positive, and the state of the capacitor in the correction DAC remains unchanged. B4. Perform SAR logic conversion on the correction DAC to obtain the first... k Mismatch coding of bit capacitors.

4. The dual passive noise shaping and correction method according to claim 3, characterized in that: During the correction phase, the correction code for each capacitor mismatch in the main DAC is calculated through the following process; B5. For the first in the main DAC k The mismatch code of the bit capacitor is subtracted from the comparator offset voltage code; B6. Calculate the first [number] in the main DAC according to the following formula. k Correction coding for bit capacitor mismatch; in: The main DAC k Correction coding for bit capacitor mismatch The main DAC k +1 bit capacitor mismatch correction code The main DAC k The result of subtracting the comparator offset voltage code from the mismatch code of the bit capacitor. The main DAC k The result of subtracting the comparator offset voltage code from the mismatch code of the +1 bit capacitor; B7. For each complete SAR logic conversion of the DAC, capacitor C... C,P and C C,N Then, the voltage of the upper plates of the P-type and N-type capacitor array in the main DAC is sampled once to achieve noise shaping.

5. The dual passive noise shaping and correction method according to claim 4, characterized in that: By traversing from the highest bit in steps B1 to B7, the correction code for capacitor mismatch in each bit of the main DAC can be obtained.

6. The dual passive noise shaping and correction method according to claim 1, characterized in that: During the normal operation phase, the corresponding correction code is added to the correction DAC through the following process; C1. Initially, connect the upper plates of all capacitors in the main DAC and the correction DAC to the common-mode voltage V. CM In the main DAC, the lower plate of the P-type capacitor array is connected to the positive input voltage V. INP In the main DAC, the lower plate of the N-stage capacitor array is connected to the inverting input voltage V. INN The lower plate of all capacitors in the calibration DAC is connected to V. CM Capacitor C C,P C C,N C W,P and C W,N Both the upper and lower plates are grounded; C2. In DAC calibration, disconnect all capacitor upper plates from V. CM The connections and corresponding connections of all lower plates of the capacitors are established, and the upper plate of the highest-position capacitor in the P-type capacitor array is connected to the reference voltage V. REF The upper plates of the remaining capacitors are grounded; the upper plate of the highest-ranking capacitor in the N-pole capacitor array is grounded, and the upper plates of the remaining capacitors are connected to V. REF ; C3. Based on symbol encoding z The result of adding 0 to the offset voltage code is used for logic control of the correction DAC. Specifically, if the result of adding a certain bit is 0, the lower plate of the capacitor for that bit in the correction DAC is grounded; if the result of adding a certain bit is 1, the lower plate of the capacitor for that bit in the correction DAC is connected to V. REF The symbol encoding z The number of 0s is m The highest bit is 1, and the rest are 0; C4. The main DAC enters normal operating mode, performing SAR logic conversion operations starting from the most significant bit. k During a bit transition, according to the first bit in the main DAC k Correction code for bit capacitor mismatch x k The code is calculated using the following formula. z k And then according to the encoding z k Perform logic control on the correction DAC. k It is a natural number and 1≤ k ≤ n , n The number of bits for a successive approximation ADC; z k = z 0+ s + x k in: s Encoding the offset voltage; C5. Correcting the DAC in the first... a After the SAR logic conversion operation of -1 cycle is completed, capacitor C is... C,P and C C,N The upper plates of the capacitors are connected to the upper plates of the P-type and N-type capacitor arrays in the main DAC, respectively. In the a -1 cycle ended and the first a Before the start of each sampling cycle, capacitor C is... W,P and C W,N Both the upper and lower plates are connected to ground to remove residual voltage; then C is connected... W,P The upper plate of the capacitor and the upper plate of the P-type capacitor array in the main DAC, as well as the C-type capacitor... C,P The upper plates are connected together, and C W,N The upper plate of the capacitor and the upper plate of the N-pole capacitor array in the main DAC, as well as the C C,N The upper plates are connected together to collect the margin voltage generated after the main DAC logic conversion; In the a Within each cycle, the capacitance C W,P and C W,N The upper plates are connected to the newly added inverting and non-inverting input ports of the comparator, respectively, and then weighted and summed with the signals from the other two input ports of the comparator. a It is a natural number greater than 1.

7. The dual passive noise shaping and correction method according to claim 1, characterized in that: This correction method belongs to analog front-end correction. It combines noise shaping technology with correction algorithm. Within a certain period of time after the chip is powered on, it can obtain higher precision correction codes for SAR ADC capacitor mismatch and comparator offset voltage through a limited correction DAC capacitor array and noise shaping technology. In normal operating mode, this method again combines noise shaping technology to add correction codes to the main DAC in the form of analog signals, reducing the impact of non-ideal factors.

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