Switch port verification method, device and switch

Abstract

The present invention relates to the technical field of communication equipment verification, and discloses a switch port verification method, device and switch, which are implemented based on a port test fixture, wherein the port test fixture includes a test contact for establishing a one-to-one corresponding electrical connection relationship with each signal pin to be tested in the port to be tested; the method includes: when the test contact establishes an electrical connection relationship with the signal pin to be tested, controlling the corresponding register of the port to be tested to perform a predetermined operation, and obtaining the state change of the circuit where the signal pin to be tested is located; based on the state change of the circuit where the signal pin to be tested is located, determining the functional correctness and line connectivity between the port to be tested and the port management chip. Since the manual operation with complicated steps and difficult operation is omitted, the efficiency of switch port verification can be effectively improved, and the verification difficulty can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of communication equipment verification, and in particular to a switch port verification method, device and switch. Background Art

[0002] In order to ensure the correctness of the port management chip (CPLD / FPGA) function and the connectivity of the lines on the board, all low-speed signals of each port need to be verified. The contents that need to be verified mainly include: 1. The correctness of the mapping between the register and the pin in the port management chip; 2. The signal connectivity between the pin of the port management chip and the port socket. At the same time, the signals that need to be verified include: port status signal, which is used to map the port status signal pin input to the status register; and port control signal, which is used to control the register to control the port control signal status.

[0003] In the prior art, the port low-speed signal (control / status signal) is realized by manual testing, which is as follows: for the port control signal, the control signal state is changed by operating the corresponding control register, and then the corresponding control signal state is observed using a signal testing instrument (oscilloscope, multimeter, etc.), so as to determine the connectivity of the control signal; for the port status signal, the corresponding status signal level is changed (grounded / pull-up), and then the corresponding status signal state is determined by reading the status register value, so as to determine the connectivity of the status signal.

[0004] Since each type of port includes multiple low-speed port signals that need to be verified, the verification efficiency using existing testing methods is low; at the same time, the existing verification methods are difficult to operate. On the one hand, in order to ensure the correct mapping of signals and registers, the register end and the signal end need to be operated synchronously, which is difficult for a single person to operate; on the other hand, in order to ensure that the entire hardware path is verified, the test / control point should be located inside the port, making it difficult to lead out the signal. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention provides a switch port verification method, device and switch, which solve the problems in the prior art of low efficiency and great difficulty in verifying low-speed signals on ports.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A switch port verification method is implemented based on a switch port verification device, wherein the switch port verification device includes a port test fixture, and the port test fixture includes a test contact for establishing a one-to-one corresponding electrical connection relationship with each signal pin to be tested in the port to be tested;

[0008] The switch port verification method comprises:

[0009] When the test contact establishes an electrical connection relationship with the signal pin to be tested, controlling the corresponding register of the port to be tested to perform a predetermined operation, and obtaining a state change of the circuit where the signal pin to be tested is located;

[0010] Based on the state change of the circuit where the signal pin to be tested is located, the functional correctness and line connectivity between the port to be tested and the port management chip are determined.

[0011] Optionally, the port test fixture comprises a control signal test contact for establishing an electrical connection with a control signal pin to be tested, and a signal lamp is provided on the circuit where the control signal test contact is located;

[0012] The obtaining of the state change of the circuit where the signal pin to be tested is located includes:

[0013] Based on the change of the signal light, obtaining the state change of the circuit where the control signal pin to be tested is located;

[0014] The determining of the functional correctness and line connectivity between the port to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located includes:

[0015] Determine the mapping correctness between the control signal pin to be tested and the corresponding control register in the port management chip, and the connectivity between the control signal pin to be tested and the corresponding port in the port management chip.

[0016] Optionally, the port test fixture further comprises a status signal test contact for establishing an electrical connection relationship with a status signal pin to be tested, and the status signal test contact is connected to the circuit where the control signal test contact is located;

[0017] The step of obtaining the state change of the circuit where the signal pin to be tested is located also includes:

[0018] Reading the status register value of the port management chip to obtain the status change of the circuit where the status signal pin to be tested is located;

[0019] The determining of the functional correctness and line connectivity between the port to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located also includes:

[0020] According to the status register value, the mapping correctness between the status signal pin to be tested and the corresponding status register in the port management chip and the connectivity between the status signal pin to be tested and the corresponding port in the port management chip are determined.

[0021] Optionally, the test fixture further comprises an in-place signal test contact for establishing an electrical connection with the in-place signal pin to be tested, and the circuit where the in-place signal test contact is located is grounded;

[0022] The step of obtaining the state change of the circuit where the signal pin to be tested is located also includes:

[0023] Reading the in-place register value of the port management chip to obtain the state change of the circuit where the in-place signal pin to be tested is located;

[0024] The determining of the functional correctness and line connectivity between the port to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located also includes:

[0025] According to the in-place register value, the mapping correctness between the in-place signal pin to be tested and the corresponding in-place register in the port management chip and the connectivity between the in-place signal pin to be tested and the corresponding port in the port management chip are determined.

[0026] Optionally, after obtaining the state change of the circuit where the signal pin to be tested is located, the method further includes:

[0027] Display the state change of the circuit where the signal pin to be tested is located.

[0028] The present invention also provides a switch port verification device, which is applied to a port management chip, comprising:

[0029] A port test fixture, used to connect to the port to be tested, including test contacts that establish a one-to-one corresponding electrical connection relationship with each signal pin to be tested in the port to be tested;

[0030] an acquisition module, used to control the corresponding register of the port to be tested to perform a predetermined operation and acquire a state change of the circuit where the signal pin to be tested is located when the test contact establishes an electrical connection relationship with the signal pin to be tested;

[0031] The determination module is used to determine the functional correctness and line connectivity between the port to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located.

[0032] Optionally, the port test fixture comprises a control signal test contact for establishing an electrical connection with a control signal pin to be tested, and a signal lamp is provided on the circuit where the control signal test contact is located;

[0033] The acquisition module is used to acquire the state change of the circuit where the control signal pin to be tested is located based on the change of the signal light;

[0034] The determination module is used to determine the mapping correctness of the control signal pin to be tested and the corresponding control register in the port management chip, as well as the connectivity between the control signal pin to be tested and the corresponding port in the port management chip according to the state change of the circuit where the control signal pin to be tested is located.

[0035] Optionally, the port test fixture further comprises a status signal test contact for establishing an electrical connection relationship with a status signal pin to be tested, and the status signal test contact is connected to the circuit where the control signal test contact is located;

[0036] The acquisition module is used to read the status register value of the port management chip to obtain the status change of the circuit where the status signal pin to be tested is located;

[0037] The determination module is used to determine the mapping correctness of the state signal pin to be tested and the corresponding state register in the port management chip, and the connectivity between the state signal pin to be tested and the corresponding port in the port management chip according to the state register value.

[0038] Optionally, the test fixture further comprises an in-place signal test contact for establishing an electrical connection with the in-place signal pin to be tested, and the circuit where the in-place signal test contact is located is grounded;

[0039] The acquisition module is used to read the in-place register value of the port management chip to obtain the state change of the circuit where the in-place signal pin to be tested is located;

[0040] The determination module is used to determine the mapping correctness of the in-place signal pin to be tested and the corresponding in-place register in the port management chip, and the connectivity between the in-place signal pin to be tested and the corresponding port in the port management chip according to the in-place register value.

[0041] The present invention also provides a switch, comprising the switch port verification device as described in any one of the above items.

[0042] Compared with the prior art, the present invention has the following beneficial effects:

[0043] The present invention provides a switch port verification method, device and switch, which establish a one-to-one corresponding electrical connection relationship between a port test fixture and each signal pin to be tested in the port to be tested, and obtain the state change of the circuit where the signal pin to be tested is located when the electrical connection relationship is successfully established, so as to determine the functional correctness and line connectivity between the port to be tested and the port management chip, thereby realizing the port verification of the switch. Since the manual operation with complicated steps and difficult operation is omitted, the efficiency of the switch port verification can be effectively improved and the verification difficulty can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0045] Figure 1 It is a block diagram of low-speed signal management of a switch port in the prior art;

[0046] Figure 2 A circuit diagram of a port test fixture used in a switch port verification method provided by the present invention;

[0047] Figure 3 A flow chart of a switch port verification method provided by the present invention;

[0048] Figure 4 A flow chart of step S1 in a switch port verification method provided by the present invention;

[0049] Figure 5 A flow chart of step S2 in a switch port verification method provided by the present invention;

[0050] Figure 6 Another flow chart of step S1 in a switch port verification method provided by the present invention;

[0051] Figure 7 An automated verification flow chart of a switch port verification method provided by the present invention;

[0052] Figure 8 An automated verification sequence diagram of a switch port verification method provided by the present invention;

[0053] Fig. 9 This is a structural block diagram of a switch port verification device provided by the present invention.

[0054] In the above figure: 10, port test fixture; 20, acquisition module; 30, determination module; 40, port to be tested; 50, display module. DETAILED DESCRIPTION

[0055] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] It should be understood that in the description of the present invention, the specific embodiments are only used to explain the present invention, rather than to limit the present invention. Among them, the exemplary embodiments are described as processes or methods depicted as flowcharts; although the flowchart describes the processing of various operations or steps in a certain order, many of the operations or steps can be implemented in parallel, concurrently or simultaneously, and the order of the operations can be rearranged. When its operation or step is completed, the corresponding processing can be terminated, and there can also be additional steps not included in the drawings. The aforementioned processing can correspond to methods, functions, procedures, subroutines, subprograms, etc., and the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0057] The term "including" and its variations used in the present invention are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The technical solution of the present invention is further described below in conjunction with the accompanying drawings and through specific implementation methods; it can be understood that for the sake of ease of description, the accompanying drawings only show parts related to the present invention rather than all structures.

[0058] See also Figure 1 , which is a common switch port low-speed signal management block diagram in the prior art. The master control controls / obtains the port low-speed signal status by accessing the register inside the port management chip to achieve the purpose of port management.

[0059] In order to ensure the correctness of the port management chip (CPLD / FPGA) function and the connectivity of the lines on the board, all low-speed signals of each port need to be verified. The parts that need to be verified mainly include: 1. The correctness of the mapping between registers and pins in the port management chip; 2. The signal connectivity between the port management chip pins and the port socket; There are two types of signals that need to be verified, including port status signals and port control signals. The port status signal is used to map the port status signal pin input to the status register, and the port control signal is used to control the register to control the port control signal status.

[0060] Since each type of port includes multiple low-speed port signals that need to be verified, if the existing test method is used to verify the multiple signals of each port in turn, the verification efficiency will be low; at the same time, on the one hand, in order to ensure the correct mapping of signals and registers, the register end and the signal end need to be operated synchronously, which is difficult for a single person to operate; on the other hand, in order to ensure that the entire hardware path is verified, the test / control point should be located inside the port, which makes it difficult to lead out the signal. Therefore, the existing manual operation method is difficult to operate.

[0061] In order to solve the above-mentioned problems, the present invention provides a switch port authentication solution, which is described in detail below in conjunction with the accompanying drawings.

[0062] Some of the terminology explained below:

[0063] FPGA: Field Programmable Gate Array;

[0064] CPLD: Complex Programmable Logic Device;

[0065] QSFP: Quad SFP interface.

[0066] Please refer to Figure 2 , an embodiment of the present invention provides a switch port verification method, which is implemented based on a switch port verification device.

[0067] The switch port verification device includes a port test fixture, and the port test fixture includes test contacts for establishing a one-to-one corresponding electrical connection relationship with each signal pin to be tested in the port to be tested.

[0068] In this embodiment, the switch port verification device is improved on the basis of loopback. For example, for a QSFP port, the device is improved on the basis of QSFP loopback.

[0069] Specifically, the port test fixture includes a control signal test contact for establishing an electrical connection with a control signal pin to be tested. A signal light is provided on the circuit where the control signal test contact is located. In this embodiment, the signal light is an LED light.

[0070] Taking the QSFP port as an example, there are two control signal test contacts, and the circuits where the two control signal test contacts are located are respectively connected to the signal lights LED_R and LED_G, and the ends of the signal lights LED_R and LED_G away from the control signal test contacts are respectively connected to the power supply VCC through resistors R1 and R2. Among them, the two control signal test contacts are respectively used to establish an electrical connection relationship with the control signal pins to be tested corresponding to the control signal RST and the control signal LPMOD.

[0071] Furthermore, the port test fixture also includes a status signal test contact for establishing an electrical connection with a status signal pin to be tested; taking the QSFP port as an example, one end of the status signal test contact is used to establish an electrical connection with a status signal pin to be tested corresponding to the status signal INT, and the other end of the status signal test contact is connected to the circuit where the control signal test contact is located.

[0072] Furthermore, the test fixture also includes an in-place signal test contact for establishing an electrical connection with the in-place signal pin to be tested; taking the QSFP port as an example, one end of the in-place signal test contact is used to establish an electrical connection with the in-place signal pin to be tested corresponding to the in-place signal ABS, and the other end is grounded.

[0073] Please refer to Figures 3 to 5 In this embodiment, the switch port verification method includes the following steps:

[0074] S1. When the test contact establishes an electrical connection relationship with the signal pin to be tested, the corresponding register of the port to be tested is controlled to perform a predetermined operation, and the state change of the circuit where the signal pin to be tested is located is obtained.

[0075] It is understandable that this embodiment is implemented based on a pre-set automated test script. Before the test contact establishes an electrical connection with the signal pin to be tested, the automated test script needs to be run once and the initial values ​​of the registers corresponding to all ports need to be confirmed to ensure the accuracy of the test results.

[0076] Specifically, step S1 includes the following steps to achieve the state change of the circuit where the control signal pin to be tested, the state signal pin to be tested and the in-position signal pin to be tested are located.

[0077] S11, based on the change of the signal light, obtaining the state change of the circuit where the control signal pin to be tested is located;

[0078] S12, reading the status register value of the port management chip to obtain the status change of the circuit where the status signal pin to be tested is located;

[0079] S13, reading the in-place register value of the port management chip to obtain the state change of the circuit where the in-place signal pin to be tested is located.

[0080] S2. Based on the state change of the circuit where the signal pin to be tested is located, determine the functional correctness and line connectivity between the port to be tested and the port management chip.

[0081] Specifically, step S2 includes the following steps to implement verification of the control signal pin to be tested, the state signal pin to be tested, and the in-position signal pin to be tested:

[0082] S21, according to the state change of the circuit where the control signal pin to be tested is located, determine the mapping correctness of the control signal pin to be tested and the corresponding control register in the port management chip, and the connectivity between the control signal pin to be tested and the corresponding port in the port management chip;

[0083] S22, according to the status register value, determine the mapping correctness between the status signal pin to be tested and the corresponding status register in the port management chip, and the connectivity between the status signal pin to be tested and the corresponding port in the port management chip;

[0084] S23. Determine the mapping correctness between the in-place signal pin to be tested and the corresponding in-place register in the port management chip, and the connectivity between the in-place signal pin to be tested and the corresponding port in the port management chip according to the in-place register value.

[0085] It can be understood that the sequence of steps S11 to S13 and steps S21 to S23 is not limited by the sequence described above, and in practical applications, the sequence of executing these steps can be adjusted accordingly.

[0086] In this embodiment, after obtaining the state change of the circuit where the signal pin to be tested is located, the method further includes:

[0087] S14, displaying the state change of the circuit where the signal pin to be tested is located.

[0088] It is understandable that the state change of the circuit can be displayed by printing it out in the form of a graph, or the state change of the circuit can be displayed in the form of a graph using a display screen.

[0089] Please refer to Figure 7 Based on the above steps, the switch port verification method provided by this embodiment is further introduced below by taking the QSFP port as an example:

[0090] When the port test fixture is connected to the port to be tested, the in-place signal on the in-place signal pin to be tested is pulled low, and the position of the port to be tested is determined by monitoring the in-place register (ABS register). The mapping correctness of the in-place register and the in-place signal pin to be tested, as well as the connectivity between the in-place signal pin to be tested and the corresponding port in the port management chip are determined by comparing with the actual position.

[0091] After determining the position of the port to be tested, the control register corresponding to the port to be tested can be operated through a pre-set automated test script, and the corresponding operation can be performed through the control register to change the state of the control signal. Based on the change of the signal light, the state change of the circuit where the control signal pin to be tested is located is obtained, thereby determining the correctness of the mapping between the control signal pin to be tested and the corresponding control register in the port management chip, as well as the connectivity between the control signal pin to be tested and the corresponding port in the port management chip.

[0092] Furthermore, since the state change of the control signal will cause the change of the status register corresponding to the port to be tested, the state change of the circuit where the status signal pin to be tested is located is obtained by reading the status register value of the port management chip in a polling manner; then, based on the status register value, the correctness of the mapping between the status signal pin to be tested and the corresponding status register in the port management chip, as well as the connectivity between the status signal pin to be tested and the corresponding port in the port management chip are determined.

[0093] Please refer to Figure 8 As can be seen from the automated verification sequence in the figure, the verification time of a single port in the present invention is reduced to about 10 seconds, while the traditional method takes about 2 minutes to verify a single port. Therefore, the verification efficiency of the verification scheme provided by the present invention can be improved by about 10 times, which effectively improves the verification efficiency.

[0094] Please refer to Fig. 9 , and please refer to it again Figure 2 Based on the above embodiments, the present invention further provides a switch port verification device, which is applied to a port management chip, comprising:

[0095] A port test fixture 10, the port test fixture 10 is used to connect to the port to be tested 40, including test contacts that establish a one-to-one corresponding electrical connection relationship with each signal pin to be tested in the port to be tested 40;

[0096] The acquisition module 20 is used to control the corresponding register of the port 40 to perform a predetermined operation and acquire the state change of the circuit where the signal pin to be tested is located when the test contact establishes an electrical connection relationship with the signal pin to be tested;

[0097] The determination module 30 is used to determine the functional correctness and line connectivity between the port 40 to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located.

[0098] The switch port verification device includes a port test fixture 10 , and the port test fixture 10 includes test contacts for establishing a one-to-one corresponding electrical connection relationship with each signal pin to be tested in the port 40 to be tested.

[0099] In this embodiment, the switch port verification device is improved on the basis of loopback. For example, for a QSFP port, the device is improved on the basis of QSFP loopback.

[0100] Specifically, the port test fixture 10 includes a control signal test contact for establishing an electrical connection with a control signal pin to be tested. A signal light is provided on the circuit where the control signal test contact is located. In this embodiment, the signal light is an LED light.

[0101] Taking the QSFP port as an example, there are two control signal test contacts, and the circuits where the two control signal test contacts are located are respectively connected to the signal lights LED_R and LED_G, and the ends of the signal lights LED_R and LED_G away from the control signal test contacts are respectively connected to the power supply VCC through resistors R1 and R2. Among them, the two control signal test contacts are respectively used to establish an electrical connection relationship with the control signal pins to be tested corresponding to the control signal RST and the control signal LPMOD.

[0102] The port test fixture 10 also includes a status signal test contact for establishing an electrical connection with the status signal pin to be tested; one end of the status signal test contact is used to establish an electrical connection with the status signal pin to be tested corresponding to the status signal INT, and the other end of the status signal test contact is connected to the circuit where the control signal test contact is located.

[0103] The test fixture also includes an in-place signal test contact for establishing an electrical connection with the in-place signal pin to be tested; one end of the in-place signal test contact is used to establish an electrical connection with the in-place signal pin to be tested corresponding to the in-place signal ABS, and the other end is grounded.

[0104] The acquisition module 20 is used to execute the following steps to realize the state change of the circuit where the control signal pin to be tested, the status signal pin to be tested and the in-position signal pin to be tested are located: based on the change of the signal light, the state change of the circuit where the control signal pin to be tested is located is obtained; the status register value of the port management chip is read to obtain the state change of the circuit where the status signal pin to be tested is located; the in-position register value of the port management chip is read to obtain the state change of the circuit where the in-position signal pin to be tested is located.

[0105] The determination module 30 is used to execute the following steps to realize the verification of the control signal pin to be tested, the status signal pin to be tested and the in-position signal pin to be tested: determine the mapping correctness of the control signal pin to be tested and the corresponding control register in the port management chip, and the connectivity between the control signal pin to be tested and the corresponding port in the port management chip according to the state change of the circuit where the control signal pin to be tested is located; determine the mapping correctness of the status signal pin to be tested and the corresponding status register in the port management chip, and the connectivity between the status signal pin to be tested and the corresponding port in the port management chip according to the status register value; determine the mapping correctness of the in-position signal pin to be tested and the corresponding in-position register in the port management chip, and the connectivity between the in-position signal pin to be tested and the corresponding port in the port management chip according to the in-position register value.

[0106] The switch port verification device provided by this embodiment is further introduced below by taking a QSFP port as an example:

[0107] When the port test fixture 10 is connected to the port 40 to be tested, the in-position signal on the in-position signal pin to be tested is pulled low, and the in-position register (ABS register) is monitored by the acquisition module 20. The determination module 30 determines the position of the port 40 to be tested, and determines the correctness of the mapping between the in-position register and the in-position signal pin to be tested, as well as the connectivity between the in-position signal pin to be tested and the corresponding port in the port management chip by comparing with the actual position.

[0108] After determining the position of the port 40 to be tested, the acquisition module 20 can operate the control register corresponding to the port 40 to be tested through a pre-set automated test script, perform corresponding operations through the control register to change the state of the control signal, and obtain the state change of the circuit where the control signal pin to be tested is located based on the change of the signal light. The determination module 30 determines the correctness of the mapping between the control signal pin to be tested and the corresponding control register in the port management chip, as well as the connectivity between the control signal pin to be tested and the corresponding port in the port management chip.

[0109] Furthermore, since the state change of the control signal will cause the change of the state register corresponding to the port 40 to be tested, the acquisition module 20 obtains the state change of the circuit where the state signal pin to be tested is located by reading the state register value of the port management chip in a polling manner; then, the determination module 30 determines the correctness of the mapping between the state signal pin to be tested and the corresponding state register in the port management chip, as well as the connectivity between the state signal pin to be tested and the corresponding port in the port management chip based on the state register value.

[0110] In this embodiment, the switch port verification device further includes a display module 50, and the display module 50 is used to display the state change of the circuit where the signal pin to be tested is located after obtaining the state change of the circuit where the signal pin to be tested is located.

[0111] Specifically, the display module 50 may be a printer that displays the state changes of the circuit in the form of graphs by printing them out; or it may be a display screen that displays the state changes of the circuit in the form of graphs by using the display screen.

[0112] Based on the above embodiments, an embodiment of the present invention provides a switch, including the switch port verification device described in the above embodiments, which can execute the above switch port verification method.

[0113] Based on the above embodiments, the present invention has the following advantages:

[0114] 1. The port test fixture 10 modified by loop back is simple in circuit structure and easy to implement;

[0115] 2. It can better include all low-speed signal verification without artificial omissions;

[0116] 3. No need to manually type commands, eliminating the steps of verifying multiple signals of each port in sequence, greatly reducing the difficulty of test verification;

[0117] 4. Please refer again Figure 8 The traditional method takes about 2 minutes to verify a single port, while the solution provided by the present invention only takes about 10 seconds, improving the verification efficiency by more than 10 times.

[0118] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A switch port verification method, characterized in that: It is implemented based on a switch port verification device, the switch port verification device includes a port test fixture, and the port test fixture includes a test contact for establishing a one-to-one corresponding electrical connection relationship with each signal pin to be tested in the port to be tested; The switch port verification method comprises: When the test contact establishes an electrical connection relationship with the signal pin to be tested, controlling the corresponding register of the port to be tested to perform a predetermined operation, and obtaining a state change of the circuit where the signal pin to be tested is located; Based on the state change of the circuit where the signal pin to be tested is located, determining the functional correctness and line connectivity between the port to be tested and the port management chip; The port test fixture comprises a control signal test contact for establishing an electrical connection with a control signal pin to be tested, and a signal lamp is provided on the circuit where the control signal test contact is located; The obtaining of the state change of the circuit where the signal pin to be tested is located includes: Based on the change of the signal light, obtaining the state change of the circuit where the control signal pin to be tested is located; The determining of the functional correctness and line connectivity between the port to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located includes: According to the state change of the circuit where the control signal pin to be tested is located, the mapping correctness of the control signal pin to be tested and the corresponding control register in the port management chip and the connectivity between the control signal pin to be tested and the corresponding port in the port management chip are determined.

2. The switch port verification method according to claim 1, characterized in that: The port test fixture further comprises a status signal test contact for establishing an electrical connection relationship with a status signal pin to be tested, wherein the status signal test contact is connected to the circuit where the control signal test contact is located; The step of obtaining the state change of the circuit where the signal pin to be tested is located also includes: Reading the status register value of the port management chip to obtain the status change of the circuit where the status signal pin to be tested is located; The determining of the functional correctness and line connectivity between the port to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located also includes: According to the status register value, the mapping correctness between the status signal pin to be tested and the corresponding status register in the port management chip and the connectivity between the status signal pin to be tested and the corresponding port in the port management chip are determined.

3. The switch port verification method according to claim 1, characterized in that: The test fixture further comprises an in-place signal test contact for establishing an electrical connection relationship with the in-place signal pin to be tested, and the circuit where the in-place signal test contact is located is grounded; The step of obtaining the state change of the circuit where the signal pin to be tested is located also includes: Reading the in-place register value of the port management chip to obtain the state change of the circuit where the in-place signal pin to be tested is located; The determining of the functional correctness and line connectivity between the port to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located also includes: According to the in-place register value, the mapping correctness between the in-place signal pin to be tested and the corresponding in-place register in the port management chip and the connectivity between the in-place signal pin to be tested and the corresponding port in the port management chip are determined.

4. The switch port verification method according to claim 1, characterized in that: After obtaining the state change of the circuit where the signal pin to be tested is located, the method further includes: Display the state change of the circuit where the signal pin to be tested is located.

5. A switch port verification device, characterized in that: Applied to port management chips, including: A port test fixture, used to connect to the port to be tested, including test contacts that establish a one-to-one corresponding electrical connection relationship with each signal pin to be tested in the port to be tested; an acquisition module, used to control the corresponding register of the port to be tested to perform a predetermined operation and acquire a state change of the circuit where the signal pin to be tested is located when the test contact establishes an electrical connection relationship with the signal pin to be tested; A determination module, used to determine the functional correctness and line connectivity between the port to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located; The port test fixture comprises a control signal test contact for establishing an electrical connection with a control signal pin to be tested, and a signal lamp is provided on the circuit where the control signal test contact is located; The acquisition module is used to acquire the state change of the circuit where the control signal pin to be tested is located based on the change of the signal light; The determination module is used to determine the mapping correctness of the control signal pin to be tested and the corresponding control register in the port management chip, as well as the connectivity between the control signal pin to be tested and the corresponding port in the port management chip according to the state change of the circuit where the control signal pin to be tested is located.

6. The switch port verification device according to claim 5, characterized in that: The port test fixture further comprises a status signal test contact for establishing an electrical connection relationship with a status signal pin to be tested, wherein the status signal test contact is connected to the circuit where the control signal test contact is located; The acquisition module is used to read the status register value of the port management chip to obtain the status change of the circuit where the status signal pin to be tested is located; The determination module is used to determine the mapping correctness of the state signal pin to be tested and the corresponding state register in the port management chip, and the connectivity between the state signal pin to be tested and the corresponding port in the port management chip according to the state register value.

7. The switch port verification device according to claim 6, characterized in that: The test fixture further comprises an in-place signal test contact for establishing an electrical connection relationship with the in-place signal pin to be tested, and the circuit where the in-place signal test contact is located is grounded; The acquisition module is used to read the in-place register value of the port management chip to obtain the state change of the circuit where the in-place signal pin to be tested is located; The determination module is used to determine the mapping correctness of the in-place signal pin to be tested and the corresponding in-place register in the port management chip, and the connectivity between the in-place signal pin to be tested and the corresponding port in the port management chip according to the in-place register value.

8. A switch, characterized in that: It comprises the switch port verification device as described in any one of claims 5 to 7.

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