Test control method and device, computer device and computer readable storage medium

Abstract

The application relates to a test control method and device, computer equipment and a computer readable storage medium. The method comprises the following steps: receiving a first test timing sent by a host; acquiring a station state flag, which comprises a sending flag or a pause flag; if the station state flag comprises the sending flag, sending the first test timing to a test board card, so that the test board card sends an excitation signal to a device under test according to the received first test timing, and tests the device under test; and if the station state flag comprises the pause flag, pausing the sending of the first test timing to the test board card until the station state flag changes from the pause flag to the sending flag. The method can improve data processing efficiency.

Description

Technical Field

[0001] This application relates to the field of testing technology, and in particular to a test control method, apparatus, computer equipment, and computer-readable storage medium. Background Technology

[0002] Automatic Test Equipment (ATE) is an automated testing machine for integrated circuits (ICs) in the semiconductor industry. It is used to test the integrity of the functions of integrated circuits and is the final process in integrated circuit manufacturing to ensure the quality of integrated circuit production.

[0003] An ATE (Automatic Test Equipment) consists of a host, a tester, and a Device Under Test (DUT). The tester includes a main control module and at least one test instrument. The host sends a test sequence to the main control module, which forwards it to the test instrument. The test instrument generates a stimulus signal based on the received test sequence and sends it to the DUT to test its functionality. Upon receiving the stimulus signal, the DUT sends a response signal back to the test instrument. The test instrument parses the response signal to obtain the data result and sends it to the main control module, which forwards the data result to the host. The host processes the feedback data result (e.g., comparing it with preset values) to generate a final processing result. Based on the processing result, the host instructs a robotic arm to classify the DUT, thus completing the testing of the DUT.

[0004] However, as the number of devices under test increases, traditional ATE systems need to process each test requirement in sequence, resulting in slow data processing efficiency. Summary of the Invention

[0005] Therefore, it is necessary to provide a test control method, apparatus, computer equipment, and computer-readable storage medium that can improve data processing efficiency in response to the above-mentioned technical problems.

[0006] Firstly, this application provides a test control method. The method includes:

[0007] Receive the first test timing sequence sent by the host;

[0008] Obtain the workstation status flag, which includes a send flag or a pause flag;

[0009] if the station status flag comprises the send flag, sending the first test timing to a test board card to make the test board card send an excitation signal to a device under test according to the received first test timing to test the device under test;

[0010] if the station status flag comprises the pause flag, pausing sending the first test timing to the test board card until the station status flag changes from the pause flag to the send flag.

[0011] In one of the embodiments, the method further comprises:

[0012] after receiving the first test timing sent by the host, sending a timing request to the host to make the host send a second test timing after the first test timing.

[0013] In one of the embodiments, the method further comprises:

[0014] receiving and buffering the second test timing sent by the host;

[0015] after sending the first test timing to the test board card, obtaining the station status flag;

[0016] if the station status flag comprises the send flag, sending the second test timing to the test board card to make the test board card send an excitation signal to the device under test according to the received second test timing to test the device under test;

[0017] if the station status flag comprises the pause flag, pausing sending the second test timing to the test board card until the station status flag changes from the pause flag to the send flag.

[0018] In one of the embodiments, the method further comprises:

[0019] after sending the first test timing to the test board card, sending a status update instruction to a status control module according to the first test timing to make the status control module update the station status flag.

[0020] In one of the embodiments, if the first test timing comprises a wait identifier, the station status flag comprises the pause flag; if the first test timing comprises a no-wait identifier or no identifier, the station status flag comprises the send flag.

[0021] In one of the embodiments, if the first test timing sequence comprises a waiting identifier and a processing identifier, the station state flag further comprises a judgment identifier; if the first test timing sequence comprises a waiting identifier and a non-processing identifier or only comprises a waiting identifier, the station state flag further comprises a non-judgment identifier or only comprises a pause identifier.

[0022] In one of the embodiments, the method further comprises:

[0023] receiving test data containing abnormal information sent by the test board card or test results containing abnormal information obtained by processing the test data by the coprocessor;

[0024] stopping sending the test timing sequence to the test board card according to the abnormal information.

[0025] In a second aspect, the application further provides a test control method. The method comprises:

[0026] receiving a state request, the state request being sent by a master module after receiving a test timing sequence sent by a host;

[0027] sending a station state flag to the master module according to the state request, the station state flag comprising a sending identifier or a pause identifier;

[0028] If the station state flag comprises the sending identifier, the master module sends the test timing sequence to a test board card, so that the test board card sends an excitation signal to a device under test according to the received test timing sequence to test the device under test; if the station state flag comprises the pause identifier, the master module pauses sending the test timing sequence to the test board card until the station state flag changes from the pause identifier to the sending identifier.

[0029] In one of the embodiments, the method further comprises:

[0030] receiving a state update instruction, the state update instruction being sent by the master module according to the test timing sequence after sending the test timing sequence to the test board card;

[0031] setting the station state flag according to the state update instruction.

[0032] In one of the embodiments, if the test timing sequence comprises a waiting identifier, the station state flag comprises the pause identifier; if the test timing sequence comprises a non-waiting identifier or no identifier, the station state flag comprises the sending identifier.

[0033] In one embodiment, if the test sequence includes a waiting flag and a processing flag, the workstation status flag further includes a judgment flag; if the test sequence includes a waiting flag and a no-processing flag or only a waiting flag, the workstation status flag further includes a no-judgment flag or only a pause flag.

[0034] In one embodiment, the method further includes:

[0035] If the workstation status flag includes a pause flag and a no-determination flag, or only includes a pause flag, then after determining that the main control module has received the test data sent by the test board, the workstation status flag is set to the sending flag;

[0036] If the workstation status flag includes a pause flag and a judgment flag, then after determining that the coprocessor has processed the test data to obtain the test result, the workstation status flag is set as the send flag.

[0037] Thirdly, this application also provides a test control device. The device includes:

[0038] The first receiving module is used to receive the first test timing sequence sent by the host;

[0039] The acquisition module is used to acquire workstation status flags, which include a send flag or a pause flag.

[0040] The first sending module is configured to send the first test timing sequence to the test board when the workstation status flag includes the sending flag, so that the test board sends an excitation signal to the device under test according to the received first test timing sequence to test the device under test; and to pause sending the first test timing sequence to the test board when the workstation status flag includes the pause flag, until the workstation status flag changes from the pause flag to the sending flag.

[0041] Fourthly, this application also provides a test control device. The device includes:

[0042] The second receiving module is used to receive status requests, which are sent by the main control module after receiving the test timing data sent by the host.

[0043] The second sending module is used to send a workstation status flag to the main control module according to the status request. The workstation status flag includes a sending flag or a pause flag.

[0044] If the station state flag comprises the sending flag, the host control module sends the test timing to the test board card, so that the test board card sends an excitation signal to a device under test according to the received test timing, and tests the device under test; if the station state flag comprises the pause flag, the host control module pauses to send the test timing to the test board card until the station state flag changes from the pause flag to the sending flag.

[0045] In a fifth aspect, the present application provides a computer device. The computer device comprises a memory and a processor, the memory stores a computer program, and the processor implements the following steps when executing the computer program:

[0046] receiving the first test timing sent by the host;

[0047] obtaining a station state flag, the station state flag comprising a sending flag or a pause flag;

[0048] If the station state flag comprises the sending flag, the first test timing is sent to the test board card, so that the test board card sends an excitation signal to a device under test according to the received first test timing, and tests the device under test;

[0049] If the station state flag comprises the pause flag, the host control module pauses to send the first test timing to the test board card until the station state flag changes from the pause flag to the sending flag.

[0050] In a sixth aspect, the present application provides a computer device. The computer device comprises a memory and a processor, the memory stores a computer program, and the processor implements the following steps when executing the computer program:

[0051] receiving a state request, the state request being sent by the host control module after receiving the test timing sent by the host;

[0052] According to the state request, a station state flag is sent to the host control module, the station state flag comprising a sending flag or a pause flag;

[0053] If the station state flag comprises the sending flag, the host control module sends the test timing to the test board card, so that the test board card sends an excitation signal to a device under test according to the received test timing, and tests the device under test; if the station state flag comprises the pause flag, the host control module pauses to send the test timing to the test board card until the station state flag changes from the pause flag to the sending flag.

[0054] In a seventh aspect, the present application provides a computer readable storage medium. The computer readable storage medium has a computer program stored thereon, and the computer program, when executed by a processor, implements the following steps:

[0055] receiving the first test timing sent by the host;

[0056] obtaining a station state flag, the station state flag comprising a sending flag or a pause flag;

[0057] if the station state flag comprises the sending flag, sending the first test timing to a test board card, so that the test board card sends an excitation signal to a device under test according to the received first test timing, and tests the device under test;

[0058] if the station state flag comprises the pause flag, pausing sending the first test timing to the test board card until the station state flag changes from the pause flag to the sending flag.

[0059] In an eighth aspect, the present application provides a computer readable storage medium. The computer readable storage medium has a computer program stored thereon, and the computer program, when executed by a processor, implements the following steps:

[0060] receiving a state request, the state request being sent by a master module after receiving a test timing sent by a host;

[0061] sending a station state flag to the master module according to the state request, the station state flag comprising a sending flag or a pause flag;

[0062] If the station state flag comprises the sending flag, the master module sends the test timing to a test board card, so that the test board card sends an excitation signal to a device under test according to the received test timing, and tests the device under test. If the station state flag comprises the pause flag, the master module pauses sending the test timing to the test board card until the station state flag changes from the pause flag to the sending flag.

[0063] The test control method, device, computer equipment and computer readable storage medium described above, after receiving the test timing sent by the host, first acquire the station state flag, the station state flag includes a sending flag or a pause flag, if the station state flag includes the sending flag, the test timing is sent to the test board card, so that the test board card sends the excitation signal to the device under test according to the received test timing, to test the device under test, so that for the test without association, the next test is directly performed without waiting for the previous test to be completed, the time consumed by waiting can be saved, and the data processing efficiency is improved. If the station state flag includes the pause flag, the test timing is paused from being sent to the test board card until the station state flag changes from the pause flag to the sending flag, so that for the associated test, the next test is performed after the previous test is completed, and the accuracy of the test result is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0064] Figure 1 An application environment diagram of the test control method in one embodiment is shown in the figure;

[0065] Figure 2 A flowchart of the test control method in one embodiment is shown in the figure;

[0066] Figure 3 A flowchart of the test control method in one embodiment is shown in the figure;

[0067] Figure 4 A flowchart of the test control method in one embodiment is shown in the figure;

[0068] Figure 5 A flowchart of the test control method in one embodiment is shown in the figure;

[0069] Figure 6 A flowchart of the test control method in one embodiment is shown in the figure;

[0070] Figure 7 A schematic diagram of the plurality of test timings carrying the identification in one embodiment is shown in the figure;

[0071] Figure 8 An interaction diagram of the process of the adjacent two test timings in the prior art when waiting is needed is shown in the figure;

[0072] Figure 9 An interaction diagram of the process of the adjacent two test timings when waiting is needed is shown in the figure;

[0073] Figure 10 An interaction diagram of the process of the adjacent two test timings when waiting is not needed in the prior art is shown in the figure;

[0074] Figure 11 An interaction diagram of the process of the adjacent two test timings when waiting is not needed in one embodiment is shown in the figure;

[0075] Figure 12 a structural block diagram of a test control device in one embodiment;

[0076] Figure 13 a structural block diagram of a test control device in one embodiment;

[0077] Figure 14 an internal structural diagram of a computer device in one embodiment. DETAILED DESCRIPTION

[0078] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not used to limit the present application.

[0079] The test control method provided by the embodiments of the present application can be applied to an application environment as shown in Figure 1 The test machine includes a main control module 102 and at least one test board card 104, the main control module 102 is electrically connected with each test board card 104 respectively. A host computer 106 is electrically connected with the main control module 102, and a device under test 108 is electrically connected with each test board card 104. The test machine further includes a state control module 110, the state control module 110 is electrically connected with the main control module 102 and each test board card 104, and a data storage system can store a station state flag corresponding to the device under test 108. The data storage system can be integrated on the main control module 102 or placed on the state control module 110.

[0080] The host computer 106 sends a test timing sequence to the main control module 102. The main control module 102 acquires the station state flag, and the station control flag includes a sending flag or a pause flag. When the station state flag includes the sending flag, the main control module 102 sends the test timing sequence to the test board card 104, and the test board card 104 sends an excitation signal to the device under test 108 according to the received test timing sequence to test the device under test 108. When the station state flag includes the pause flag, the main control module 102 pauses to send the test timing sequence to the test board card 104 until the station state flag changes from the pause flag to the sending flag.

[0081] The master module 102 and the state control module 110 can be, but are not limited to, various general-purpose central processing units (CPUs), microprocessors, application-specific integrated circuits (ASICs), single-chip microcomputers, digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, integrated circuits for controlling program execution, and the like.

[0082] In one embodiment, as shown in Figure 2 , a test control method is provided, which is applied to the master module in Figure 1 for example, and includes the following steps.

[0083] In step 202, a first test timing sent by a host is received.

[0084] The test timing is a test instruction at a certain moment in a test program. For example, the test program includes N test instructions at N moments, N is a positive integer, and the first test timing can be any one of the test instruction at the first moment, the test instruction at the second moment, …, and the test instruction at the Nth moment.

[0085] For example, the host sends the first test timing to the master module in the tester through a network.

[0086] In step 204, a station state flag is obtained, and the station state flag includes a sending flag or a pause flag. If the station state flag includes the sending flag, step 206 is performed; if the station state flag includes the pause flag, step 208 is performed.

[0087] The station state flag corresponds to a station where a device under test is located. Each station can be provided with a device under test, and each station state flag represents the test state of the device under test in the corresponding station. For example, a test board card is electrically connected to M stations, M is a positive integer, and M station state flags are provided accordingly. The first station state flag represents the test state of the device under test in the first station, the second station state flag represents the test state of the device under test in the second station, …, and the Mth station state flag represents the test state of the device under test in the Mth station.

[0088] Exemplarily, the station state flag can be arranged on the master module, and in this case, the master module can directly acquire the station state flag. The station state flag can also be arranged on the state control module, and in this case, the master module sends a state request to the state control module, and the state control module sends the station state flag to the master module according to the state request.

[0089] Optionally, the acquired station state flag can only include the station state flag corresponding to the station where the device under test measured in the first test timing measurement is located. Therefore, the number of acquired station state flags is consistent with the number of devices under test measured in the first test timing measurement. If the device under test measured in the first test timing measurement is one, only one station state flag is acquired; if the device under test measured in the first test timing measurement is multiple, multiple station state flags are acquired at the same time.

[0090] In step 206, the first test timing is sent to the test board card, so that the test board card sends an excitation signal to the device under test according to the received first test timing to test the device under test.

[0091] The excitation signal is a signal generated by the test board card based on the test timing.

[0092] Exemplarily, the master module sends the test timing to the test board card, the test board card sends the excitation signal to the device under test according to the test timing, the device under test feeds back a response signal to the test board card according to the excitation signal, and the test board card obtains test data according to the response signal.

[0093] In step 208, the sending of the first test timing to the test board card is suspended until the station state flag changes from the pause flag to the sending flag.

[0094] Exemplarily, if the station state flag includes the pause flag, the master module does not send the test timing to the test board card. Only when the station state flag includes the sending flag, the master module sends the test timing to the test board card.

[0095] The station state flag will change accordingly according to the actual situation. When the station state flag changes from the pause flag to the sending flag, the master module sends the first test timing to the test board card, that is, step 206 is executed.

[0096] The test control method described above, after receiving the test timing sent by the host, first acquires the station state flag, the station state flag including a sending flag or a pause flag, if the station state flag includes the sending flag, the test timing is sent to the test board card, so that the test board card sends the excitation signal to the device under test according to the received test timing, and the device under test is tested, so that for the test without association, the next test can be directly performed without waiting for the previous test to be completed, the time consumed by waiting can be saved, and the data processing efficiency is improved. If the station state flag includes the pause flag, the sending of the test timing to the test board card is paused until the station state flag changes from the pause flag to the sending flag, so that for the associated test, the next test is still performed after the previous test is completed, and the accuracy of the test result is avoided.

[0097] The test program usually includes a plurality of test timings, and the host sends the plurality of test timings to the host control module in sequence according to the order. The first test timing and the second test timing are two adjacent test timings in the plurality of test timings, and the second test timing is located after the first test timing, that is, the host sends the first test timing to the host control module first, and then sends the second test timing to the host control module. The above embodiment introduces the host sending the first test timing to the host control module, and the following introduces the host sending the second test timing to the host control module.

[0098] In one embodiment, as shown in Figure 3 The method further includes:

[0099] Step S300, after receiving the first test timing sent by the host, sending a timing request to the host to make the host send the second test timing located after the first test timing.

[0100] The timing request is a signal that the host control module requests the host to send the test timing.

[0101] For example, the host control module sends a timing request to the host according to the received first test timing. The host sends the second test timing located after the first test timing to the host control module according to the received timing request.

[0102] In the above embodiment, after receiving the first test timing sent by the host, the host control module actively asks the host for the second test timing located after the first test timing, so that the second test timing can be acquired and cached synchronously when the first test timing is used for testing, so as to save the time consumed by waiting for the second test timing to be transmitted from the host to the host control module, thereby saving the time consumed by waiting and improving the data processing efficiency.

[0103] For example, continuing to refer to Figure 3 The method further includes:

[0104] Step 302, receiving and buffering the second test timing sent by the host.

[0105] The second test timing is a test timing located after the first test timing.

[0106] For example, the host module sends the second test timing to the host module in the tester through the network, and the host module buffers the second test timing in the storage module in the tester. The storage module can be integrated in the host module or set independently from the host module.

[0107] Step 304, after sending the first test timing to the test board card, obtaining the station state flag. If the station state flag includes the sending flag, step 306 is executed; if the station state flag includes the pause flag, step 308 is executed.

[0108] Specifically, step 304 can be similar to step 204, which will not be described here. Understandably, the station state flag will change accordingly according to the actual situation. The station state flag when the host module sends the second test timing to the test board card can be different from the station state flag when the host module sends the first test timing to the test board card. Therefore, the station state flag is obtained again here.

[0109] Step 306, sending the second test timing to the test board card, so that the test board card sends the excitation signal to the device under test according to the received second test timing, and tests the device under test.

[0110] Specifically, step 306 can be similar to step 206, which will not be described here. Understandably, after the test board card receives the first test timing, it will send the excitation signal corresponding to the first test timing to the device under test. After the test board card receives the second test timing, it will send the excitation signal corresponding to the second test timing to the device under test.

[0111] Step 308, pausing sending the second test timing to the test board card until the station state flag changes from the pause flag to the sending flag.

[0112] Specifically, step 308 can be similar to step 208, which will not be described here. Understandably, after step 208, if the station state flag changes from the pause flag to the sending flag, the host module sends the first test timing to the test board card, i.e. step 206 is executed. After step 308, if the station state flag changes from the pause flag to the sending flag, the host module sends the second test timing to the test board card, i.e. step 306 is executed.

[0113] In the above embodiment, after receiving the second test timing sent by the host, the first test timing is buffered first, and then can be used directly, avoiding wasting time waiting for the second test timing to be transmitted from the host to the host module. After sending the first test timing to the test board card, the station state flag is obtained to determine whether the sending of the second test timing needs to wait for the test corresponding to the first test timing to be completed according to the station state flag. If the station state flag includes a sending flag, it indicates that the sending of the second test timing does not need to wait for the test corresponding to the first test timing to be completed, at which time the second test timing is sent to the test board card to make the test board card send an excitation signal to the device under test according to the received second test timing to test the device under test. In this way, the next test can be performed directly without waiting for the previous test to be completed, which can save the time consumed by waiting and improve the data processing efficiency. If the station state flag includes a pause flag, it indicates that the sending of the second test timing needs to wait for the test corresponding to the first test timing to be completed, at which time the sending of the test timing to the test board card is paused until the station state flag changes from the pause flag to the sending flag, which can avoid affecting the accuracy of the test results.

[0114] As mentioned above, the station state flag will change accordingly according to the actual situation. The station state flag can change in two cases: one is to update the station state flag according to whether the next test timing needs to wait for the test corresponding to the previous test timing to be completed between the sending of the adjacent two test timings; the other is to update the station state flag when the test corresponding to the previous test timing is completed if the next test timing needs to wait for the test corresponding to the previous test timing to be completed. The host module mainly involves the former case, which will be described in detail below.

[0115] In one embodiment, the method further includes: after sending the first test timing to the test board card, sending a state update instruction to the state control module according to the first test timing to make the state control module update the station state flag.

[0116] In the above embodiment, after sending the first test timing to the test board card, the state update instruction is sent to the state control module according to the first test timing, which can update the station state flag in time according to whether the next test timing needs to wait for the test corresponding to the previous test timing to be completed between the sending of the adjacent two test timings.

[0117] For example, if the first test timing includes a wait identifier, the station state flag includes a pause flag; if the first test timing includes a start identifier or does not include an identifier, the station state flag includes a sending flag.

[0118] In the above embodiment, if the first test sequence includes the waiting identifier, it indicates that the next test sequence (e.g., the second test sequence) needs to wait for the completion of the test corresponding to the previous test sequence (i.e., the first test sequence). In this case, the station state flag includes the pause identifier, and the main control module will pause sending the second test sequence after the first test sequence to the test board card until the test corresponding to the previous test sequence (i.e., the first test sequence) is completed. If the first test sequence includes the start identifier or does not include the identifier, it indicates that the next test sequence (e.g., the second test sequence) does not need to wait for the completion of the test corresponding to the previous test sequence (i.e., the first test sequence). In this case, the station state flag includes the sending identifier, and the main control module will send the second test sequence after the first test sequence to the test board card. In this way, the next test can be performed directly without waiting for the completion of the previous test (i.e., the first test sequence), which can save the time consumed by waiting and improve the data processing efficiency.

[0119] For example, if the first test sequence includes the waiting identifier and the processing identifier, the station state flag further includes the judgment identifier. If the first test sequence includes the waiting identifier and the non-processing identifier or only includes the waiting identifier, the station state flag further includes the non-judgment identifier or only includes the pause identifier.

[0120] Specifically, if the first test sequence includes the waiting identifier and the processing identifier, the station state flag includes the pause identifier and the judgment identifier. If the first test sequence includes the waiting identifier and the non-processing identifier, the station state flag can include the pause identifier and the non-judgment identifier, or only include the pause identifier. If the first test sequence only includes the waiting identifier, the station state flag can include the pause identifier and the non-judgment identifier, or only include the pause identifier.

[0121] In the above embodiment, in the case where the first test sequence includes the waiting identifier, if the first test sequence further includes the processing identifier, it indicates that the completion of the test corresponding to the first test sequence takes the test result obtained by processing the test data as the judgment standard. The station state flag changes from the pause identifier to the sending identifier after receiving the test result. If the first test sequence further includes the non-processing identifier or only includes the waiting identifier, it indicates that the completion of the test corresponding to the first test sequence takes the test data as the judgment standard. The station state flag changes from the pause identifier to the sending identifier after receiving the test data.

[0122] In one embodiment, as shown in Figure 4 , a test control method is provided. Taking the state control module in Figure 1 as an example, the method includes the following steps:

[0123] Step 402, receiving a state request, the state request being sent by the main control module after receiving the test sequence sent by the host.

[0124] Step 404, according to the state request, sending the station state flag to the master module, the station state flag including a sending flag or a pause flag.

[0125] Wherein, if the station state flag includes the sending state, the master module sends the test timing to the test board card, so that the test board card sends the excitation signal to the device under test according to the received test timing, and tests the device under test. If the station state flag includes the pause flag, the master module pauses to send the test timing to the test board card until the station state flag changes from the pause flag to the sending flag.

[0126] In the above test control method, after the master module receives the test timing sent by the host, the master module sends a state request to the state control module, and the state control module sends the station state flag to the master module according to the state request, the station state flag including a sending flag or a pause flag. If the station state flag includes the sending flag, the master module sends the test timing to the test board card, so that the test board card sends the excitation signal to the device under test according to the received test timing, and tests the device under test. In this way, for tests without association, the next test can be performed directly without waiting for the previous test to complete, which can save the time consumed by waiting and improve the data processing efficiency. If the station state flag includes the pause flag, the master module pauses to send the test timing to the test board card until the station state flag changes from the pause flag to the sending flag. In this way, for tests with association, the next test is still performed after the previous test is completed, which avoids affecting the accuracy of the test results. At the same time, the test board card can also execute other instructions during the period when the result data is not fed back, improving the efficiency of the test.

[0127] As mentioned above, the station state flag will change according to the actual situation. The station state flag can change in two cases: one is to update the station state flag according to whether the next test timing needs to wait for the completion of the test corresponding to the previous test timing between the sending of the two adjacent test timings; the other is to update the station state flag when the test corresponding to the previous test timing is completed, if the next test timing needs to wait for the completion of the test corresponding to the previous test timing. The following will be described in detail.

[0128] In one embodiment, as shown in FIG. 5, the method further includes: Figure 5

[0129] Step 500, sending a state request to the master module.

[0130] Wherein, the step 500 is an optional step.

[0131] ​Specifically, the state control module can send a state request to the master module to actively acquire the state of the master module, or can not send a state request to the master module and passively receive the state update instruction actively sent by the master module.

[0132] In step 502, the state update instruction is received, and the state update instruction is sent by the master module according to the test timing after the test timing is sent to the test board card.

[0133] In step 504, the station state flag is set according to the state update instruction.

[0134] In the above embodiment, the master module sends a state update instruction to the state control module according to the test timing after sending the test timing to the test board card, and the station state flag can be updated in time according to whether the next test timing needs to wait for the completion of the test corresponding to the previous test timing between the sending of the adjacent two test timings.

[0135] For example, if the test timing includes a wait identifier, the station state flag includes a pause flag; if the test timing includes a no-wait identifier or does not include an identifier, the station state flag includes a send flag.

[0136] In the above embodiment, if the first test timing includes a wait identifier, it indicates that the next test timing needs to wait for the completion of the test corresponding to the previous test timing, at this time the station state flag includes a pause flag, and the master module will pause sending the first test timing to the test board card until the test corresponding to the previous test timing is completed. If the first test timing includes a start identifier or does not include an identifier, it indicates that the next test timing does not need to wait for the completion of the test corresponding to the previous test timing, at this time the station state flag includes a send flag, and the master module will send the first test timing to the test board card, so that the next test can be performed directly without waiting for the previous test to be completed, which can save the time consumed by waiting and improve the data processing efficiency.

[0137] For example, if the test timing includes a wait identifier and a process identifier, the station state flag further includes a judgment flag; if the test timing includes a wait identifier and a no-process identifier or only includes a wait identifier, the station state flag further includes a no-judgment flag or only includes a pause flag.

[0138] Correspondingly, the method further includes: if the station state flag includes a pause flag and a no-judgment flag or only includes a pause flag, setting the station state flag to a send flag after determining that the master module receives the test data sent by the test board card; if the station state flag includes a pause flag and a judgment flag, setting the station state flag to a send flag after determining that the coprocessor processes the test data to obtain a test result.

[0139] In the above embodiments, if the first test timing further comprises a processing flag in the case that the first test timing comprises a waiting flag, it indicates that the first test timing corresponds to the completion of the test, and the test result obtained by processing the test data is taken as the judgment standard, and the station state flag changes from the pause flag to the sending flag after the test result is received; if the first test timing further comprises a non-processing flag or only comprises a waiting flag, it indicates that the first test timing corresponds to the completion of the test, and the test data is taken as the judgment standard, and the station state flag changes from the pause flag to the sending flag after the test data is received.

[0140] In combination with the above embodiments, the change of the station state flag can be summarized in the following table 1:

[0141] Table 1

[0142]

[0143] As can be seen, the test timing comprises a plurality of combinations of flags, and the station state flag is updated according to different situations.

[0144] In one embodiment, as shown in Figure 6 , a test control method is provided, comprising the following steps:

[0145] Step 601, the host sends a first test timing to the master module.

[0146] Step 602, after receiving the first test timing, the master module sends a state request to the state control module, and sends a timing request to the host.

[0147] Step 603, the state control module sends a station state flag to the master module according to the state request. If the station state flag comprises a sending flag, steps 604-606 are executed; if the station state flag comprises a pause flag, step 607 is executed.

[0148] Step 604, the master module sends the first test timing to the test board card, and sends a state update instruction to the state control module according to the first test timing.

[0149] Step 605, the state update module sets the station state flag according to the state update instruction.

[0150] Step 606, the test board card sends an excitation signal to the device under test according to the received first test timing, and tests the device under test.

[0151] Step 607, the master module pauses to send the first test timing to the test board card until the station state flag changes from the pause flag to the sending flag.

[0152] Step 608, the host sends the second test timing to the master module.

[0153] Step 609, the master module caches the second test timing after receiving the second test timing.

[0154] Step 610, the master module acquires the site state flag after sending the first test timing to the test board card. If the site state flag includes the sending flag, steps 611-612 are executed; if the site state flag includes the pause flag, step 613 is executed.

[0155] Step 611, the master module sends the second test timing to the test board card.

[0156] Step 612, the test board card sends the excitation signal to the device under test according to the received second test timing.

[0157] Step 613, the master module pauses sending the second test timing to the test board card until the site state flag changes from the pause flag to the sending flag.

[0158] Figure 7 An illustration of carrying the identification in the multiple test timings in one embodiment. The following takes the test timing as an example to specifically describe the identification in the test timing: Figure 7

[0159] The Nth test timing is first sent. Since the Nth test timing does not include the identification, the site state flag includes the sending flag, thus the N+1th test timing can be sent immediately after the Nth test timing is sent, without waiting.

[0160] Then after the N+1th test timing is sent, since the N+1th test timing only includes the waiting identification, the site state flag includes the pause flag, thus the N+2th test timing cannot be sent immediately after the N+1th test timing is sent. The N+2th test timing can be sent only after the master module receives the test data sent by the test board card, the site state flag changes to the sending flag.

[0161] Then after the N+2th test timing is sent, since the N+2th test timing does not include the identification, the site state flag includes the sending flag, thus the N+3th test timing can be sent immediately after the N+2th test timing is sent, without waiting.

[0162] ​Then after sending the N+3th test sequence, since the N+3th test sequence only includes the wait identifier, the station status identifier includes the pause identifier, therefore, the N+4th test sequence cannot be sent immediately after sending the N+3th test sequence. It is required to wait until the station status identifier becomes the sending identifier after the host module receives the test data sent by the test board card, and then the N+4th test sequence can be sent.

[0163] Then after sending the N+4th test sequence, since the N+4th test sequence includes the wait identifier and the processing identifier, the station status identifier includes the pause identifier, therefore, the N+5th test sequence cannot be sent immediately after sending the N+4th test sequence. It is required to wait until the station status identifier becomes the sending identifier after the coprocessor processes the test data to obtain the test result, and then the N+5th test sequence can be sent.

[0164] Figure 8 The interaction diagram of the processing procedure of the adjacent two test sequences in the prior art when waiting is required is shown in Fig. 1. Figure 8 As shown in Fig. 1, the previous test sequence (indicated by black dots) is first sent by the host to the host module, and then sent by the host module to the test board card. The test board card sends an excitation signal (also indicated by black dots) to the device under test based on the test sequence (indicated by black dots), the device under test generates a response signal (also indicated by black dots) based on the excitation signal (indicated by black dots) and feeds back to the test board card, and the test board card obtains test data (also indicated by black dots) according to the response signal (indicated by black dots). The test data (indicated by black dots) is first sent by the test board card to the host module, and then sent by the host module to the host. The host processes the test data (indicated by black dots) to obtain a test result (also indicated by black dots).

[0165] After the whole processing procedure of the previous test sequence (indicated by black dots) is completed, the processing of the subsequent test sequence (indicated by white dots) is performed. The subsequent test sequence (indicated by white dots) is first sent by the host to the host module, and then sent by the host module to the test board card. The subsequent test sequence (indicated by white dots) is similar to the previous test sequence (indicated by black dots), and therefore the subsequent procedure is omitted.

[0166] Figure 9 The interaction diagram of the processing procedure of the adjacent two test sequences in an embodiment when waiting is required is shown in Fig. 2. Figure 9 As shown in Fig. 2, the previous test sequence (indicated by black dots) is first sent by the host to the host module, and then sent by the host module to the test board card. In this process, the host sends the subsequent test sequence (indicated by white dots) to the host module immediately after sending the previous test sequence (indicated by black dots) to the host module.

[0167] After receiving the previous test timing sequence (represented by black dots), the test board sends an excitation signal (also represented by black dots) to the device under test (DUT) based on this test timing sequence (represented by black dots). The DUT generates a response signal (also represented by black dots) based on the excitation signal (represented by black dots) and sends it back to the test board. The test board obtains test data (also represented by black dots) based on the response signal (represented by black dots). If this test data (represented by black dots) does not require data processing, it is first sent by the test board to the main control module, and then by the main control module to the host; if data processing is required, it is sent by the test board to the coprocessor. The coprocessor processes the test data (represented by black dots), obtains the test result (also represented by black dots), and sends it to both the main control module and the host. Upon receiving the test data or test result, the main control module immediately sends the next test timing sequence (represented by white dots) to the test board.

[0168] Figure 10 This is an interaction diagram illustrating the processing of two adjacent test sequences in the prior art when no waiting is required. For example... Figure 10 As shown, the previous test sequence (represented by black dots) is first sent from the host to the main control module, and then from the main control module to the test board. Based on this test sequence (represented by black dots), the test board sends a stimulus signal (also represented by black dots) to the device under test (DUT). The DUT generates a response signal (also represented by black dots) based on the stimulus signal (represented by black dots) and sends it back to the test board. The test board obtains test data (also represented by black dots) based on the response signal (represented by black dots). This test data (represented by black dots) is first sent from the test board to the main control module, and then from the main control module to the host.

[0169] The next test sequence (represented by a white dot) is processed only after the previous test sequence (represented by a black dot) has completed its entire processing. The next test sequence (represented by a white dot) is first sent from the host to the main control module, and then from the main control module to the test board... The next test sequence (represented by a white dot) is similar to the previous test sequence (represented by a black dot), so subsequent processes are omitted.

[0170] Figure 11 This is an interaction diagram illustrating the processing of two adjacent test sequences in one embodiment when no waiting is required. For example... Figure 11 As shown, the previous test timing sequence (represented by black dots) is first sent by the host to the main control module, and then the main control module sends it to the test board. Specifically, after the host sends the previous test timing sequence (represented by black dots) to the main control module, it immediately sends the next test timing sequence (represented by white dots) to the main control module as well.

[0171] After the test board card receives the previous test timing (indicated by a black dot), the test board card sends an excitation signal (also indicated by a black dot) to the device under test based on the test timing (indicated by a black dot). The device under test generates a response signal (also indicated by a black dot) based on the excitation signal (indicated by a black dot) and feeds back to the test board card. The test board card obtains test data (also indicated by a black dot) according to the response signal (indicated by a black dot). The test data (indicated by a black dot) is first sent to the host control module by the test board card, and then sent to the host by the host control module. After receiving the test data or the test result, the host control module immediately sends a next test timing (indicated by a white dot) to the test board card.

[0172] It should be understood that, although each step in the flowchart involved in each embodiment as described above is shown in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, at least part of the steps in the flowchart involved in each embodiment as described above can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or steps or stages in other steps.

[0173] Based on the same inventive concept, the embodiments of the present application also provide a test control device for implementing the test control method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the above method, so the specific limitations in one or more test control device embodiments provided below can refer to the limitations of the test control method described above, which will not be repeated here.

[0174] In one embodiment, as shown in FIG. 12, Figure 12 a test control device 1200 is provided, comprising a first receiving module 1201, an obtaining module 1202, and a first sending module 1203, wherein:

[0175] The first receiving module 1201 is configured to receive a first test timing sent by a host.

[0176] The obtaining module 1202 is configured to obtain a station state flag, wherein the station state flag comprises a sending flag or a pause flag.

[0177] The first sending module 1203 is configured to send the first test timing to the test board card to make the test board card send the excitation signal to the DUT according to the received first test timing to test the DUT when the station state flag comprises the sending flag; and pause sending the first test timing to the test board card until the station state flag changes from the pause flag to the sending flag when the station state flag comprises the pause flag.

[0178] In one embodiment, the first sending module 1203 is further configured to send a timing request to the host after receiving the first test timing sent by the host to make the host send the second test timing after the first test timing.

[0179] In one embodiment, the first receiving module 1201 is further configured to receive and buffer the second test timing sent by the host. The obtaining module 1202 is further configured to obtain the station state flag after sending the first test timing to the test board card. The first sending module 1203 is further configured to send the second test timing to the test board card to make the test board card send the excitation signal to the DUT according to the received second test timing to test the DUT when the station state flag comprises the sending flag; and pause sending the second test timing to the test board card until the station state flag changes from the pause flag to the sending flag when the station state flag comprises the pause flag.

[0180] In one embodiment, the first sending module 1203 is further configured to send a state update instruction to the state control module according to the first test timing after sending the first test timing to the test board card to make the state control module update the station state flag.

[0181] In one embodiment, the station state flag comprises the pause flag if the first test timing comprises the wait identifier; and the station state flag comprises the sending flag if the first test timing comprises the no-wait identifier or no identifier.

[0182] In one embodiment, the station state flag further comprises the judgment flag if the first test timing comprises the wait identifier and the process identifier; and the station state flag further comprises the no-judgment flag or only comprises the pause flag if the first test timing comprises the wait identifier and the no-process identifier or only comprises the wait identifier.

[0183] In one embodiment, the first receiving module 1201 is further configured to receive the test data containing the exception information sent by the test board card or the test result containing the exception information obtained by processing the test data by the coprocessor. The first sending module 1203 is further configured to stop sending the test timing to the test board card according to the exception information.

[0184] In one embodiment, as shown in FIG. 1, the test system comprises a host 100, a coprocessor 200 and a test board card 300. Figure 13As shown, a test control apparatus 1300 is provided, comprising: a second receiving module 1301 and a second sending module 1302, wherein:

[0185] The second receiving module 1301 is configured to receive a state request, the state request being sent by the master module after receiving the test timing sent by the host.

[0186] The second sending module 1302 is configured to send a station state flag to the master module according to the state request, the station state flag comprising a sending flag or a pause flag.

[0187] If the station state flag comprises the sending flag, the master module sends the test timing to the test board card, so that the test board card sends the excitation signal to the device under test according to the received test timing, and tests the device under test; if the station state flag comprises the pause flag, the master module pauses to send the test timing to the test board card until the station state flag changes from the pause flag to the sending flag.

[0188] In an embodiment, the second receiving module 1301 is further configured to receive a state update instruction, the state update instruction being sent by the master module according to the test timing after sending the test timing to the test board card. The apparatus further comprises a setting module configured to set the station state flag according to the state update instruction.

[0189] In an embodiment, if the test timing comprises a wait identifier, the station state flag comprises the pause flag; if the test timing comprises a no-wait identifier or no identifier, the station state flag comprises the sending flag.

[0190] In an embodiment, if the test timing comprises the wait identifier and a process identifier, the station state flag further comprises a judgment flag; if the test timing comprises the wait identifier and a no-process identifier or only the wait identifier, the station state flag further comprises a no-judgment flag or only the pause flag.

[0191] In an embodiment, the setting module is further configured to, when the station state flag comprises the pause flag and the no-judgment flag or only the pause flag, set the station state flag to the sending flag after determining that the master module receives the test data sent by the test board card; when the station state flag comprises the pause flag and the judgment flag, set the station state flag to the sending flag after determining that the co-processor processes the test data to obtain the test result.

[0192] The above-mentioned various modules in the test control apparatus can be realized by software, hardware and combinations thereof, in whole or in part. The above-mentioned various modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so as to be called and executed by the processor to perform the operations corresponding to the above-mentioned various modules.

[0193] In one embodiment, a computer device is provided, and an internal structure diagram of the computer device can be as shown in Figure 14 The computer device includes a processor, a memory, an input / output interface (I / O), and a communication interface. The processor, the memory, and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is configured to exchange information between the processor and external devices. The communication interface of the computer device is configured to communicate with external terminals through a network connection. The computer program is executed by the processor to implement a test control method.

[0194] Those skilled in the art can understand that Figure 14 The structure shown in the above embodiment is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0195] In one embodiment, a computer device is provided, and the computer device includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the following steps: receiving a first test timing sent by a host; obtaining a station state flag, the station state flag including a sending flag or a pause flag; if the station state flag includes the sending flag, sending the first test timing to a test board card, so that the test board card sends an excitation signal to a device under test according to the received first test timing, and tests the device under test.

[0196] In one embodiment, the processor executes the computer program to further implement the following steps: after receiving the first test timing sent by the host, sending a timing request to the host, so that the host sends a second test timing located after the first test timing.

[0197] In one embodiment, the processor, when executing the computer program, further implements the following steps: receiving and buffering the second test timing sent by the host; obtaining the station state flag after sending the first test timing to the test board card; if the station state flag comprises the sending flag, sending the second test timing to the test board card, so that the test board card sends the excitation signal to the device under test according to the received second test timing, and tests the device under test; if the station state flag comprises the pause flag, pausing sending the second test timing to the test board card until the station state flag changes from the pause flag to the sending flag.

[0198] In one embodiment, the processor, when executing the computer program, further implements the following steps: after sending the first test timing to the test board card, sending a state update instruction to the state control module according to the first test timing, so that the state control module updates the station state flag.

[0199] In one embodiment, the processor, when executing the computer program, further implements the following steps: if the first test timing comprises the waiting identifier, the station state flag comprises the pause flag; if the first test timing comprises the no-wait identifier or does not comprise the identifier, the station state flag comprises the sending flag.

[0200] In one embodiment, the processor, when executing the computer program, further implements the following steps: if the first test timing comprises the waiting identifier and the processing identifier, the station state flag further comprises the judgment flag; if the first test timing comprises the waiting identifier and the no-processing identifier or only comprises the waiting identifier, the station state flag further comprises the no-judgment flag or only comprises the pause flag.

[0201] In one embodiment, a computer device is provided, comprising a memory and a processor, the memory storing a computer program, and the processor, when executing the computer program, implements the following steps: receiving a state request, the state request being sent by a master module after receiving a test timing sent by a host; sending a station state flag to the master module according to the state request, the station state flag comprising a sending flag or a pause flag; wherein, if the station state flag comprises the sending flag, the master module sends the test timing to a test board card, so that the test board card sends an excitation signal to a device under test according to the received test timing, and tests the device under test; if the station state flag comprises the pause flag, the master module pauses sending the test timing to the test board card until the station state flag changes from the pause flag to the sending flag.

[0202] In one embodiment, the processor, when executing the computer program, further implements the following steps: receiving a state update instruction, the state update instruction being sent by the master module according to the test timing after sending the test timing to the test board card; setting the station state flag according to the state update instruction.

[0203] In one embodiment, the processor, when executing the computer program, further implements the following steps: if the test timing sequence includes the wait identifier, the station state identifier includes a pause identifier; if the test timing sequence includes the no-wait identifier or does not include the identifier, the station state identifier includes a send identifier.

[0204] In one embodiment, the processor, when executing the computer program, further implements the following steps: if the test timing sequence includes the wait identifier and the process identifier, the station state identifier further includes a judge identifier; if the test timing sequence includes the wait identifier and the no-process identifier or only includes the wait identifier, the station state identifier further includes a no-judge identifier or only includes the pause identifier.

[0205] In one embodiment, the processor, when executing the computer program, further implements the following steps: if the station state identifier includes the pause identifier and the no-judge identifier or only includes the pause identifier, after determining that the test data sent by the test board is received by the host module, the station state identifier is set to the send identifier; if the station state identifier includes the pause identifier and the judge identifier, after determining that the test data is processed by the coprocessor to obtain the test result, the station state identifier is set to the send identifier.

[0206] In one embodiment, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program, and the computer program, when executed by a processor, implements the following steps: receiving a first test timing sequence sent by a host; obtaining a station state identifier, the station state identifier including a send identifier or a pause identifier; if the station state identifier includes the send identifier, sending the first test timing sequence to a test board to make the test board send an excitation signal to a device under test according to the received first test timing sequence to test the device under test; if the station state identifier includes the pause identifier, pausing sending the first test timing sequence to the test board until the station state identifier changes from the pause identifier to the send identifier.

[0207] In one embodiment, the computer program, when executed by the processor, further implements the following steps: after receiving the first test timing sequence sent by the host, sending a timing sequence request to the host to make the host send a second test timing sequence located after the first test timing sequence.

[0208] In one embodiment, the computer program, when executed by the processor, further implements the following steps: receiving and buffering the second test timing sequence sent by the host; after sending the first test timing sequence to the test board, obtaining the station state identifier; if the station state identifier includes the send identifier, sending the second test timing sequence to the test board to make the test board send an excitation signal to the device under test according to the received second test timing sequence to test the device under test; if the station state identifier includes the pause identifier, pausing sending the second test timing sequence to the test board until the station state identifier changes from the pause identifier to the send identifier.

[0209] In one embodiment, the computer program, when executed by the processor, further implements the following steps: after sending the first test timing to the test board card, sending a state update instruction to the state control module according to the first test timing, so that the state control module updates the station state flag.

[0210] In one embodiment, the computer program, when executed by the processor, further implements the following steps: if the first test timing includes the wait identifier, the station state flag includes the pause flag; if the first test timing includes the no-wait identifier or does not include the identifier, the station state flag includes the send flag.

[0211] In one embodiment, the computer program, when executed by the processor, further implements the following steps: if the first test timing includes the wait identifier and the process identifier, the station state flag further includes the judge flag; if the first test timing includes the wait identifier and the no-process identifier or only includes the wait identifier, the station state flag further includes the no-judge flag or only includes the pause flag.

[0212] In one embodiment, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program. The computer program, when executed by the processor, implements the following steps: receiving a state request, the state request being sent by the master module after receiving the test timing sent by the host; according to the state request, sending the station state flag to the master module, the station state flag including the send flag or the pause flag; wherein, if the station state flag includes the send flag, the master module sends the test timing to the test board card, so that the test board card sends the excitation signal to the device under test according to the received test timing, and tests the device under test; if the station state flag includes the pause flag, the master module pauses to send the test timing to the test board card until the station state flag changes from the pause flag to the send flag.

[0213] In one embodiment, the computer program, when executed by the processor, further implements the following steps: receiving a state update instruction, the state update instruction being sent by the master module according to the test timing after sending the test timing to the test board card; setting the station state flag according to the state update instruction.

[0214] In one embodiment, the computer program, when executed by the processor, further implements the following steps: if the test timing includes the wait identifier, the station state flag includes the pause flag; if the test timing includes the no-wait identifier or does not include the identifier, the station state flag includes the send flag.

[0215] In one embodiment, the computer program, when executed by the processor, further implements the following steps: if the test timing includes the wait identifier and the process identifier, the station state flag further includes the judge flag; if the test timing includes the wait identifier and the no-process identifier or only includes the wait identifier, the station state flag further includes the no-judge flag or only includes the pause flag.

[0216] In one embodiment, the computer program, when executed by the processor, further implements the following steps: if the station state flag comprises the pause flag and the no-judge flag or only comprises the pause flag, setting the station state flag to the send flag after determining that the test data sent by the test board is received by the host module; if the station state flag comprises the pause flag and the judge flag, setting the station state flag to the send flag after determining that the test data is processed by the coprocessor to obtain the test result.

[0217] In one embodiment, a computer program product is provided, comprising a computer program which, when executed by the processor, implements the following steps: receiving the first test timing sent by the host; obtaining a station state flag, the station state flag comprising a send flag or a pause flag; if the station state flag comprises the send flag, sending the first test timing to the test board to make the test board send the excitation signal to the device under test according to the received first test timing to test the device under test; if the station state flag comprises the pause flag, pausing sending the first test timing to the test board until the station state flag changes from the pause flag to the send flag.

[0218] In one embodiment, the computer program, when executed by the processor, further implements the following steps: after receiving the first test timing sent by the host, sending a timing request to the host to make the host send the second test timing after the first test timing.

[0219] In one embodiment, the computer program, when executed by the processor, further implements the following steps: receiving the second test timing sent by the host and buffering; after sending the first test timing to the test board, obtaining the station state flag; if the station state flag comprises the send flag, sending the second test timing to the test board to make the test board send the excitation signal to the device under test according to the received second test timing to test the device under test; if the station state flag comprises the pause flag, pausing sending the second test timing to the test board until the station state flag changes from the pause flag to the send flag.

[0220] In one embodiment, the computer program, when executed by the processor, further implements the following steps: after sending the first test timing to the test board, sending a state update instruction to the state control module according to the first test timing to make the state control module update the station state flag.

[0221] In one embodiment, the computer program, when executed by the processor, further implements the following steps: if the first test timing comprises the wait identifier, the station state flag comprises the pause flag; if the first test timing comprises the no-wait identifier or does not comprise the identifier, the station state flag comprises the send flag.

[0222] In one embodiment, the computer program, when executed by the processor, further implements the following steps: if the first test timing sequence comprises the waiting identifier and the processing identifier, the station state flag further comprises a judgment identifier; if the first test timing sequence comprises the waiting identifier and the non-processing identifier or only comprises the waiting identifier, the station state flag further comprises a non-judgment identifier or only comprises the pause identifier.

[0223] In one embodiment, a computer program product is provided, comprising a computer program which, when executed by a processor, implements the following steps: receiving a state request, the state request being sent by a master module after receiving a test timing sequence sent by a host; sending a station state flag to the master module according to the state request, the station state flag comprising a sending identifier or a pause identifier; wherein, if the station state flag comprises the sending identifier, the master module sends the test timing sequence to a test board card, so that the test board card sends an excitation signal to a device under test according to the received test timing sequence to test the device under test; if the station state flag comprises the pause identifier, the master module pauses to send the test timing sequence to the test board card until the station state flag changes from the pause identifier to the sending identifier.

[0224] In one embodiment, the computer program, when executed by the processor, further implements the following steps: receiving a state update instruction, the state update instruction being sent by the master module according to the test timing sequence after sending the test timing sequence to the test board card; setting the station state flag according to the state update instruction.

[0225] In one embodiment, the computer program, when executed by the processor, further implements the following steps: if the test timing sequence comprises the waiting identifier, the station state flag comprises the pause identifier; if the test timing sequence comprises the non-waiting identifier or does not comprise the identifier, the station state flag comprises the sending identifier.

[0226] In one embodiment, the computer program, when executed by the processor, further implements the following steps: if the test timing sequence comprises the waiting identifier and the processing identifier, the station state flag further comprises the judgment identifier; if the test timing sequence comprises the waiting identifier and the non-processing identifier or only comprises the waiting identifier, the station state flag further comprises the non-judgment identifier or only comprises the pause identifier.

[0227] In one embodiment, the computer program, when executed by the processor, further implements the following steps: if the station state flag comprises the pause identifier and the non-judgment identifier or only comprises the pause identifier, setting the station state flag to the sending identifier after determining that the master module receives test data sent by the test board card; if the station state flag comprises the pause identifier and the judgment identifier, setting the station state flag to the sending identifier after determining that the coprocessor processes the test data to obtain a test result.

[0228] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of the country and region.

[0229] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing related hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of each method can be included. In the embodiments provided in the present application, any reference to memory, database or other medium can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., without being limited thereto.

[0230] The technical features of the above embodiments can be combined arbitrarily. In order to make the description simple, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present application.

[0231] The above-described embodiments are merely illustrative of several embodiments of the present application, and the description is relatively specific and detailed, but should not be understood as a limitation on the scope of the patent. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A test control method, characterized in that, The method is applied to the main control module of a testing machine; the testing machine includes a main control module, a coprocessor, at least one test board, and a status control module. The main control module is electrically connected to each test board, the coprocessor is electrically connected to the main control module, and the coprocessor is also electrically connected to each test board. The status control module is electrically connected to the main control module and each test board. The host is electrically connected to the main control module, and the device under test (DUT) is electrically connected to each test board. The method includes: The main control module receives the first test timing sequence sent by the host; The main control module acquires a workstation status flag, which includes a send flag or a pause flag. Specifically, when sending the second test sequence does not require waiting for the completion of the test corresponding to the first test sequence, the workstation status flag includes a send flag; when sending the second test sequence requires waiting for the completion of the test corresponding to the first test sequence, the workstation status flag includes a pause flag. The first test sequence and the second test sequence are two adjacent test sequences among multiple test sequences, and the second test sequence is located after the first test sequence. If the workstation status flag includes the sending flag, the main control module sends the first test timing sequence to the test board, so that the test board sends an excitation signal to the device under test according to the received first test timing sequence to test the device under test; If the workstation status flag includes the pause flag, the main control module pauses sending the first test sequence to the test board until the workstation status flag changes from the pause flag to the send flag. After the main control module sends the first test timing sequence to the test board, the main control module sends a status update instruction to the status control module according to the identifier and update conditions in the first test timing sequence, so that the status control module updates the workstation status flag. The update conditions include: when the workstation status flag includes a pause flag, after determining that the main control module has received the test data sent by the test board, setting the workstation status flag to the send flag; when the workstation status flag includes a pause flag and a judgment flag, after determining that the coprocessor has processed the test data to obtain the test result, setting the workstation status flag to the send flag.

2. The method according to claim 1, characterized in that, The method further includes: After receiving the first test timing sequence sent by the host, a timing request is sent to the host so that the host sends a second test timing sequence that follows the first test timing sequence.

3. The method according to claim 2, characterized in that, The method further includes: Receive the second test timing sequence sent by the host and cache it; After sending the first test sequence to the test board, the workstation status flag is obtained; If the workstation status flag includes the sending flag, then the second test timing sequence is sent to the test board so that the test board sends an excitation signal to the device under test according to the received second test timing sequence to test the device under test; If the workstation status flag includes the pause flag, then the transmission of the second test sequence to the test board is paused until the workstation status flag changes from the pause flag to the transmit flag.

4. The method according to claim 1, characterized in that, If the first test sequence includes a waiting flag, then the workstation status flag includes the pause flag; if the first test sequence includes a no-wait flag or does not include a flag, then the workstation status flag includes the send flag.

5. The method according to claim 4, characterized in that, If the first test sequence includes a waiting flag and a processing flag, then the workstation status flag also includes a judgment flag; if the first test sequence includes a waiting flag and a no-processing flag or only a waiting flag, then the workstation status flag also includes a no-judgment flag or only a pause flag.

6. A test control method, characterized in that, The method is applied to the state control module of a testing machine. The testing machine includes a main control module, a coprocessor, at least one test board, and a state control module. The main control module is electrically connected to each test board, the coprocessor is electrically connected to the main control module, and the coprocessor is also electrically connected to each test board. The state control module is electrically connected to the main control module and each test board. The host is electrically connected to the main control module, and the device under test (DUT) is electrically connected to each test board. The method includes: The status control module receives a status request, which is sent by the main control module after receiving the test sequence from the host. The status control module sends a workstation status flag to the main control module according to the status request. The workstation status flag includes a send flag or a pause flag. Specifically, if the sending of the second test sequence does not require waiting for the completion of the test corresponding to the first test sequence, the workstation status flag includes a send flag. If the sending of the second test sequence requires waiting for the completion of the test corresponding to the first test sequence, the workstation status flag includes a pause flag. The first test sequence and the second test sequence are two adjacent test sequences among multiple test sequences, and the second test sequence is located after the first test sequence. If the workstation status flag includes the send flag, the main control module sends the test sequence to the test board, so that the test board sends an excitation signal to the device under test according to the received test sequence to test the device under test; if the workstation status flag includes the pause flag, the main control module pauses sending the test sequence to the test board until the workstation status flag changes from the pause flag to the send flag. The status control module receives status update instructions and update conditions, which are sent by the main control module according to the test timing sequence after sending the test timing sequence to the test board. The status control module sets the workstation status flag according to the status update instruction and update conditions; wherein, the update conditions include: when the workstation status flag includes a pause flag, after determining that the main control module has received the test data sent by the test board, setting the workstation status flag to the send flag; when the workstation status flag includes a pause flag and a judgment flag, after determining that the coprocessor has processed the test data to obtain the test result, setting the workstation status flag to the send flag.

7. The method according to claim 6, characterized in that, If the test sequence includes a waiting flag, then the workstation status flag includes the pause flag; if the test sequence includes a no-wait flag or does not include a flag, then the workstation status flag includes the send flag.

8. The method according to claim 7, characterized in that, If the test sequence includes a waiting flag and a processing flag, then the workstation status flag also includes a judgment flag; if the test sequence includes a waiting flag and a no-processing flag or only a waiting flag, then the workstation status flag also includes a no-judgment flag or only a pause flag.

9. The method according to claim 8, characterized in that, The method further includes: If the workstation status flag includes a pause flag and a no-determination flag, or only includes a pause flag, then after determining that the main control module has received the test data sent by the test board, the workstation status flag is set to the sending flag.

10. A test control device, characterized in that, The device includes: The first receiving module is used to receive the first test timing sequence sent by the host; An acquisition module is used to acquire a workstation status flag, which includes a send flag or a pause flag. Specifically, when the transmission of the second test sequence does not require waiting for the completion of the test corresponding to the first test sequence, the workstation status flag includes a send flag; when the transmission of the second test sequence requires waiting for the completion of the test corresponding to the first test sequence, the workstation status flag includes a pause flag. The first test sequence and the second test sequence are two adjacent test sequences among multiple test sequences, and the second test sequence is located after the first test sequence. The first sending module is configured to send the first test timing sequence to the test board when the workstation status flag includes the sending flag, so that the test board sends an excitation signal to the device under test according to the received first test timing sequence to test the device under test; and to pause sending the first test timing sequence to the test board when the workstation status flag includes the pause flag, until the workstation status flag changes from the pause flag to the sending flag. The device is further configured to, after sending the first test timing sequence to the test board, send a status update instruction to the status control module according to the identifier and update conditions in the first test timing sequence, so that the status control module updates the workstation status flag. The update conditions include: when the workstation status flag includes a pause flag, after determining that the main control module has received the test data sent by the test board, setting the workstation status flag to the sending flag; when the workstation status flag includes a pause flag and a judgment flag, after determining that the coprocessor has processed the test data to obtain the test result, setting the workstation status flag to the sending flag.

11. A test control device, characterized in that, The device includes: The second receiving module is used to receive status requests, which are sent by the main control module after receiving the test timing data sent by the host. The second sending module is used to send a workstation status flag to the main control module according to the status request. The workstation status flag includes a sending flag or a pause flag. Where the sending of the second test sequence does not require waiting for the completion of the test corresponding to the first test sequence, the workstation status flag includes a sending flag. Where the sending of the second test sequence requires waiting for the completion of the test corresponding to the first test sequence, the workstation status flag includes a pause flag. The first test sequence and the second test sequence are two adjacent test sequences among multiple test sequences, and the second test sequence is located after the first test sequence. If the workstation status flag includes the send flag, the main control module sends the test sequence to the test board, so that the test board sends an excitation signal to the device under test according to the received test sequence to test the device under test; if the workstation status flag includes the pause flag, the main control module pauses sending the test sequence to the test board until the workstation status flag changes from the pause flag to the send flag. The device is also used to receive status update instructions and update conditions, wherein the status update instructions and update conditions are sent by the main control module according to the test timing sequence after sending the test timing sequence to the test board; The device is further configured to set the workstation status flag according to the status update instruction and update conditions, wherein the update conditions include: when the workstation status flag includes a pause flag, after determining that the main control module has received the test data sent by the test board, setting the workstation status flag to the send flag; when the workstation status flag includes a pause flag and a judgment flag, after determining that the coprocessor has processed the test data to obtain the test result, setting the workstation status flag to the send flag.

12. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 5, or the steps of the method according to any one of claims 6 to 9.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5, or the steps of the method according to any one of claims 6 to 9.

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