A memory

Abstract

The application discloses a memory, comprising: a memory structure body, a first source line compensation resistor to an Xth source line compensation resistor, a first bit line compensation resistor to an Xth bit line compensation resistor; an i-th source line compensation resistor is arranged in series on a source line total branch of an i-th storage library, an i-th bit line compensation resistor is arranged in series on a bit line total branch of the i-th storage library, a resistance value of the i-th source line compensation resistor is Ra x i, and a resistance value of the i-th bit line compensation resistor is Rb x i; the first global source line and the first global bit line of the memory are shared by the 0th storage library to the Xth storage library, and a line physical distance between the 0th storage library to the Xth storage library and a global driver in the memory structure body decreases; Ra and Rb respectively represent parasitic resistance values on the first global source line and the first global bit line between adjacent two storage libraries. The scheme of the application effectively guarantees the reliability of the memory. The scheme is simple, easy to implement and low in cost.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a memory. Background Technology

[0002] With the continuous development of technology, the demand for memory capacity is increasing. Within memory, there is an inverse exponential relationship between the voltage a storage cell withstands and its durability; that is, the higher the voltage it withstands, the shorter its lifespan.

[0003] Especially for large-capacity memory, the significant differences in physical distance between memory cells at different addresses result in noticeable differences in the length of read / write transmission paths. (See also...) Figure 1 , Figure 1 In this context, "Bank" refers to the storage bank. Banks in the far-end address segment have longer transmission paths and therefore more parasitic resistance than banks in the near-end address segment. To ensure that each memory cell in the far-end address segment bank has sufficient read / write voltage, the required voltage value is usually set based on the far-end address segment bank, which has more parasitic resistance. However, as described above, this approach exceeds the required voltage value for the near-end address segment bank, which has lower parasitic resistance, resulting in a shorter lifespan for the near-end address segment bank and thus affecting the reliability of the memory.

[0004] In conclusion, how to effectively ensure the reliability of memory is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a memory that effectively ensures the reliability of the memory.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] A memory, comprising:

[0008] The main body of the memory structure includes the first to the Xth source line compensation resistors and the first to the Xth bit line compensation resistors.

[0009] The i-th source line compensation resistor is connected in series on the source line branch of the i-th storage unit, and the i-th bit line compensation resistor is connected in series on the bit line branch of the i-th storage unit. The resistance value of the i-th source line compensation resistor is Ra×i, and the resistance value of the i-th bit line compensation resistor is Rb×i.

[0010] Repositories 0 to X share the first global source line and the first global bit line of the memory, and the physical distance between the line and the global driver in the main body of the memory structure decreases from repository 0 to repository X.

[0011] Where X is a positive integer, i is a positive integer and 1≤i≤X, Ra represents the parasitic resistance value on the first global source line between two adjacent repositories, and Rb represents the parasitic resistance value on the first global bit line between two adjacent repositories.

[0012] Preferably, it also includes: an inter-block compensation circuit and a first decoder;

[0013] The first decoder is configured to: when any storage block in any repository from repository 0 to repository X is selected, control the resistance value of the inter-block compensation circuit based on the address of the selected storage block to perform inter-block parasitic resistance compensation.

[0014] Preferably, the inter-block compensation circuit includes a source line inter-block compensation circuit disposed on the first global source line and a bit line inter-block compensation circuit disposed on the first global bit line, and the first decoder is specifically used for:

[0015] When any storage block in any repository from repository 0 to repository X is selected, the resistance value of the source line inter-block compensation circuit is controlled based on the address of the selected storage block, according to the rule that the closer the physical distance between the storage block and the global driver, the greater the resistance value of the source line inter-block compensation circuit; and the resistance value of the bit line inter-block compensation circuit is controlled according to the rule that the closer the physical distance between the storage block and the global driver, the greater the resistance value of the bit line inter-block compensation circuit.

[0016] Preferably, each of the 0th to Xth repositories includes 0th to Yth storage blocks, and in any repository, the physical distance between the line and the global driver decreases from the 0th storage block to the Yth storage block in that repository; the source line inter-block compensation circuit is connected to the first power supply positive terminal and the input terminal of the first global source line, and the bit line inter-block compensation circuit is connected to the second power supply positive terminal and the input terminal of the first global bit line;

[0017] The first decoder is specifically used for:

[0018] When the selected storage block is the j-th storage block in any of the repositories from 0 to X, and the current mode is the first path, the resistance of the source line inter-block compensation circuit is controlled to be Rc×j, the resistance of the bit line inter-block compensation circuit is controlled to be Rd×j, and the current is controlled to flow from the source line inter-block compensation circuit to the bit line inter-block compensation circuit; when the selected storage block is the j-th storage block in any of the repositories from 0 to X, and the current mode is the second path, the resistance of the source line inter-block compensation circuit is controlled to be Rc×j, the resistance of the bit line inter-block compensation circuit is controlled to be Rd×j, and the current is controlled to flow from the bit line inter-block compensation circuit to the source line inter-block compensation circuit.

[0019] Where Y is a positive integer, j is an integer and 0≤j≤Y, Rc represents the source line parasitic resistance value in a single memory block, and Rd represents the bit line parasitic resistance value in a single memory block.

[0020] Preferably, the source line parasitic resistance value in a single memory block is the source line parasitic resistance value determined by the parameter information of the source line and the number of memory cells divided in a single memory block;

[0021] The parasitic resistance value of the bit line in a single memory block is determined by the parameter information of the bit line and the number of memory cells in the single memory block.

[0022] Preferably, the source line block compensation circuit includes: the 0th to the Yth source line bridge arms arranged in parallel, and Y source line block resistors; each source line bridge arm is composed of an upper switch and a lower switch connected in series, and the connection end of the upper switch and the lower switch serves as the middle end of the source line bridge arm, and the middle ends of any two adjacent source line bridge arms are connected through one source line block resistor, and the resistance value of each source line block resistor is Rc;

[0023] The first ends of the 0th to Yth source line bridge arms are all connected to the positive terminal of the first power supply, the second ends of the 0th to Yth source line bridge arms are all grounded, and the middle end of the 0th source line bridge arm is connected to the input terminal of the first global source line.

[0024] The bit line inter-block compensation circuit includes: the 0th to the Yth bit line bridge arms arranged in parallel, and Y bit line inter-block resistors; each bit line bridge arm is composed of an upper switch and a lower switch connected in series, and the connection end of the upper switch and the lower switch serves as the middle end of the bit line bridge arm. The middle ends of any two adjacent bit line bridge arms are connected through one bit line inter-block resistor, and the resistance value of each bit line inter-block resistor is Rd.

[0025] The first ends of the 0th to Yth bit line bridge arms are all connected to the positive terminal of the second power supply, the second ends of the 0th to Yth bit line bridge arms are all grounded, and the middle end of the 0th bit line bridge arm is connected to the input terminal of the first global bit line.

[0026] The first decoder is specifically used to: when the selected storage block is the j-th storage block in any of the 0 to X storage repositories, and the current mode is the first path mode, control the upper switch of the j-th source line bridge arm to be turned on, and control the lower switch of the j-th bit line bridge arm to be turned on; when the selected storage block is the j-th storage block in any of the 0 to X storage repositories, and the current mode is the second path mode, control the lower switch of the j-th source line bridge arm to be turned on, and control the upper switch of the j-th bit line bridge arm to be turned on.

[0027] Preferably, both the source line block compensation circuit and the bit line block compensation circuit are integrated into the global driver.

[0028] Preferably, the parasitic resistance value on the first global source line between two adjacent repositories is the parasitic resistance value determined by the parameter information of the first global source line;

[0029] The parasitic resistance value on the first global bit line between two adjacent repositories is the parasitic resistance value determined by the parameter information of the first global bit line.

[0030] Preferably, the first end of the i-th source line compensation resistor serves as the connection end between the source line main branch of the i-th storage repository and the first global source line, and the second end of the i-th source line compensation resistor is connected to the start switch on the source line main branch of the i-th storage repository.

[0031] The first end of the i-th bit line compensation resistor serves as the connection point between the bit line main branch of the i-th storage repository and the first global bit line, and the second end of the i-th bit line compensation resistor is connected to the start switch on the bit line main branch of the i-th storage repository.

[0032] Preferably, it further includes: source line compensation resistors from the (X+2)th to the (X+Z)th bit line compensation resistors;

[0033] The source line compensation resistor is connected in series on the source line branch of the storage a, the bit line compensation resistor is connected in series on the bit line branch of the storage a, and the resistance value of the source line compensation resistor is Ra2×(aX-1), and the resistance value of the bit line compensation resistor is Rb2×(aX-1).

[0034] The X+1 to X+Z repositories share the second global source line and the second global bit line of the memory, and the physical distance between the lines and the global drivers in the main body of the memory structure decreases from the X+1 repository to the X+Z repository.

[0035] Where X and Z are both positive integers, a is a positive integer and X+2≤a≤X+Z, Ra2 represents the parasitic resistance value on the second global source line between two adjacent repositories, and Rb2 represents the parasitic resistance value on the second global bit line between two adjacent repositories.

[0036] Preferably, the memory further includes an inter-block compensation circuit and a first decoder;

[0037] The first decoder is used to: when any storage block in any repository from the (X+1)th to the (X+Z)th repository is selected, control the resistance value of the inter-block compensation circuit based on the address of the selected storage block to perform inter-block parasitic resistance compensation.

[0038] Preferably, the memory is an MRAM memory.

[0039] By applying the technical solution provided in this invention, different sizes of source line compensation resistors and bit line compensation resistors are set to compensate for the parasitic resistance of different memory repositories, thereby ensuring that memory repositories in different address segments can receive appropriate voltage values ​​and thus guaranteeing memory reliability. Specifically, in the solution of this application, source line compensation resistors from the first to the Xth and bit line compensation resistors from the first to the Xth are set. The 0th to Xth repositories share the first global source line and the first global bit line of the memory. From the 0th to the Xth repositories, the physical distance between the lines and the global drivers in the main memory structure decreases. Therefore, in this application, the i-th source line compensation resistor is connected in series on the source line branch of the i-th repository, and the i-th bit line compensation resistor is connected in series on the bit line branch of the i-th repository. The resistance value of the i-th source line compensation resistor is Ra×i, and the resistance value of the i-th bit line compensation resistor is Rb×i. That is, the closer to the global driver, the larger the resistance values ​​of the source line compensation resistor and the bit line compensation resistor are. Conversely, the farther away from the global driver, the larger the existing parasitic resistance on the line, and therefore the smaller the compensation resistance value is set. As can be seen, by setting source line compensation resistors and bit line compensation resistors of different sizes to compensate for the parasitic resistance of different memory repositories, the equivalent resistance between the repositories in different address segments and the global driver is consistent. This ensures that repositories in different address segments receive consistent voltage values, preventing voltage deviations in repositories in near-end address segments. Therefore, the solution in this application effectively guarantees the reliability of the memory. Furthermore, this application only requires setting source line compensation resistors from the 1st to the Xth and bit line compensation resistors from the 1st to the Xth to achieve parasitic resistance compensation between repositories from the 0th to the Xth. The solution is simple to implement, low in cost, and requires minimal hardware modifications to the memory. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A schematic diagram showing the parasitic resistance difference between banks;

[0042] Figure 2 This is a schematic diagram of the structure of a memory according to the present invention;

[0043] Figure 3 This is a schematic diagram of the first structure of a memory in a specific embodiment of the present invention;

[0044] Figure 4 A schematic diagram showing the parasitic resistance difference within the bank;

[0045] Figure 5 This is a schematic diagram of the source line and bit line block compensation circuit in a specific embodiment of the present invention.

[0046] Figure 6a This is a schematic diagram of the P2AP path mode in a specific embodiment of the present invention;

[0047] Figure 6b This is a schematic diagram of the AP2P path mode in a specific embodiment of the present invention;

[0048] Figure 7 This is a schematic diagram of the second structure of the memory in a specific embodiment of the present invention. Detailed Implementation

[0049] The core of this invention is to provide a memory that effectively ensures memory reliability. Furthermore, the solution is simple to implement and has low cost.

[0050] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of a memory according to the present invention, which may include:

[0052] The main body of the memory structure includes the first to the Xth source line compensation resistors and the first to the Xth bit line compensation resistors.

[0053] The i-th source line compensation resistor is connected in series on the source line branch of the i-th storage unit, and the i-th bit line compensation resistor is connected in series on the bit line branch of the i-th storage unit. The resistance value of the i-th source line compensation resistor is Ra×i, and the resistance value of the i-th bit line compensation resistor is Rb×i.

[0054] The 0th to the Xth repositories share the first global source line and the first global bit line of the memory, and the physical distance between the lines and the global drivers in the memory structure body decreases from the 0th to the Xth repositories.

[0055] Where X is a positive integer, i is a positive integer and 1≤i≤X, Ra represents the parasitic resistance value on the first global source line between two adjacent repositories, and Rb represents the parasitic resistance value on the first global bit line between two adjacent repositories.

[0056] Specifically, the memory structure described in this application refers to the memory structure other than the first to Xth source line compensation resistors and the first to Xth bit line compensation resistors. The specific details may depend on the actual memory structure design in the specific application. Figure 3 This is a schematic diagram of the structure of MRAM (Magnetoresistive Random Access Memory) in a specific embodiment. Figure 3 The diagram illustrates the memory structure, including repositories 0 through X, the global I / O module, the global driver, the top-level controller, the sub-controllers, the word line drivers, and the line selectors. Figure 3 Each line selector is labeled MUX.

[0057] Repositories 0 through X share the first global source line and the first global bit line of the memory, and the physical distance between the lines and the global drivers in the main body of the memory structure decreases from repository 0 to repository X.

[0058] In high-density, high-capacity memory, a bank is typically divided into multiple banks based on their addresses. Due to differences in physical distance from the global driver, the parasitic resistance on the lines between different banks and the global driver varies. It is understandable that the greater the distance from the global driver, the greater the parasitic resistance.

[0059] It should also be noted that in this application, the repository farthest from the global driver among the first global source lines and the first global bit lines of the shared memory is designated as repository 0, the second farthest is designated as repository 1, and repository X is closest to the global driver. In other specific cases, other numbering methods may be used, such as designating repository 0 as the one closest to the global driver. This can be achieved by following the principles of this application and appropriately setting the resistance values ​​of the compensation resistors for each source line and each bit line based on the differences in the physical distance between each repository and the global driver.

[0060] This application achieves compensation of source line parasitic resistance values ​​between different banks through source line compensation resistors from the first to the Xth, and achieves compensation of bit line parasitic resistance values ​​between different banks through bit line compensation resistors from the first to the Xth.

[0061] Specifically, this application requires that the i-th source line compensation resistor be connected in series on the source line main branch of the i-th storage repository, and the i-th bit line compensation resistor be connected in series on the bit line main branch of the i-th storage repository, and the resistance value of the i-th source line compensation resistor is Ra×i, and the resistance value of the i-th bit line compensation resistor is Rb×i.

[0062] In practical applications, the number of source line branches and bit line branches varies depending on the arrangement of storage cells in the repository. This application connects the i-th source line compensation resistor in series on the total source line branch of the i-th repository. Compared to setting a separate source line compensation resistor on each source line branch, this requires fewer resistors, thus improving the reliability of the proposed solution. The same principle applies to bit lines and source lines.

[0063] Furthermore, it can be understood that the total source line branch of the i-th repository refers to the total source line branch after summing all source line branches of the i-th repository, and the total source line branch of the i-th repository needs to be connected to the first global source line. Bit lines are analogous to source lines. This application's... Figure 2 For ease of description, the diagram shows the source line branch and bit line branch of each repository.

[0064] Ra represents the parasitic resistance value on the first global source line between two adjacent repositories. Repository 0 is farthest from the global driver, so no compensation is needed. Repository 1 is the second farthest from the global driver, so a first source line compensation resistor needs to be set for it, with a resistance value of Ra. Similarly, repository X is closest to the global driver and has the smallest parasitic resistance value on its source line, therefore a first source line compensation resistor needs to be set for it, with a resistance value of Ra × X.

[0065] Similar to the source line, Rb represents the parasitic resistance value on the first global bit line between two adjacent repositories. Repository 0 is farthest from the global driver, so no compensation is needed. Repository 1 is the second farthest from the global driver, so a first bit line compensation resistor needs to be set for it, with a resistance value of Rb. And so on, repository X is closest to the global driver and has the smallest parasitic resistance value on the bit line, therefore a first bit line compensation resistor needs to be set for it, with a resistance value of Rb×X.

[0066] Because of the provision of source line compensation resistors from the 1st to the Xth and bit line compensation resistors from the 1st to the Xth, the differences in parasitic resistance values ​​between different banks and the global driver are compensated, thereby enabling different banks to withstand consistent voltages and ensuring the service life of each bank.

[0067] Different source line compensation resistors have different resistance values. In practical applications, for any given source line compensation resistor, the required resistance value can be achieved through a single resistor or by connecting multiple resistors in series or parallel. For example, in a specific scenario, using Ra as a resistance unit, a corresponding number of resistance units Ra are selected and connected in series according to the required resistance value of the source line compensation resistor to obtain the desired resistance value. The same principle applies to bit lines and source lines.

[0068] In addition, X is a positive integer, and its specific value can be set and adjusted according to actual needs. Furthermore, in practical applications, the number of banks in the memory can usually be a power of 2.

[0069] In one specific embodiment of the present invention, the parasitic resistance value on the first global source line between two adjacent repositories is the parasitic resistance value determined by the parameter information of the first global source line.

[0070] The parasitic resistance value on the first global bit line between two adjacent repositories is the parasitic resistance value determined by the parameter information of the first global bit line.

[0071] In this implementation, the value of Ra is determined by the parameter information of the first global source line, and the value of Rb is determined by the parameter information of the first global bit line, which is relatively simple and convenient.

[0072] Specifically, the memory cells and global drivers are typically connected by metals of characteristic dimensions, such as 20nm-30nm Cu or W. Therefore, the resistance of any single line can be easily determined by the formula R = rho * L / (W * T), where R represents the resistance of the line, rho represents the resistivity of the line material, and L, W, and T represent the length, width, and thickness of the line, respectively. Thus, by obtaining the parameter information of the first global source line, the value of Ra can be easily determined; similarly, by obtaining the parameter information of the first global bit line, the value of Rb can be easily determined.

[0073] This application requires that the i-th source line compensation resistor be connected in series on the source line main branch of the i-th storage repository, and the i-th bit line compensation resistor be connected in series on the bit line main branch of the i-th storage repository. The specific positions can be set as needed. In a specific embodiment of the present invention, the first end of the i-th source line compensation resistor serves as the connection end between the source line main branch of the i-th storage repository and the first global source line, and the second end of the i-th source line compensation resistor is connected to the start switch on the source line main branch of the i-th storage repository.

[0074] The first end of the i-th bit line compensation resistor serves as the connection point between the bit line main branch of the i-th storage repository and the first global bit line, and the second end of the i-th bit line compensation resistor is connected to the start switch on the bit line main branch of the i-th storage repository.

[0075] In this embodiment, each source line compensation resistor is connected in series at the start switch on the main branch of the source line of the corresponding storage unit, and each bit line compensation resistor is connected in series at the start switch on the main branch of the bit line of the corresponding storage unit, which facilitates the arrangement of each source line compensation resistor and each bit line compensation resistor.

[0076] In practical applications, the source line compensation resistors and bit line compensation resistors can be selected as metal resistors, ploy resistors, trap resistors, or other types of resistors as needed. The types of resistors in the embodiments described below can also be selected as needed.

[0077] The start switch on the source line branch of the i-th repository, and the start switch on the bit line branch of the i-th repository, are activated when reading or writing to the i-th repository is required. Figure 2 The second decoder controls the conduction of both based on the received address. Each start switch and the second decoder are typically pre-configured in the memory, meaning this application requires no additional configuration. The specific switch type for each start switch can be various types such as NMOS transistor, PMOS transistor, transmission gate, or bipolar transistor, and can be set as needed.

[0078] In addition, Figure 3In this process, the i-th source line compensation resistor and the i-th bit line compensation resistor are integrated into the line selector MUX corresponding to the i-th repository. Figure 3 The label "Between_Bank_Compensation" indicates that the parasitic resistance between banks is being compensated.

[0079] The applicant further considered, see reference Figure 4 Not only are there differences in parasitic resistance between banks, but within a bank, each bank is typically divided into multiple blocks based on block addresses. The physical distance between blocks also varies, resulting in different voltages experienced by the memory cells within each block. Therefore, in one specific embodiment of this application, parasitic resistance compensation is also performed between different blocks. A block is the memory block described in this application.

[0080] Specifically, the memory may also include: inter-block compensation circuitry and a first decoder;

[0081] The first decoder is used to: when any storage block in any repository from repository 0 to repository X is selected, control the resistance value of the inter-block compensation circuit based on the address of the selected storage block to perform inter-block parasitic resistance compensation.

[0082] The specific circuit configuration of the inter-block compensation circuit can be set according to actual needs, but it is understood that the inter-block compensation circuit needs to be connected to the first decoder. The first decoder can obtain the address of the currently selected memory block, and then adaptively control the resistance value of the inter-block compensation circuit based on the address of the currently selected memory block, thereby compensating for the parasitic resistance between different blocks.

[0083] Considering that there are two path modes, in a specific embodiment of the present invention, in order to facilitate the implementation of the inter-block compensation circuit, the inter-block compensation circuit may specifically include a source line inter-block compensation circuit disposed on the first global source line and a bit line inter-block compensation circuit disposed on the first global bit line. The first decoder can control the specific state of the source line inter-block compensation circuit and the bit line inter-block compensation circuit.

[0084] The first decoder is specifically used for:

[0085] When any storage block in any repository from repository 0 to repository X is selected, the resistance value of the source line inter-block compensation circuit is controlled based on the address of the selected storage block, according to the rule that the closer the physical distance between the storage block and the global driver, the greater the resistance value of the source line inter-block compensation circuit; and the resistance value of the bit line inter-block compensation circuit is controlled according to the rule that the closer the physical distance between the storage block and the global driver, the greater the resistance value of the bit line inter-block compensation circuit.

[0086] In this embodiment, since the source line inter-block compensation circuit is set on the first global source line and the bit line inter-block compensation circuit is set on the first global bit line, for any storage block in any repository from the 0th to the Xth repository, the source line inter-block compensation circuit and the bit line inter-block compensation circuit are used when compensating for the parasitic resistance between blocks. This makes the solution of this application very low in cost. That is, the parasitic resistance compensation between blocks in any repository from the 0th to the Xth repository is achieved by using one source line inter-block compensation circuit and one bit line inter-block compensation circuit.

[0087] When performing inter-block parasitic resistance compensation, the first decoder controls the resistance value of the source line inter-block compensation circuit according to the rule that the closer the physical distance between the memory block and the global driver, the higher the resistance value of the source line inter-block compensation circuit. This ensures that the parasitic resistance on the source lines of different blocks within the same memory bank relative to the global driver remains consistent. Similarly, the first decoder controls the resistance value of the bit line inter-block compensation circuit according to the rule that the closer the physical distance between the memory block and the global driver, the higher the resistance value of the bit line inter-block compensation circuit. This ensures that the parasitic resistance on the bit lines of different blocks within the same memory bank relative to the global driver remains consistent.

[0088] In one specific embodiment of the present invention, each of the 0th to Xth repositories includes the 0th to Yth storage blocks, and in any repositories, the physical distance of the line between the 0th storage block and the global driver decreases from the 0th storage block to the Yth storage block in that repository; the source line block compensation circuit is connected to the first power supply positive terminal and the input terminal of the first global source line, and the bit line block compensation circuit is connected to the second power supply positive terminal and the input terminal of the first global bit line;

[0089] The first decoder is specifically used for:

[0090] When the selected storage block is the j-th storage block in any of the storage repositories from the 0th to the Xth, and the current mode is the first path, the resistance of the source line inter-block compensation circuit is controlled to be Rc×j, and the resistance of the bit line inter-block compensation circuit is controlled to be Rd×j, and the control current flows from the source line inter-block compensation circuit to the bit line inter-block compensation circuit.

[0091] When the selected storage block is the j-th storage block in any of the storage repositories from the 0th to the Xth repository, and the current is the second path mode, the resistance of the source line inter-block compensation circuit is controlled to be Rc×j, and the resistance of the bit line inter-block compensation circuit is controlled to be Rd×j, and the control current flows from the bit line inter-block compensation circuit to the source line inter-block compensation circuit.

[0092] Where Y is a positive integer, j is an integer and 0≤j≤Y, Rc represents the source line parasitic resistance value in a single memory block, and Rd represents the bit line parasitic resistance value in a single memory block.

[0093] In practical applications, the first decoder can be an additional setting, or it can be a function reuse of some existing decoders to achieve the function of the first decoder required by this application.

[0094] Similar to the numbering of repositories described above, in this embodiment of the application, the physical distance between the storage block from the 0th to the Yth storage block in any of the repositories from the 0th to the Xth is decreasing from the global drive. That is, for any of the repositories from the 0th to the Xth, the storage block farthest from the global drive is numbered as storage block 0, and so on, with the storage block closest to the global drive being numbered as storage block Y.

[0095] In other specific situations, other numbering methods can be used. For example, the memory block farthest from the global driver can be numbered as memory block Y, and so on, with the memory block closest to the global driver numbered as memory block 0. Simply follow the principles of this application, and when reading and writing memory blocks, control the source line inter-block compensation circuit and the bit line inter-block compensation circuit accordingly based on the specific location of the memory block.

[0096] The source line inter-block compensation circuit is located at the input terminal of the first global source line, and the bit line inter-block compensation circuit is connected to the input terminal of the first global bit line. The first decoder can generate corresponding switch control signals based on the address of the currently selected memory block and according to the current path pattern. This controls the state of the source line inter-block compensation circuit and the bit line inter-block compensation circuit, specifically controlling their resistance values ​​to ensure that the current resistance value meets the compensation requirements of the memory block currently being read from or written to, and that the current direction conforms to the current path pattern.

[0097] The first path mode is P2AP (parallel to anti-parallel) path mode, which refers to the path of current flowing from the source line to the bit line, which can change 0 in the memory cell to 1. The second path mode is AP2P (anti-parallel to parallel) path mode, which refers to the path of current flowing from the bit line to the source line, which can change 1 in the memory cell to 0.

[0098] Since the physical distance between the global driver and the 0th block to the Yth block in any of the repositories from 0 to X decreases, when the selected block is the jth block in any of the repositories from 0 to X, the switch control signal generated by the first decoder needs to control the resistance of the source line inter-block compensation circuit to Rc×j. That is, for the 0th block, which is farthest from the global driver in the repository, no compensation is needed, meaning the resistance of the source line inter-block compensation circuit is 0. For the 1st block, which is the second farthest from the global driver in the repository, the resistance of the source line inter-block compensation circuit needs to be Rc, and so on. For the Yth block, which is closest to the global driver in the repository, the resistance of the source line inter-block compensation circuit needs to be Rc×Y. The bit line inter-block compensation circuit works similarly to the source line inter-block compensation circuit.

[0099] The specific circuit configurations of the source line block compensation circuit and the bit line block compensation circuit can be set as needed, as long as they can achieve the functions of this application.

[0100] See also Figure 5 In one specific embodiment of the present invention, the source line block compensation circuit includes: the 0th to the Yth source line bridge arms arranged in parallel, and Y source line block resistors; each source line bridge arm is composed of an upper switch and a lower switch connected in series, and the connection end of the upper switch and the lower switch serves as the middle end of the source line bridge arm, and the middle ends of any two adjacent source line bridge arms are connected through one source line block resistor, and the resistance value of each source line block resistor is Rc;

[0101] The first ends of the 0th to Yth source line bridge arms are all connected to the positive terminal of the first power supply, the second ends of the 0th to Yth source line bridge arms are all grounded, and the middle end of the 0th source line bridge arm is connected to the input terminal of the first global source line.

[0102] The bit line inter-block compensation circuit includes: the 0th to Yth bit line bridge arms connected in parallel, and Y bit line inter-block resistors; each bit line bridge arm is composed of an upper switch and a lower switch connected in series, and the connection end of the upper switch and the lower switch serves as the middle end of the bit line bridge arm. The middle ends of any two adjacent bit line bridge arms are connected through one bit line inter-block resistor, and the resistance value of each bit line inter-block resistor is Rd.

[0103] The first ends of the 0th to Yth bit line bridge arms are all connected to the positive terminal of the second power supply, the second ends of the 0th to Yth bit line bridge arms are all grounded, and the middle end of the 0th bit line bridge arm is connected to the input terminal of the first global bit line.

[0104] The first decoder is specifically used for:

[0105] When the selected storage block is the j-th storage block in any of the repositories from 0 to X, and the current mode is the first path, the upper switch of the j-th source line bridge arm is turned on, and the lower switch of the j-th bit line bridge arm is turned on; when the selected storage block is the j-th storage block in any of the repositories from 0 to X, and the current mode is the second path, the lower switch of the j-th source line bridge arm is turned on, and the upper switch of the j-th bit line bridge arm is turned on.

[0106] exist Figure 5 In this diagram, the positive terminals of the second power supply are represented as VDD1 and VDD2, respectively. The upper and lower switches of the 0th source line bridge arm are represented as QS01 and QS02, respectively. Correspondingly, the upper and lower switches of the 1st source line bridge arm are represented as QS11 and QS12, and so on. The upper and lower switches of the Yth source line bridge arm are represented as QSY1 and QSY2, respectively. Similarly, the upper and lower switches of the 0th bit line bridge arm are represented as QB01 and QB02, respectively. Correspondingly, the upper and lower switches of the 1st bit line bridge arm are represented as QB11 and QB12, and so on. The upper and lower switches of the Yth bit line bridge arm are represented as QBY1 and QBY2, respectively.

[0107] The middle ends of any two adjacent source line bridge arms are connected by a source line block inter-resistor with a resistance of Rc, and the middle ends of any two adjacent bit line bridge arms are connected by a bit line block inter-resistor with a resistance of Rd.

[0108] Based on the circuit connection relationship and the specific function of the first decoder, when the selected memory block is the j-th memory block in any of the storage repositories from 0 to X, and the current mode is the first path, the generated switch control signal is a switch control signal used to control the upper switch of the j-th source line bridge arm to turn on and control the lower switch of the j-th bit line bridge arm to turn on. In other words, for memory blocks closer to the global driver, the number of source line inter-block resistors effective on the transmission line is greater, that is, the resistance value compensated by this application is larger.

[0109] by Figure 6a For example, if the first decoder receives the address of the 0th memory block and the current path mode is P2AP, then the first decoder will control the upper switch of the 0th source line bridge arm to turn on and control the lower switch of the 0th bit line bridge arm to turn on, that is, control... Figure 6a With QS01 and QB02 turned on and the rest turned off, the signal can start from the positive terminal of the first power supply, pass through QS01, flow through the selected MTJ memory cell, and then to ground via QB02. In this example, since the 0th memory block is the farthest from the global driver, no compensation is required.

[0110] and Figure 6a In another example, if the first decoder receives the address of the Yth memory block and the current path mode is P2AP, then the first decoder will control the upper switch of the Yth source line bridge arm to turn on and control the lower switch of the Yth bit line bridge arm to turn on, that is, control... Figure 6a With QSY1 and QBY2 turned on and the rest turned off, the signal can start from the positive terminal of the first power supply, pass through QSY1 and Y resistors (Rc), flow through the selected MTJ memory cell, pass through Y resistors (Rd), and then to ground via QBY2. In this example, because the Yth memory block is closest to the global driver, the required compensation resistance value is the largest.

[0111] The second path pattern corresponds to the first path pattern; please refer to [link / reference]. Figure 6b .

[0112] Figure 6b In one example, if the first decoder receives the address of memory block 0 and the current path mode is AP2P, then the first decoder will control the lower switch of source line bridge arm 0 to turn on and the upper switch of bit line bridge arm 0 to turn on, i.e., control... Figure 6a With QS02 and QB01 turned on and the rest turned off, the signal can travel from the positive terminal of the second power supply, through QB01, through the selected MTJ memory cell, and then to ground via QS02. In this example, since the 0th memory block is the farthest from the global driver, no compensation is required.

[0113] and Figure 6b In another example, if the first decoder receives the address of the Yth memory block and the current path mode is AP2P, then the first decoder will control the lower switch of the Yth source line bridge arm to turn on and control the upper switch of the Yth bit line bridge arm to turn on, that is, control... Figure 6b With QSY2 and QBY1 turned on and the rest turned off, the signal can start from the positive terminal of the second power supply, pass through QBY1 and Y resistors (Rd), flow through the selected MTJ memory cell, pass through Y resistors (Rc), and then to ground via QSY2. In this example, because the Yth memory block is closest to the global driver, it requires the largest compensation resistance value.

[0114] The switching types of the upper and lower switching transistors in each bridge arm can be various, such as NMOS transistors, PMOS transistors, transmission gates, and transistors, and can be set as needed. For example, in a specific scenario, the upper switching transistors of each bridge arm are set to PMOS transistors, and the lower switching transistors of each bridge arm are set to NMOS transistors. The drains of the PMOS transistors in each bridge arm are connected to the drains of the NMOS transistors. The sources of each PMOS transistor are connected to the corresponding power supply terminal, and the sources of each NMOS transistor are grounded. Furthermore, typically, all PMOS transistors and NMOS transistors have the same model and dimensions.

[0115] In this specific embodiment of the present application, the source line block compensation circuit is realized by using the parallel arrangement of the 0th to Yth source line bridge arms and the Y source line block inter-resistors, and the bit line block compensation circuit is realized by using the parallel arrangement of the 0th to Yth bit line bridge arms and the Y bit line block inter-resistors. The circuit structure is simple and clear, and the reliability is high.

[0116] In one specific embodiment of the present invention, the source line parasitic resistance value in a single memory block is determined by the parameter information of the source line and the number of memory cells divided in a single memory block.

[0117] The parasitic resistance value of the bit line in a single memory block is determined by the parameter information of the bit line and the number of memory cells in the single memory block.

[0118] In this implementation, considering that the parasitic resistance value of a single memory cell can be determined using the parameter information of the source line, multiplying this value by the number of memory cells in a single memory block easily yields the parasitic resistance value of the source line in that single memory block, i.e., the value of Rc. Similarly, the parasitic resistance value of a single memory cell can be determined using the parameter information of the bit line, multiplying this value by the number of memory cells in a single memory block easily yields the parasitic resistance value of the bit line in that single memory block, i.e., the value of Rd. The parameter information of the source line should include the source line length, width, thickness, and resistivity in a single memory block, and the same applies to the bit line.

[0119] In one specific embodiment of the present invention, both the source line block compensation circuit and the bit line block compensation circuit are integrated in the global driver.

[0120] In this embodiment, considering that this application only needs to set up one source line inter-block compensation circuit and one bit line inter-block compensation circuit to perform compensation between storage blocks of each repository in the 0th to Xth repository, the source line inter-block compensation circuit and the bit line inter-block compensation circuit can be integrated into the global driver, thereby facilitating the routing of the source line inter-block compensation circuit and the bit line inter-block compensation circuit. Figure 3The In_Bank_Compensation means that both the source line inter-block compensation circuit and the bit line inter-block compensation circuit are integrated into the global driver.

[0121] In one specific embodiment of the present invention, it may further include: source line compensation resistors from the (X+2)th to the (X+Z)th bit line compensation resistors;

[0122] The source line compensation resistor is connected in series on the source line branch of the storage a, the bit line compensation resistor is connected in series on the bit line branch of the storage a, and the resistance value of the source line compensation resistor is Ra2×(aX-1), and the resistance value of the bit line compensation resistor is Rb2×(aX-1).

[0123] The X+1 to X+Z repositories share the second global source line and the second global bit line of the memory, and the physical distance between the line and the global driver in the memory structure body decreases from the X+1 repository to the X+Z repository.

[0124] Where X and Z are both positive integers, a is a positive integer and X+2≤a≤X+Z, Ra2 represents the parasitic resistance value on the second global source line between two adjacent repositories, and Rb2 represents the parasitic resistance value on the second global bit line between two adjacent repositories.

[0125] In the foregoing embodiments of this application, the 0th to Xth repositories share the first global source line and the first global bit line of the memory. In this embodiment, considering that the memory may undergo processes such as... Figure 7 The symmetrical setup shown means that the X+1 to X+Z repositories share the second global source line and the second global bit line of the memory, thus connecting to the global driver. For the X+1 to X+Z repositories, this application can also set the X+2 to X+Z source line compensation resistors and the X+2 to X+Z bit line compensation resistors to achieve the corresponding compensation.

[0126] Ra2 represents the parasitic resistance value on the second global source line between two adjacent repositories, and Rb2 represents the parasitic resistance value on the second global bit line between two adjacent repositories. Of course, in general, Ra2 is equal to Ra, and Rb2 is equal to Rb.

[0127] The physical distance between the (X+1)th repository and the global driver is the farthest, so no compensation is needed. The physical distance between the (X+2)th repository and the global driver is the second farthest; therefore, a (X+2)th source line compensation resistor with a value of Ra2 is connected in series on the source line branch of the (X+2)th repository. Similarly, a (X+3)th source line compensation resistor with a value of Ra2×2 is connected in series on the source line branch of the (X+3)th repository. And so on. The physical distance between the (X+Z)th repository and the global driver is the shortest; therefore, a (X+Z)th source line compensation resistor with a value of Ra2×(aX-1) is connected in series on the source line branch of the (X+Z)th repository. The bit lines are treated similarly to the source lines.

[0128] The number of repositories for the second global source line and the second global bit line in the shared memory can be set as needed, that is, the value of Z can be set as needed. This application's... Figure 7 For easier viewing, the values ​​of X and Z are set to 1 and 2 respectively. Figure 7 The second global source line and the second global bit line are represented as 2_GSL and 2_GBL, respectively.

[0129] In one specific embodiment of the present invention, for each of the X+1 to X+Z repositories, compensation between storage blocks can also be performed.

[0130] Specifically, when the memory also includes inter-block compensation circuitry and a first decoder;

[0131] The first decoder can also be used to: when any storage block in any repository from the X+1 to the X+Z repository is selected, control the resistance value of the inter-block compensation circuit based on the address of the selected storage block to perform inter-block parasitic resistance compensation.

[0132] Similar to the aforementioned implementation method, in this implementation method, for each repository in the X+1 to X+Z repositories, compensation between storage blocks is also performed. The specific principle is the same as above, and will not be explained further here.

[0133] It should be emphasized that in this embodiment, the inter-block compensation circuit and the first decoder mentioned above are used to achieve compensation between storage blocks of any of the storage blocks in the X+1 to X+Z storage repositories. This is because cost savings are taken into account, and therefore the devices are reused. In other embodiments, corresponding inter-block compensation circuits and decoders can be configured for the X+1 to X+Z storage repositories as needed, without affecting the implementation of the present invention.

[0134] In practical applications, each of the X+1 to X+Z repositories may also include storage blocks 0 to Y, and in any repository, the physical distance between the storage block 0 and the global drive decreases from the storage block 0 to the storage block Y in that repository.

[0135] When the inter-block compensation circuit is specifically composed of a source line inter-block compensation circuit and a bit line inter-block compensation circuit, the source line inter-block compensation circuit can be connected to the input terminal of the second global source line, and the bit line inter-block compensation circuit can be connected to the input terminal of the second global bit line.

[0136] The first decoder can also be specifically used for:

[0137] When the selected storage block is the j-th storage block in any of the storage repositories from X+1 to X+Z, and the current mode is the first path, the resistance of the source line inter-block compensation circuit is controlled to be Rc×j, and the resistance of the bit line inter-block compensation circuit is controlled to be Rd×j, and the control current flows from the source line inter-block compensation circuit to the bit line inter-block compensation circuit.

[0138] When the selected storage block is the j-th storage block in the X+1 to X+Z storage repositories, and the current mode is the second path, the resistance of the source line inter-block compensation circuit is controlled to be Rc×j, the resistance of the bit line inter-block compensation circuit is controlled to be Rd×j, and the control current flows from the bit line inter-block compensation circuit to the source line inter-block compensation circuit.

[0139] Where Y is a positive integer, j is an integer and 0≤j≤Y, Rc represents the source line parasitic resistance value in a single memory block, and Rd represents the bit line parasitic resistance value in a single memory block.

[0140] The memory in this application can typically be an MRAM memory, but in other cases it can also be a memory based on resistive memory cells, a resistive variable memory, or a phase-change memory, etc.

[0141] By applying the technical solution provided in this invention, different sizes of source line compensation resistors and bit line compensation resistors are set to compensate for the parasitic resistance of different memory repositories, thereby ensuring that memory repositories in different address segments can receive appropriate voltage values ​​and thus guaranteeing memory reliability. Specifically, in the solution of this application, source line compensation resistors from the first to the Xth and bit line compensation resistors from the first to the Xth are set. The 0th to Xth repositories share the first global source line and the first global bit line of the memory. From the 0th to the Xth repositories, the physical distance between the lines and the global drivers in the main memory structure decreases. Therefore, in this application, the i-th source line compensation resistor is connected in series on the source line branch of the i-th repository, and the i-th bit line compensation resistor is connected in series on the bit line branch of the i-th repository. The resistance value of the i-th source line compensation resistor is Ra×i, and the resistance value of the i-th bit line compensation resistor is Rb×i. That is, the closer to the global driver, the larger the resistance values ​​of the source line compensation resistor and the bit line compensation resistor are. Conversely, the farther away from the global driver, the larger the existing parasitic resistance on the line, and therefore the smaller the compensation resistance value is set. As can be seen, by setting source line compensation resistors and bit line compensation resistors of different sizes to compensate for the parasitic resistance of different memory repositories, the equivalent resistance between the repositories in different address segments and the global driver is consistent. This ensures that repositories in different address segments receive consistent voltage values, preventing voltage deviations in repositories in near-end address segments. Therefore, the solution in this application effectively guarantees the reliability of the memory. Furthermore, this application only requires setting source line compensation resistors from the 1st to the Xth and bit line compensation resistors from the 1st to the Xth to achieve parasitic resistance compensation between repositories from the 0th to the Xth. The solution is simple to implement, low in cost, and requires minimal hardware modifications to the memory.

[0142] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0143] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0144] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A memory, characterized in that, include: The main body of the memory structure includes the first to the Xth source line compensation resistors and the first to the Xth bit line compensation resistors. The i-th source line compensation resistor is connected in series on the source line branch of the i-th storage unit, and the i-th bit line compensation resistor is connected in series on the bit line branch of the i-th storage unit. The resistance value of the i-th source line compensation resistor is Ra×i, and the resistance value of the i-th bit line compensation resistor is Rb×i. Repositories 0 to X share the first global source line and the first global bit line of the memory, and the physical distance between the line and the global driver in the main body of the memory structure decreases from repository 0 to repository X. Where X is a positive integer, i is a positive integer and 1≤i≤X, Ra represents the parasitic resistance value on the first global source line between two adjacent repositories, and Rb represents the parasitic resistance value on the first global bit line between two adjacent repositories. It also includes: source line compensation resistors from X+2 to X+Z, and bit line compensation resistors from X+2 to X+Z; The source line compensation resistor is connected in series on the source line branch of the storage a, the bit line compensation resistor is connected in series on the bit line branch of the storage a, and the resistance value of the source line compensation resistor is Ra2×(aX-1), and the resistance value of the bit line compensation resistor is Rb2×(aX-1). The X+1 to X+Z repositories share the second global source line and the second global bit line of the memory, and the physical distance between the lines and the global drivers in the main body of the memory structure decreases from the X+1 repository to the X+Z repository. Where X and Z are both positive integers, a is a positive integer and X+2≤a≤X+Z, Ra2 represents the parasitic resistance value on the second global source line between two adjacent repositories, and Rb2 represents the parasitic resistance value on the second global bit line between two adjacent repositories.

2. The memory according to claim 1, characterized in that, Also includes: Inter-block compensation circuit and first decoder; The first decoder is configured to: when any storage block in any repository from repository 0 to repository X is selected, control the resistance value of the inter-block compensation circuit based on the address of the selected storage block to perform inter-block parasitic resistance compensation.

3. The memory according to claim 2, characterized in that, The inter-block compensation circuit includes a source line inter-block compensation circuit disposed on the first global source line and a bit line inter-block compensation circuit disposed on the first global bit line. The first decoder is specifically used for: When any storage block in any repository from repository 0 to repository X is selected, the resistance value of the source line inter-block compensation circuit is controlled based on the address of the selected storage block, according to the rule that the closer the physical distance between the storage block and the global driver, the greater the resistance value of the source line inter-block compensation circuit; and the resistance value of the bit line inter-block compensation circuit is controlled according to the rule that the closer the physical distance between the storage block and the global driver, the greater the resistance value of the bit line inter-block compensation circuit.

4. The memory according to claim 3, characterized in that, Each of the 0th to Xth repositories includes the 0th to Yth storage blocks, and in any repository, the physical distance between the line and the global driver decreases from the 0th storage block to the Yth storage block in that repository; the source line inter-block compensation circuit is connected to the first power supply positive terminal and the input terminal of the first global source line, and the bit line inter-block compensation circuit is connected to the second power supply positive terminal and the input terminal of the first global bit line; The first decoder is specifically used for: When the selected storage block is the j-th storage block in any of the repositories from 0 to X, and the current mode is the first path, the resistance of the source line inter-block compensation circuit is controlled to be Rc×j, the resistance of the bit line inter-block compensation circuit is controlled to be Rd×j, and the current is controlled to flow from the source line inter-block compensation circuit to the bit line inter-block compensation circuit; when the selected storage block is the j-th storage block in any of the repositories from 0 to X, and the current mode is the second path, the resistance of the source line inter-block compensation circuit is controlled to be Rc×j, the resistance of the bit line inter-block compensation circuit is controlled to be Rd×j, and the current is controlled to flow from the bit line inter-block compensation circuit to the source line inter-block compensation circuit. Where Y is a positive integer, j is an integer and 0≤j≤Y, Rc represents the source line parasitic resistance value in a single memory block, and Rd represents the bit line parasitic resistance value in a single memory block.

5. The memory according to claim 4, characterized in that, The source line parasitic resistance value in a single memory block is determined by the parameter information of the source line and the number of memory cells in the single memory block. The parasitic resistance value of the bit line in a single memory block is determined by the parameter information of the bit line and the number of memory cells in the single memory block.

6. The memory according to claim 4, characterized in that, The source line block compensation circuit includes: the 0th to the Yth source line bridge arms arranged in parallel, and Y source line block resistors; each source line bridge arm is composed of an upper switch and a lower switch connected in series, and the connection end of the upper switch and the lower switch serves as the middle end of the source line bridge arm. The middle ends of any two adjacent source line bridge arms are connected through one source line block resistor, and the resistance value of each source line block resistor is Rc. The first ends of the 0th to Yth source line bridge arms are all connected to the positive terminal of the first power supply, the second ends of the 0th to Yth source line bridge arms are all grounded, and the middle end of the 0th source line bridge arm is connected to the input terminal of the first global source line. The bit line inter-block compensation circuit includes: the 0th to the Yth bit line bridge arms arranged in parallel, and Y bit line inter-block resistors; each bit line bridge arm is composed of an upper switch and a lower switch connected in series, and the connection end of the upper switch and the lower switch serves as the middle end of the bit line bridge arm. The middle ends of any two adjacent bit line bridge arms are connected through one bit line inter-block resistor, and the resistance value of each bit line inter-block resistor is Rd. The first ends of the 0th to Yth bit line bridge arms are all connected to the positive terminal of the second power supply, the second ends of the 0th to Yth bit line bridge arms are all grounded, and the middle end of the 0th bit line bridge arm is connected to the input terminal of the first global bit line. The first decoder is specifically used to: when the selected storage block is the j-th storage block in any of the 0 to X storage repositories, and the current mode is the first path mode, control the upper switch of the j-th source line bridge arm to be turned on, and control the lower switch of the j-th bit line bridge arm to be turned on; when the selected storage block is the j-th storage block in any of the 0 to X storage repositories, and the current mode is the second path mode, control the lower switch of the j-th source line bridge arm to be turned on, and control the upper switch of the j-th bit line bridge arm to be turned on.

7. The memory according to claim 3, characterized in that, Both the source line block compensation circuit and the bit line block compensation circuit are integrated in the global driver.

8. The memory according to claim 1, characterized in that, The parasitic resistance value on the first global source line between two adjacent repositories is the parasitic resistance value determined by the parameter information of the first global source line; The parasitic resistance value on the first global bit line between two adjacent repositories is the parasitic resistance value determined by the parameter information of the first global bit line.

9. The memory according to claim 1, characterized in that, The first end of the i-th source line compensation resistor serves as the connection point between the source line main branch of the i-th storage repository and the first global source line, and the second end of the i-th source line compensation resistor is connected to the start switch on the source line main branch of the i-th storage repository. The first end of the i-th bit line compensation resistor serves as the connection point between the bit line main branch of the i-th storage repository and the first global bit line, and the second end of the i-th bit line compensation resistor is connected to the start switch on the bit line main branch of the i-th storage repository.

10. The memory according to claim 1, characterized in that, When the memory also includes an inter-block compensation circuit and a first decoder; The first decoder is used to: when any storage block in any repository from the (X+1)th to the (X+Z)th repository is selected, control the resistance value of the inter-block compensation circuit based on the address of the selected storage block to perform inter-block parasitic resistance compensation.

11. The memory according to any one of claims 1 to 10, characterized in that, The memory is an MRAM memory.

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