Data read / write method, data read method, three-dimensional memory, and electronic device

Abstract

The application provides a data read-write method, a data reading method, a three-dimensional memory and an electronic device. The data read-write method comprises the following steps: a logic chip determines first write data; the logic chip compresses the first write data according to sample data to obtain a redundancy code; the bit difference between the first write data and the sample data is within a preset range; the redundancy code and the storage address of the sample data are stored in a redundancy storage area of a storage chip; and the logic chip and the storage chip are three-dimensionally integrated. The method of the application can realize high compression rate, reduce the delay of memory access data, and reduce the power consumption of a CPU. In addition, when the capacity of the cache area is insufficient, the method of the application can transfer at least part of the data, expand the storage capacity, and reduce the CPU overhead.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a data read / write method, a data reading method, a three-dimensional memory, and an electronic device. Background Technology

[0002] like Figure 1 As shown, in existing technologies, a compression / decompression module is introduced between the processor's (e.g., CPU's) cache memory and external memory (e.g., DDR). This module is connected to the cache memory via a multi-channel bus and to the external memory via a single-channel bus. When writing data, the compression / decompression module compresses the data, and the compressed data is stored in the DRAM. When reading data, the compressed data is read from the DRAM, decompressed by the compression / decompression module, and then sent back to the cache memory. This structure, by introducing a compression / decompression module on the CPU side, increases CPU power consumption and memory access latency. Summary of the Invention

[0003] This invention provides a data read / write method, a data reading method, a three-dimensional memory, and an electronic device, which can achieve a high compression rate, reduce the latency of accessing memory data, and reduce the power consumption of the CPU.

[0004] To solve the above-mentioned technical problems, the first technical solution provided by the present invention is: to provide a data read and write method, the method comprising: a logic chip determining first write data; the logic chip compressing the first write data according to sample data to obtain a redundancy code; the bit difference between the first write data and the sample data being within a preset range; storing the redundancy code and the storage address of the sample data in the redundant storage area of ​​the storage chip, wherein the logic chip and the storage chip are three-dimensionally integrated.

[0005] The method further includes: the logic chip receiving second write data; storing the sample data in the second write data into the sample storage area of ​​the storage chip; and writing the remaining data in the second write data other than the sample data into the cache area of ​​the logic chip.

[0006] Before the logic chip determines the first write data, the process includes: determining whether the available storage space of the logic chip's cache is greater than a threshold; if not, determining at least a portion of the data in the cache as the first write data.

[0007] Before the step of the logic chip compressing the first written data according to the sample data to obtain the redundancy code, the method includes: determining whether the sample storage area of ​​the storage chip has sample data matching the first written data; if not, determining whether the first written data contains sample data, and the bit difference between the sample data in the first written data and the remaining data in the first written data is within a preset range; or, determining whether the cache area contains sample data; if the first written data or the cache area contains sample data, storing the sample data in the sample storage area of ​​the storage chip.

[0008] If the sample storage area, the first written data, and the cache area do not contain the sample data, the first written data is written to the original data storage area of ​​the storage chip.

[0009] The method further includes: receiving a read instruction; reading the sample data from the sample storage area based on the read instruction, and reading the redundant code from the redundant storage area; and obtaining the read data based on the sample data and the redundant code.

[0010] The step of the logic chip compressing the first written data according to the sample data to obtain a redundant code includes: the logic chip using an encoding / decoding module to compress the first written data according to the sample data to obtain a redundant code; the encoding / decoding module is disposed in the logic chip; wherein the encoding / decoding module includes at least one of BCH error correction algorithm and LDPC.

[0011] To solve the above-mentioned technical problems, the second technical solution provided by the present invention is: to provide a data reading method, the method comprising: receiving a reading instruction; reading sample data from the sample storage area of ​​the memory based on the reading instruction, and reading redundant code from the redundant storage area of ​​the memory; and using the encoding and decoding module in the memory to obtain the read data based on the sample data and the redundant code.

[0012] To solve the above-mentioned technical problems, the third technical solution provided by the present invention is as follows: a three-dimensional memory is provided, comprising: a logic chip; a memory chip, the memory chip including a redundant memory area; the logic chip and the memory chip are three-dimensionally integrated; wherein, the logic chip determines first write data; the first write data is compressed according to sample data to obtain a redundant code; the bit difference between the first write data and the sample data is within a preset range; and the redundant code and the storage address of the sample data are stored in the redundant memory area of ​​the memory chip.

[0013] The logic chip includes: an encoding / decoding module, which is used to calculate the redundancy code of the first written data based on the sample data, and to calculate the read data based on the sample data and the redundancy code; an address command module, which is used to receive read instructions and write instructions; and a memory controller, which is connected to the storage chip and is used to control the logic chip and the storage chip.

[0014] The storage chip further includes a raw data storage area and a sample data storage area. The raw data storage area is used to store the first written data, and the sample data storage area is used to store the sample data.

[0015] The sample storage area, the redundant storage area, and the original data storage area are located on the same storage chip; or the sample storage area, the redundant storage area, and the original data storage area are located on different storage chips.

[0016] To solve the above-mentioned technical problems, the fourth technical solution provided by the present invention is as follows: An electronic device is provided, comprising: a three-dimensional memory and a processing chip; the three-dimensional memory includes: a logic chip and a storage chip; the storage chip includes a redundant storage area; the logic chip and the storage chip are three-dimensionally integrated; wherein, the logic chip determines first write data; the first write data is compressed according to sample data to obtain a redundant code; the bit difference between the first write data and the sample data is within a preset range; the redundant code and the storage address of the sample data are stored in the redundant storage area of ​​the storage chip; the three-dimensional memory includes an interface, and the three-dimensional memory is connected to the processing chip through the interface.

[0017] The beneficial effects of this invention, unlike existing technologies, are as follows: This invention uses a logic chip to determine the first write data; the logic chip compresses the first write data based on sample data to obtain a redundancy code; the bit difference between the first write data and the sample data is within a preset range; the redundancy code and the storage address of the sample data are stored in the redundant storage area of ​​the storage chip, and the logic chip and the storage chip are three-dimensionally integrated. The method of this application eliminates the need to read data out of memory during compression, achieving a high compression ratio, reducing memory access latency, and lowering CPU power consumption. Furthermore, when the cache capacity is insufficient, the method of this application transfers at least a portion of the data, expanding storage capacity and reducing CPU overhead. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0019] Figure 1 This is a schematic diagram of the storage architecture of existing technologies;

[0020] Figure 2 This is a flowchart illustrating the first embodiment of the data read / write method of the present invention;

[0021] Figure 3 This is a flowchart illustrating a second embodiment of the data read / write method of the present invention;

[0022] Figure 4 This is a flowchart illustrating an embodiment of the data reading method of the present invention;

[0023] Figure 5 This is a schematic diagram of the structure of an embodiment of the three-dimensional memory of the present invention;

[0024] Figure 6 This is a schematic diagram of another embodiment of the three-dimensional memory of the present invention;

[0025] Figure 7 This is a schematic diagram of the structure of an embodiment of the electronic device of the present invention. Specific implementation methods

[0026] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0027] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0029] Please see Figure 2 , Figure 2 This is a flowchart illustrating the first embodiment of the data read / write method of the present invention, specifically including:

[0030] Step S11: The logic chip determines the first data to be written.

[0031] In one embodiment, the first written data is data that needs to be transferred out of the logic chip. Specifically, the data read / write method of this application is applied to a three-dimensional memory, which includes a logic chip and a memory chip, which are stacked and connected by one of the three-dimensional integration methods. For example, three-dimensional integration is achieved through through-silicon vias (TSVs) and / or hybrid bonding technology. The logic chip has a buffer area. In practical applications, when data is stored, it is preferentially stored in the buffer area. However, when the storage space in the buffer area is insufficient, the data in the buffer area needs to be cleared. The cleared data at this time is the first written data.

[0032] In one specific embodiment, it is determined whether the available storage space of the logic chip's cache is greater than a threshold. If the available space is greater than the threshold, it can continue to be used without clearing the data in the cache. If the available space is not greater than the threshold, at least a portion of the data in the cache needs to be cleared. Specifically, at least a portion of the data in the cache is determined as the first data to be written. In one embodiment, if the storage space in the cache is insufficient, the data that was first stored in the cache is determined as the first data to be written, based on the order of time. In another embodiment, if the cache space is insufficient, the data is prioritized according to the number of times it is read. Data read more frequently has higher priority, and data read less frequently has lower priority. At least a portion of the less frequently used, i.e., lower priority data is determined as the first data to be written.

[0033] Step S12: The logic chip compresses the first written data according to the sample data to obtain a redundancy code; the bit difference between the first written data and the sample data is within a preset range.

[0034] To save space, the first written data needs to be compressed during transfer. In one embodiment, the logic chip compresses the first written data based on sample data to obtain redundant codes. It should be noted that the bit difference between the first written data and the sample data is within a preset range. That is, during compression, the sample data corresponding to the first written data needs to be determined, and the relationship between the sample data and the first written data needs to satisfy the compression condition, i.e., the bit difference is within the preset range.

[0035] It should be noted that this preset range represents the error correction capability, that is, the bit difference between the data to be transferred and the sample data needs to be within the error correction capability range.

[0036] Specifically, when compressing the first written data, sample data needs to be determined. In one embodiment of this application, the logic chip determines the sample data during the process of writing data to the buffer. Specifically, the logic chip receives the second written data, determines whether the second written data contains sample data, and if so, stores the sample data in the second written data in the sample storage area of ​​the storage chip, and writes the remaining data in the second written data other than the sample data into the buffer of the logic chip. Suppose that the second write data received by the logic chip includes: 0xFF00AA55BB0000CB, 0xFF00AA55BB0000C8, 0xFF00AA55BB0000C4, and 0xFF00AA55BB0000CC. After judgment, it is found that the bit difference between 0xFF00AA55BB0000CC and 0xFF00AA55BB0000CB, 0xFF00AA55BB0000C8, and 0xFF00AA55BB0000C4 is 2 bits, which is within the preset range. At this time, 0xFF00AA55BB0000CC is determined as sample data and stored in the sample storage area of ​​the memory chip, while the remaining data is stored in the cache area. Therefore, when the storage space in the cache is insufficient, at least some of the data is determined to be the first written data. At this time, it is determined whether the sample storage area of ​​the storage chip has sample data that matches the first written data. If so, the sample data is found from the sample storage area, and the first written data is compressed based on the sample data to obtain the redundancy code.

[0037] In another embodiment of this application, if there is no matching sample data in the sample storage area, it can also be determined whether the first written data contains sample data. The bit difference between the sample data in the first written data and the remaining data in the first written data is within a preset range. Specifically, suppose the first data to be written includes 0xFF00AA55BB0000CB, 0xFF00AA55BB0000C8, 0xFF00AA55BB0000C4, and 0xFF00AA55BB0000CC. However, there is no matching sample data in the sample storage area. It is determined that 0xFF00AA55BB0000CC in the first data to be written can be used as sample data for the other data (0xFF00AA55BB0000CB, 0xFF00AA55BB0000C8, and 0xFF00AA55BB0000C4) in the first data to be written. Therefore, the other data (0xFF00AA55BB0000CB, 0xFF00AA55BB0000C8, and 0xFF00AA55BB0000C4) are compressed based on the data 0xFF00AA55BB0000CC to obtain redundant code.

[0038] Understandably, in one embodiment of this application, if the sample storage area does not contain sample data matching the first written data, it can also be determined whether the cache contains sample data. Specifically, assuming the first written data includes 0xFF00AA55BB0000CB, 0xFF00AA55BB0000C8, and 0xFF00AA55BB0000C4, and the sample storage area does not contain matching sample data, it is then determined whether the cache contains sample data. Assuming the cache contains data 0xFF00AA55BB0000CC, it can be determined that the cache contains sample data.

[0039] It should be noted that if the first write data or the cache contains sample data, the sample data is stored in the sample storage area of ​​the memory chip. If the sample storage area, the first write data, and the cache do not contain sample data, the first write data is written to the original data storage area of ​​the memory chip.

[0040] In one embodiment of this application, the logic chip uses an encoding / decoding module to compress the first written data based on the sample data to obtain a redundant code; the encoding / decoding module is disposed in the logic chip; wherein, the encoding / decoding module includes at least one of BCH error correction algorithm and LDPC.

[0041] Taking the BCH error correction algorithm as an example, the data bit width and redundancy code bit width of the BCH error correction algorithm are configurable. For example, it can be configured with a data bit width of 64 bits, a redundancy code of 14 bits, and an error correction capability of 2 bits; or it can be configured with a data bit width of 128 bits, a redundancy code of 28 bits, and an error correction capability of 4 bits. The specific configuration is not limited.

[0042] Taking the BCH error correction algorithm with a 64-bit data width, 14-bit redundancy code, and 2-bit error correction capability as an example, for the sample data 0xFF00AA55BB0000CC, it differs from the first written data 0xFF00AA55BB0000CB, 0xFF00AA55BB0000C8, and 0xFF00AA55BB0000C4 by 1 bit, which meets the error correction capability requirement. The redundancy code of the data to be transferred 0xFF00AA55BB0000CB, 0xFF00AA55BB0000C8, and 0xFF00AA55BB0000C4 is calculated using the BCH error correction algorithm. Assume that the calculated redundancy code is 0x3FEB, 0x1537, and 0x27F6.

[0043] Step S13: Store the redundant code and the storage address of the sample data in the redundant storage area of ​​the memory chip, and integrate the logic chip and the memory chip in three dimensions.

[0044] Specifically, the redundancy code and the storage address of the sample data are stored in the redundancy area of ​​the memory chip. Assuming that the storage address or index of the sample data in the sample storage area is 0x00, then 0x00 and the redundancy codes 0x3FEB, 0x1537, and 0x27F6 are stored in the redundancy area of ​​the memory chip.

[0045] In another embodiment of this application, the redundancy code (0x3FEB, 0x1537, 0x27F6) is associated with the storage address of the sample data. Assuming the storage address or index of the sample data in the sample storage area is 0x00, the association results between the redundancy code and the storage address of the sample data are (0x00, 0x3FEB), (0x00, 0x0x1537), and (0x00, 0x0x27F6). This association result is stored in the redundancy storage area of ​​the memory. Therefore, when reading the redundancy code, the storage address of the corresponding sample data can be determined, and the sample data can then be read.

[0046] In this embodiment, encoding (compression) is performed using the internal encoding / decoding module of the memory, eliminating the need to read data out of the memory. This achieves in-memory compression, resulting in a high compression ratio, reduced memory access latency, and lower CPU power consumption. Furthermore, the method of this application can expand storage capacity and reduce CPU overhead by transferring at least a portion of the data when the cache capacity is insufficient.

[0047] Please see Figure 3 , Figure 3 This is a flowchart illustrating the second embodiment of the data read / write method of the present invention. In this embodiment, steps S21 to S23 are the same as those described above. Figure 2 In the first embodiment shown, steps S11 to S13 are the same, except that this embodiment further includes the following after step S23:

[0048] Step S24: Receive read command.

[0049] Step S25: Read sample data from the sample storage area and read redundant code from the redundant storage area based on the read command.

[0050] Specifically, the read address is determined based on the read instruction; in response to the read address being the address of the sample storage area and / or the redundant storage area, sample data is read from the sample storage area, and redundant code is read from the redundant storage area. In response to the read address being the address of the original storage area, data is read from the original storage area to obtain the read data; in response to the read address being the address of the cache area, data is read from the cache area to obtain the read data.

[0051] Specifically, the read address can contain only the storage address of the sample data. Since the redundant code is associated with the storage address of the sample data, the redundant code can be obtained based on the storage address of the sample data. Of course, the read address can also contain both the storage address of the sample data and the storage address of the redundant code.

[0052] Step S26: Obtain the readout data based on the sample data and the redundant code.

[0053] After obtaining the sample data and redundant code, the readout data is obtained based on the sample data and redundant code using the BCH error correction algorithm or LDPC algorithm.

[0054] Please see him 4. Figure 4 This is a flowchart illustrating an embodiment of the data reading method of the present invention, specifically including:

[0055] Step S31: Receive read command.

[0056] Step S32: Read sample data from the sample storage area of ​​the memory based on the read instruction, and read redundant code from the redundant storage area of ​​the memory.

[0057] Step S33: Use the encoding / decoding module in the memory to obtain the read data based on the sample data and the redundant code.

[0058] Specifically, the read address is determined based on the read instruction; in response to the read address being the address of the sample storage area and / or the redundant storage area, sample data is read from the sample storage area, and redundant code is read from the redundant storage area. In response to the read address being the address of the original storage area, data is read from the original storage area to obtain the read data; in response to the read address being the address of the cache area, data is read from the cache area to obtain the read data.

[0059] Specifically, the read address can contain only the storage address of the sample data. Since the redundant code is associated with the storage address of the sample data, the redundant code can be obtained based on the storage address of the sample data. Of course, the read address can also contain both the storage address of the sample data and the storage address of the redundant code.

[0060] After obtaining the sample data and redundant code, the readout data is obtained based on the sample data and redundant code using the encoding and decoding modules in the memory, such as the BCH error correction algorithm or the LDPC algorithm.

[0061] In this embodiment, during data reading, the sample data and redundant codes are decoded using the internal encoding / decoding module of the memory to obtain the read data, eliminating the need to read the data out of the memory and then decode it. This achieves a high compression ratio, reduces memory access latency, and lowers CPU power consumption.

[0062] Please see Figure 5 This is a schematic diagram of the structure of an embodiment of the three-dimensional memory of the present invention. The three-dimensional memory includes a logic chip 62 and a memory chip 61. The memory chip 61 and the logic chip 62 are three-dimensionally integrated. Specifically, the memory chip 61 and the logic chip 62 are connected through one of the three-dimensional integration methods. For example, three-dimensional integration is achieved through through-silicon vias (TSVs) and / or hybrid bonding techniques.

[0063] The memory chip 61 includes a redundant storage area, and the logic chip 62 determines the first write data; compresses the first write data according to the sample data to obtain a redundant code; the bit difference between the first write data and the sample data is within a preset range; and stores the redundant code and the storage address of the sample data in the redundant storage area of ​​the memory chip.

[0064] In one embodiment, please refer to Figure 6 The logic chip 62 includes an encoding / decoding module, an address command module, and a memory controller. The encoding / decoding module is used to calculate the redundancy code of the first written data based on the sample data, and to calculate the read data based on the sample data and the redundancy code. The address command module is used to receive read instructions and write instructions. The memory controller is connected to the memory chip and is used to control the logic chip and the memory chip.

[0065] Specifically, the memory chip also includes a raw data storage area and a sample data storage area. The raw data storage area is used to store the first written data, and the sample data storage area is used to store sample data.

[0066] In the embodiments of this application, the memory chip 61 is provided with a raw data storage area, a sample storage area and a redundant storage area, wherein the raw data storage area, the sample storage area and the redundant storage area are all connected to the memory controller of the logic chip 62 through hybrid bonding and / or through-silicon vias.

[0067] Specifically, the memory controller of logic chip 62 determines the first write data from the cache. In one embodiment, the memory controller determines whether the available storage space in the cache of the logic chip is greater than a threshold; in response to no, the memory controller determines at least a portion of the data in the cache as the first write data.

[0068] The memory controller of logic chip 62 compresses the first written data based on the sample data to obtain a redundancy code. Specifically, the logic chip receives the second written data; the memory controller stores the sample data in the second written data into the sample storage area of ​​the memory chip; and writes the remaining data in the second written data, excluding the sample data, into the buffer area of ​​the logic chip.

[0069] Specifically, determine whether the sample storage area of ​​the memory chip contains sample data that matches the first written data;

[0070] If not, the memory controller determines whether the first written data contains sample data, and the bit difference between the sample data in the first written data and the rest of the data in the first written data is within a preset range; or, determines whether the cache contains sample data; if the first written data or the cache contains sample data, the sample data is stored in the sample storage area of ​​the memory chip.

[0071] The memory controller of logic chip 62 stores the redundant code and the storage address of the sample data in the redundant storage area of ​​the memory chip. Specifically, if the sample storage area, the first write data, and the cache area do not contain sample data, the first write data is written to the original data storage area of ​​the memory chip.

[0072] Specifically, during data writing, the address command module receives a write command and second write data from an external device, such as the CPU, via the memory IF interface. The memory controller determines whether sample data exists in the second write data. If so, the memory controller stores the sample data in the second write data into the sample storage area of ​​the memory chip and writes the remaining data in the second write data, excluding the sample data, into the cache area of ​​the logic chip. When writing data to the cache area, if the cache space is insufficient, the memory controller transfers at least a portion of the data in the cache area as the first write data to the memory chip. Specifically, the memory controller determines whether there is matching sample data in the cache area, the sample storage area, or the first write data. If so, the first write data is compressed based on the sample data to obtain a redundancy code, and the redundancy code and the storage address of the sample data are stored in the redundancy storage area. If there is no sample data in the cache area, the sample storage area, or the first write data, the first write data is stored in the original data storage area.

[0073] During data reading, the address command module receives read commands from external devices, such as the CPU, via the memory IF interface. Based on these commands, it obtains the read address. If the read address is the address of the cache, the data is retrieved from the cache. If the read address is the original data storage area, the memory controller retrieves the data from the original data storage area. If the read address is the sample storage area, the memory controller reads the sample image from the sample storage area. Since the storage address of the sample data is associated with the redundancy code, the memory controller can also retrieve the redundancy code from the redundancy area based on the read address. If the read address is both the sample storage area and the redundancy storage area, the memory controller reads the sample image from the sample storage area and retrieves the redundancy code from the redundancy area. After obtaining the sample data and the redundancy code, the encoding / decoding module decodes the data based on the sample data and the redundancy code to obtain the read data.

[0074] It should be noted that the encoding / decoding module is based on the BCH error correction algorithm or LDPC.

[0075] Understandably, after data is transferred from the cache to the memory chip, the transferred data is deleted from the cache. This utilizes the memory chip to expand storage space. Since the logic chip and memory chip are connected through one of the three-dimensional integration methods, it offers advantages such as high bandwidth and low power consumption.

[0076] In one embodiment, the sample storage area, redundant storage area, and original data storage area are located on the same memory chip. That is, a single memory chip is defined as the sample storage area, redundant storage area, and original data storage area, respectively. In another embodiment, the sample storage area, redundant storage area, and original data storage area are located on different memory chips. That is, the sample storage area, redundant storage area, and original data storage area are located on different memory chips, such as... Figure 5 The illustrated method involves three-dimensional integration onto a logic chip. It is understood that multiple memory chips can be used, corresponding to the sample storage area, redundant storage area, and original data storage area, and these chips are stacked and bonded along a direction away from the logic chip. In one feasible embodiment, the memory chips corresponding to the sample storage area, redundant storage area, and original data storage area can also be three-dimensionally integrated and then connected to the logic chip using one of the three-dimensional integration methods, without specific limitations. When multiple memory chips are three-dimensionally integrated, signal communication between the individual memory chips is achieved through through-silicon vias (TSVs).

[0077] In one embodiment, the three-dimensional memory further includes a substrate 63, and a surface of the logic chip 62 away from the memory chip 61 is connected to the substrate 63 via solder balls.

[0078] The three-dimensional memory of this application incorporates an encoding / decoding module within the memory itself. Data transfer, encoding, and decoding all occur within the memory, eliminating the need to read data out of the memory. This achieves a high compression rate, reduces memory access latency, and lowers CPU power consumption. Furthermore, the method of this application can expand storage capacity and reduce CPU overhead by transferring at least a portion of the data when the cache capacity is insufficient.

[0079] Please see Figure 7 This is a schematic diagram of the structure of an embodiment of the electronic device of the present invention. The electronic device includes a three-dimensional memory and a processing chip 64. The three-dimensional memory includes a logic chip 62 and a storage chip 61. The storage chip 61 includes a redundant storage area. The logic chip 62 and the storage chip 61 are three-dimensionally integrated. The logic chip 62 determines first write data. The first write data is compressed according to sample data to obtain a redundant code. The bit difference between the first write data and the sample data is within a preset range. The redundant code and the storage address of the sample data are stored in the redundant storage area of ​​the storage chip. The three-dimensional memory includes an interface, and the three-dimensional memory is connected to the processing chip through the interface.

[0080] Specifically, the 3D memory includes an interface memory IF, which connects to the processing chip 64.

[0081] The electronic device of this application incorporates an encoding / decoding module within its memory. Data transfer, encoding, and decoding all occur within the memory, eliminating the need to read data out of the memory. This achieves high compression rates, reduces memory access latency, and lowers CPU power consumption. Furthermore, the method of this application can expand storage capacity and reduce CPU overhead by transferring at least a portion of the data when the cache capacity is insufficient.

[0082] In the several embodiments provided in this application, it should be understood that the disclosed methods and apparatus can be implemented by other methods. For example, the apparatus implementation methods described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0083] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this implementation method according to actual needs.

[0084] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0085] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a system server, or a network device, etc.) or a processor to execute all or part of the steps of the various embodiments of this application.

[0086] The above are merely implementation methods of the present invention and do not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A data read / write method, characterized in that, The method includes: The logic chip determines the first data to be written; The logic chip compresses the first written data based on the sample data to obtain a redundancy code; the bit difference between the first written data and the sample data is within a preset range. The redundant code and the storage address of the sample data are stored in the redundant storage area of ​​the storage chip, and the logic chip and the storage chip are three-dimensionally integrated; Before the step of the logic chip compressing the first written data according to the sample data to obtain the redundancy code, the following steps are included: Determine whether the sample storage area of ​​the memory chip contains sample data that matches the first written data; If not, determine whether the first written data contains sample data, and whether the bit difference between the sample data in the first written data and the rest of the data in the first written data excluding the sample data is within a preset range; or, determine whether the cache of the logic chip contains sample data. If the first written data or the cache contains sample data, the sample data is stored in the sample storage area of ​​the storage chip.

2. The method according to claim 1, characterized in that, The method further includes: The logic chip receives the second write data and determines whether the second write data contains sample data. If so, the sample data in the second written data is stored in the sample storage area of ​​the storage chip; The remaining data in the second write data, excluding the sample data, is written into the cache area of ​​the logic chip; the bit difference between the sample data in the second write data and the remaining data in the second write data, excluding the sample data, is within a preset range.

3. The method according to claim 1, characterized in that, Before the logic chip determines the first write data, the following steps are included: Determine whether the available storage space of the cache area of ​​the logic chip is greater than a threshold; If no response is received, at least a portion of the data in the cache is identified as the first written data.

4. The method according to claim 1, characterized in that, If the sample storage area, the first written data, and the cache area do not contain the sample data, the first written data is written to the original data storage area of ​​the storage chip.

5. The method according to any one of claims 1 to 4, characterized in that, The method further includes: Receive read command; Based on the read instruction, the sample data is read from the sample storage area, and the redundant code is read from the redundant storage area; The readout data is obtained based on the sample data and the redundant code.

6. The method according to any one of claims 1 to 4, characterized in that, The step of the logic chip compressing the first written data according to the sample data to obtain the redundancy code includes: The logic chip uses an encoding / decoding module to compress the first written data based on the sample data to obtain a redundant code; the encoding / decoding module is located in the logic chip. The encoding / decoding module includes at least one of BCH error correction algorithm and LDPC.

7. A three-dimensional memory, characterized in that, include: Logic chip; A memory chip, the memory chip including a redundant memory area; the logic chip is three-dimensionally integrated with the memory chip; The logic chip determines first write data; the logic chip compresses the first write data based on sample data to obtain a redundancy code; the bit difference between the first write data and the sample data is within a preset range; the redundancy code and the storage address of the sample data are stored in the redundancy storage area of ​​the storage chip; the logic chip further determines whether the sample storage area of ​​the storage chip has sample data matching the first write data; if not, it determines whether the first write data contains sample data, and the bit difference between the sample data in the first write data and the rest of the data in the first write data is within a preset range; or, it determines whether the buffer area of ​​the logic chip contains sample data; if the first write data or the buffer area contains sample data, the sample data is stored in the sample storage area of ​​the storage chip.

8. The three-dimensional memory according to claim 7, characterized in that, The logic chip includes: The encoding and decoding module is used to calculate the redundancy code of the first written data based on the sample data, and to calculate the read data based on the sample data and the redundancy code. The address command module is used to receive read and write commands. A memory controller, connected to the memory chip, is used to control the logic chip and the memory chip.

9. The three-dimensional memory according to any one of claims 7 to 8, characterized in that, The storage chip further includes a raw data storage area and a sample storage area. The raw data storage area is used to store the first written data, and the sample storage area is used to store the sample data.

10. The three-dimensional memory according to claim 9, characterized in that, The sample storage area, the redundant storage area, and the original data storage area are located on the same storage chip; or The sample storage area, the redundant storage area, and the original data storage area are located on different storage chips.

11. An electronic device, characterized in that, include: Three-dimensional memory and processing chips; The three-dimensional memory includes: a logic chip and a memory chip; The memory chip includes a redundant storage area; the logic chip is three-dimensionally integrated with the memory chip; wherein, the logic chip determines first write data; the logic chip compresses the first write data according to sample data to obtain a redundant code; the bit difference between the first write data and the sample data is within a preset range; the redundant code and the storage address of the sample data are stored in the redundant storage area of ​​the memory chip; the logic chip further determines whether the sample storage area of ​​the memory chip has sample data matching the first write data; if not, it determines whether the first write data contains sample data, and the bit difference between the sample data in the first write data and the rest of the data in the first write data excluding the sample data is within a preset range; or, it determines whether the cache area of ​​the logic chip contains sample data; if the first write data or the cache area contains sample data, the sample data is stored in the sample storage area of ​​the memory chip; The three-dimensional memory includes an interface, through which the three-dimensional memory is connected to the processing chip.

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