Method for fabricating gallium oxide-based power transistor with low ohmic contact resistance and device

Abstract

The application provides a manufacturing method of a low-ohmic contact gallium oxide power transistor and a device. 3 The UID layer is then grown on the Fe-doped beta-Ga2O3 substrate by using an epitaxial device, a lightly-doped channel layer is then grown on the UID layer, and then a Si-doped GaN layer is grown by using the epitaxial device; since the spontaneous polarization effect of GaN and the doping are relatively easy, a heavily-doped GaN layer can be easily obtained, the GaN layer is annealed in an oxygen atmosphere at high temperature to form a heavily-doped Ga2O3 cap layer, so that the lattice mismatch between the two is reduced, and the cap layer serves as an ohmic contact layer, then a Ti / Au metal stack is deposited on the cap layer to form a good ohmic contact, so that the on-resistance of the device is reduced, and then the gate is manufactured and electrodes are led out to form the low-ohmic contact gallium oxide power transistor.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device fabrication technology, specifically relating to a method and device for fabricating a gallium oxide-based power transistor with low ohmic contact resistance. Background Technology

[0002] Due to its ultra-wide bandgap and high breakdown field strength, β-Ga₂O₃ materials exhibit high voltage withstand capability and high power output, making them promising for applications in power electronics. In recent years, this has attracted numerous scholars to research β-Ga₂O₃ crystal materials and power devices.

[0003] However, due to the high bandgap of gallium oxide, current technologies commonly use ohmic region ion implantation to heavily dope it with Si ions. This process is technically challenging, making it difficult to guarantee the quality of the ohmic contacts, resulting in high on-resistance of the device. β-Ga₂O₃ fabricated using this process typically has an on-resistance higher than 15 mΩ•cm. 2 This limits the application of gallium oxide power transistors in the field of power electronics. Therefore, fabricating transistors that balance high breakdown voltage and low on-resistance remains a difficulty and challenge for gallium oxide power transistors. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a method and device for fabricating a gallium oxide-based power transistor with low ohmic contact resistance, thereby solving the problem of high ohmic contact resistance in current gallium oxide power transistors. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] In a first aspect, the present invention provides a method for fabricating a gallium oxide-based power transistor with low ohmic contact resistance, comprising:

[0006] Step 1: Obtain a β-Ga2O3 substrate;

[0007] Step 2: Grow a UID (Unintentionally Doped) layer on the β-Ga2O3 substrate;

[0008] Step 3: Grow a lightly doped β-Ga2O3 layer on the UID layer as a channel layer;

[0009] Step 4: Grow a heavily doped GaN cap layer on the channel layer and anneal it in an oxygen atmosphere to obtain a heavily doped Ga2O3 cap layer.

[0010] Step 5: Etch the heavily doped Ga2O3 cap layer in areas other than the ohmic region, while retaining the heavily doped Ga2O3 cap layer in the ohmic region;

[0011] Step 6: Deposit a Ti / Au metal stack on top of the heavily doped Ga2O3 cap layer in the ohmic region, and perform thermal annealing to form the source electrode and drain electrode of the ohmic contact;

[0012] Step 7: Grow an Al2O3 layer as a dielectric layer in the active region outside the ohmic region, and etch away the dielectric layer in the source and drain regions;

[0013] Step 8: Deposit a Ni / Au stack as gate metal on the dielectric layer and fabricate interconnect leads to complete the fabrication of a gallium oxide-based power transistor with low ohmic contact resistance.

[0014] Optionally, the UID layer has a thickness of 100~500nm and a carrier concentration of 1×10⁻⁶. 14 cm -3 ~1×10 16 cm -3 The channel layer has a thickness of 200~600nm and a doping concentration of 1×10⁻⁶. 17 cm -3 ~5×10 18 cm -3 The thickness of the heavily doped Ga2O3 cap layer is 10~50 nm, and the doping concentration is 1×10⁻⁶. 19 cm -3 ~1×10 21 cm -3 The thickness of the dielectric layer is 10~30nm.

[0015] Optionally, step 4 includes:

[0016] Step 4-1: Epitaxially grow a Si-doped GaN layer above the channel layer;

[0017] Step 4-2: Place the material formed in step 4-1 into an annealing furnace and anneal it in an oxygen atmosphere to transform the heavily doped GaN cap layer into a heavily doped polycrystalline Ga2O3 cap layer.

[0018] Optionally, step 5 includes:

[0019] The heavily doped Ga2O3 cap layer in areas other than the ohmic region is etched to a depth of 10-50 nm, while retaining the heavily doped Ga2O3 cap layer in the ohmic region.

[0020] Optionally, step 6 includes:

[0021] Step 6-1: Evaporate Ti / Au metal stacks with thicknesses of 20 / 200 nm on top of the heavily doped Ga2O3 cap layer in the ohmic region;

[0022] Step 6-2: After evaporating the Ti / Au metal stack, perform rapid thermal annealing and alloy the evaporated Ti / Au metal to complete the fabrication of the source electrode and drain electrode.

[0023] Optionally, step 8 includes:

[0024] Step 8-1: Deposit Ni / Au metal stacks on top of the dielectric layer with thicknesses of 45 / 400 nm, respectively;

[0025] Step 8-2: Etch the Al2O3 dielectric layer above the Ni / Au metal stack, with an etching thickness of 10-30 nm;

[0026] Step 8-3: Deposit interconnect metal and bring out the source electrode, drain electrode, and gate electrode.

[0027] Secondly, the present invention provides a gallium oxide-based power transistor device with low ohmic contact resistance, which is fabricated using the method for fabricating a gallium oxide-based power transistor with low ohmic contact resistance described in the first aspect.

[0028] The beneficial effects of this invention are:

[0029] This invention provides a method and device for fabricating a low-ohmic contact gallium oxide power transistor. The method involves growing a β-Ga2O3 UID layer on an Fe-doped β-Ga2O3 substrate using an epitaxial device, followed by a lightly doped channel layer on top of the UID layer, and then a Si-doped GaN layer. Due to the spontaneous polarization effect of GaN and its relatively easy doping, a heavily doped GaN layer is readily obtained. This invention anneals the GaN layer in an oxygen atmosphere at high temperature to form a heavily doped Ga2O3 cap layer, reducing the lattice mismatch between the two layers and serving as an ohmic contact layer. A good ohmic contact is then formed by depositing a Ti / Au metal stack on top of this cap layer, thereby reducing the on-resistance of the device. Finally, the gate is fabricated and electrodes are brought out to form a low-ohmic contact gallium oxide power transistor.

[0030] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0031] Figure 1 This is a flowchart illustrating a method for fabricating a gallium oxide-based power transistor with low ohmic contact resistance, as provided in an embodiment of the present invention.

[0032] Figure 2 This is a schematic diagram of the structure of a gallium oxide-based power transistor with low ohmic contact resistance provided in an embodiment of the present invention;

[0033] Figure 3This is a schematic diagram of the manufacturing process of the device of the present invention provided in an embodiment of the present invention. Detailed Implementation

[0034] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0035] like Figure 1 As shown, the method for fabricating a gallium oxide-based power transistor with low ohmic contact resistance provided by the present invention includes:

[0036] Step 1: Obtain a Fe-doped β-Ga2O3 substrate;

[0037] Step 2: Grow a UID layer on the β-Ga2O3 substrate;

[0038] Step 3: Grow a lightly doped β-Ga2O3 layer on the UID layer as a channel layer;

[0039] Step 4: Grow a heavily doped GaN cap layer on the channel layer and anneal it in an oxygen atmosphere to obtain a heavily doped Ga2O3 cap layer.

[0040] As an optional embodiment of the present invention, step 4 includes:

[0041] Step 4-1: Epitaxially grow a Si-doped GaN layer above the channel layer;

[0042] Step 4-2: Place the material formed in step 4-1 into an annealing furnace and anneal it in an oxygen atmosphere to transform the heavily doped GaN cap layer into a heavily doped polycrystalline Ga2O3 cap layer.

[0043] Step 5: Etch the heavily doped Ga2O3 cap layer in areas other than the ohmic region, while retaining the heavily doped Ga2O3 cap layer in the ohmic region;

[0044] This step involves etching the heavily doped Ga2O3 cap layer in areas other than the ohmic region, with an etching depth of 10-50 nm, while retaining the heavily doped Ga2O3 cap layer in the ohmic region.

[0045] Step 6: Deposit a Ti / Au metal stack on top of the heavily doped Ga2O3 cap layer in the ohmic region, and perform thermal annealing to form the source electrode and drain electrode of the ohmic contact;

[0046] As an optional embodiment of the present invention, step 6 includes:

[0047] Step 6-1: Evaporate Ti / Au metal stacks with thicknesses of 20 / 200 nm on top of the heavily doped Ga2O3 cap layer in the ohmic region;

[0048] Step 6-2: After evaporating the Ti / Au metal stack, perform rapid thermal annealing and alloy the evaporated Ti / Au metal to complete the fabrication of the source electrode and drain electrode.

[0049] Step 7: Grow an Al2O3 layer as a dielectric layer in the active region outside the ohmic region, and etch away the dielectric layer in the source and drain regions;

[0050] Step 8: Deposit a Ni / Au stack as gate metal on the dielectric layer and fabricate interconnect leads to complete the fabrication of a gallium oxide-based power transistor with low ohmic contact resistance.

[0051] As an optional embodiment of the present invention, step 8 includes:

[0052] Step 8-1: Deposit Ni / Au metal stacks on top of the dielectric layer with thicknesses of 45 / 400 nm, respectively;

[0053] Step 8-2: Etch the Al2O3 dielectric layer above the Ni / Au metal stack, with an etching thickness of 10-30 nm;

[0054] Step 8-3: Deposit interconnect metal and bring out the source electrode, drain electrode, and gate electrode.

[0055] The UID layer has a thickness of 100~500nm and a carrier concentration of 1×10⁻⁶. 14 cm -3 ~1×10 16 cm -3 The channel layer has a thickness of 200~600nm and a doping concentration of 1×10⁻⁶. 17 cm -3 ~5×10 18 cm -3 The thickness of the heavily doped Ga2O3 cap layer is 10~50 nm, and the doping concentration is 1×10⁻⁶. 19 cm -3 ~1×10 21 cm -3 The thickness of the dielectric layer is 10~30nm.

[0056] refer to Figure 3 This invention provides a gallium oxide-based power transistor with low ohmic contact resistance, fabricated using a method for manufacturing such a transistor. The device includes an Fe-doped β-Ga₂O₃ substrate, a β-Ga₂O₃ UID layer, a β-Ga₂O₃ channel layer, an oxidized Ga₂O₃ cap layer, an Al₂O₃ dielectric layer, source / drain Ti / Au ohmic electrodes, and a Ni / Au gate. The bottom layer is the substrate, and above it is a 100-500 nm thick UID layer with a carrier concentration of 1 × 10⁻⁶.14 cm -3 ~1×10 16 cm -3 Above the UID layer is a channel layer of 200~600nm with a doping concentration of 1×10⁻⁶. 17 cm -3 ~5×10 18 cm -3 The ohmic region above the channel layer is a Ga2O3 cap layer obtained after oxidation, with a thickness of 10~50 nm and a doping concentration of 1×10⁻⁶. 19 cm -3 ~1×10 21 cm -3 Above the Ga2O3 cap layer 4 is the Ti / Au source / drain electrode, and between the Ga2O3 cap layers is a 10~30nm Al2O3 dielectric layer, above which is the Ni / Au gate.

[0057] The specific manufacturing process of the present invention will be described below through examples.

[0058] Example 1: Reference Figure 3 To fabricate gallium oxide power transistors with a 200nm channel layer.

[0059] Step 1a. Epitaxial growth of gallium oxide channel layer.

[0060] 1.1a) A β-Ga2O3 UID layer with a thickness of 100 nm and a carrier concentration of 1 × 10⁻⁶ is grown on an Fe-doped β-Ga2O3 substrate. 14 cm -3 ;

[0061] 1.2a) A channel layer with a thickness of 200 nm and a doping concentration of 1 × 10⁻⁶ is grown above the UID layer. 17 cm -3 ;

[0062] 1.3a) An epitaxial layer of Si-doped GaN with a thickness of 10 nm and a doping concentration of 1 × 10⁻⁶ is grown above the channel layer. 19 cm -3 ;

[0063] 1.4a) The epitaxial material is placed in an annealing furnace and annealed in an oxygen atmosphere. After annealing, the heavily doped GaN cap layer will be transformed into a heavily doped polycrystalline Ga2O3 cap layer.

[0064] Step 2a. Fabricate the ohmic electrode.

[0065] 2.1a) Etch the Ga2O3 cap layer except for the ohmic region to a depth of 10 nm;

[0066] 2.2a) A Ti / Au metal stack with thicknesses of 20 / 200 nm is deposited on top of the Ga2O3 cap layer;

[0067] 2.3a) Rapid hot annealing is used to alloy the ohmic metal to complete the fabrication of the source and drain ohmic electrodes;

[0068] Step 3a. Fabricate the gate electrode and interconnect metal.

[0069] 3.1a) An Al2O3 dielectric layer with a thickness of 10 nm is grown in the active region;

[0070] 3.2a) A Ni / Au metal stack with thicknesses of 45 / 400 nm is deposited on top of the Al2O3 dielectric layer;

[0071] 3.3a) The Al2O3 dielectric layer above the metal layer of the etching machine has an etching thickness of 10 nm;

[0072] 3.4a) Deposit interconnect metal and bring out electrodes.

[0073] Example 2: Reference Figure 3 They fabricated gallium oxide power transistors with a 400nm channel layer.

[0074] Step 1b. Epitaxial growth of gallium oxide channel layer.

[0075] 1.1b) A β-Ga2O3UID layer with a thickness of 300 nm and a carrier concentration of 1 × 10⁻⁶ is grown on an Fe-doped Ga2O3 substrate. 15 cm -3 ;

[0076] 1.2b) A channel layer with a thickness of 400 nm and a doping concentration of 1 × 10⁻⁶ is grown above the UID layer. 18 cm -3 ;

[0077] 1.3b) An epitaxial layer of Si-doped GaN with a thickness of 30 nm and a doping concentration of 1 × 10⁻⁶ is grown above the channel layer. 20 cm -3 ;

[0078] 1.4b) The epitaxial material is placed in an annealing furnace and annealed in an oxygen atmosphere. After annealing, the heavily doped GaN cap layer will be transformed into a heavily doped polycrystalline Ga2O3 cap layer.

[0079] Step 2b. Fabricate the ohmic electrode.

[0080] 2.1b) Etch the Ga2O3 cap layer except for the ohmic region to a depth of 30 nm;

[0081] 2.2b) A Ti / Au metal stack with thicknesses of 20 / 200 nm is deposited on top of the Ga2O3 cap layer;

[0082] 2.3b) Rapid hot annealing is used to alloy the ohmic metal to complete the fabrication of the source and drain ohmic electrodes;

[0083] Step 3b. Fabricate the gate electrode and interconnect metal.

[0084] 3.1b) An Al2O3 dielectric layer with a thickness of 20 nm is grown in the active region;

[0085] 3.2b) A Ni / Au metal stack with thicknesses of 45 / 400 nm is deposited on top of the Al2O3 dielectric layer;

[0086] 3.3b) The Al2O3 dielectric layer above the metal layer of the etching machine has an etching thickness of 20 nm;

[0087] 3.4b) Deposit interconnect metal and bring out electrodes.

[0088] Example 3: Reference Figure 3 They fabricated gallium oxide power transistors with a 600nm channel layer.

[0089] Step 1c. Epitaxial growth of gallium oxide channel layer.

[0090] 1.1c) A β-Ga2O3 UID layer with a thickness of 500 nm and a carrier concentration of 1 × 10⁻⁶ is grown on an Fe-doped β-Ga2O3 substrate. 16 cm -3 ;

[0091] 1.2c) A channel layer with a thickness of 600 nm and a doping concentration of 5 × 10⁻⁶ nm is grown above the UID layer. 18 cm -3 ;

[0092] 1.3) An epitaxial layer of Si-doped GaN with a thickness of 50 nm and a doping concentration of 1 × 10⁻⁶ is grown above the channel layer. 21 cm -3 ;

[0093] 1.4c) The epitaxial material is placed in an annealing furnace and annealed in an oxygen atmosphere at a temperature of 900°C for 5 minutes. After annealing, the heavily doped GaN cap layer will be transformed into a heavily doped polycrystalline Ga2O3 cap layer.

[0094] Step 2c. Fabricate the ohmic electrode.

[0095] 2.1c) Etch the Ga2O3 cap layer except for the ohmic region to a depth of 50 nm;

[0096] 2.2c) A Ti / Au metal stack is deposited on top of the Ga2O3 cap layer, with thicknesses of 20 / 200 nm, respectively;

[0097] 2.3c) Rapid thermal annealing is used to alloy the ohmic metal to complete the fabrication of the source and drain ohmic electrodes;

[0098] Step 3c. Fabricate the gate electrode and interconnect metal.

[0099] 3.1c) An Al2O3 dielectric layer with a thickness of 30 nm is grown in the active region;

[0100] 3.2c) A Ni / Au metal stack is deposited on top of the Al2O3 dielectric layer, with thicknesses of 45 / 400 nm, respectively;

[0101] 3.3c) The Al2O3 dielectric layer above the metal layer of the etching machine has an etching thickness of 30 nm;

[0102] 3.4c) Deposit interconnect metal and bring out electrodes.

[0103] This invention provides a method and device for fabricating a low-ohmic contact gallium oxide power transistor. The method involves growing a β-Ga2O3 UID layer on an Fe-doped β-Ga2O3 substrate using an epitaxial device, followed by a lightly doped channel layer on top of the UID layer, and then a Si-doped GaN layer. Due to the spontaneous polarization effect of GaN and its relatively easy doping, a heavily doped GaN layer is readily obtained. This invention anneals the GaN layer in an oxygen atmosphere at high temperature to form a heavily doped Ga2O3 cap layer, reducing the lattice mismatch between the two layers and serving as an ohmic contact layer. A good ohmic contact is then formed by depositing a Ti / Au metal stack on top of this cap layer, thereby reducing the on-resistance of the device. Finally, the gate is fabricated and electrodes are brought out to form a low-ohmic contact gallium oxide power transistor.

[0104] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0105] Although this application has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0106] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a gallium oxide-based power transistor with low ohmic contact resistance, characterized in that, include: Step 1: Obtain a β-Ga2O3 substrate; Step 2: Grow an unintentionally doped UID layer on the β-Ga2O3 substrate; Step 3: Grow a lightly doped β-Ga2O3 layer on the UID layer as a channel layer; Step 4: Grow a heavily doped GaN cap layer on the channel layer and anneal it in an oxygen atmosphere to obtain a heavily doped Ga2O3 cap layer. Step 5: Etch the heavily doped Ga2O3 cap layer in areas other than the ohmic region, while retaining the heavily doped Ga2O3 cap layer in the ohmic region; Step 6: Deposit a Ti / Au metal stack on top of the heavily doped Ga2O3 cap layer in the ohmic region, and perform thermal annealing to form the source electrode and drain electrode of the ohmic contact; Step 7: Grow an Al2O3 layer as a dielectric layer in the active region outside the ohmic region, and etch away the dielectric layer in the source and drain regions; Step 8: Deposit a Ni / Au stack as gate metal on the dielectric layer and fabricate interconnect leads to complete the fabrication of a gallium oxide-based power transistor with low ohmic contact resistance.

2. The method for fabricating a gallium oxide-based power transistor with low ohmic contact resistance according to claim 1, characterized in that, The UID layer has a thickness of 100~500 nm and a carrier concentration of 1×10⁻⁶. 14 cm -3 ~1×10 16 cm -3 The channel layer has a thickness of 200~600nm and a doping concentration of 1×10⁻⁶. 17 cm -3 ~5×10 18 cm -3 The thickness of the heavily doped Ga2O3 cap layer is 10~50 nm, and the doping concentration is 1×10⁻⁶. 19 cm -3 ~1×10 21 cm -3 The thickness of the dielectric layer is 10~30nm.

3. The method for fabricating a gallium oxide-based power transistor with low ohmic contact resistance according to claim 1, wherein step 4 includes: Step 4-1: Epitaxially grow a Si-doped GaN layer above the channel layer; Step 4-2: Place the material formed in step 4-1 into an annealing furnace and anneal it in an oxygen atmosphere to transform the heavily doped GaN cap layer into a heavily doped polycrystalline Ga2O3 cap layer.

4. The method for fabricating a gallium oxide-based power transistor with low ohmic contact resistance according to claim 2, wherein step 5 includes: The heavily doped Ga2O3 cap layer in areas other than the ohmic region is etched to a depth of 10-50 nm, while retaining the heavily doped Ga2O3 cap layer in the ohmic region.

5. The method for fabricating a gallium oxide-based power transistor with low ohmic contact resistance according to claim 2, wherein step 6 comprises: Step 6-1: Evaporate Ti / Au metal stacks with thicknesses of 20 / 200 nm on top of the heavily doped Ga2O3 cap layer in the ohmic region; Step 6-2: After evaporating the Ti / Au metal stack, perform rapid thermal annealing and alloy the evaporated Ti / Au metal to complete the fabrication of the source electrode and drain electrode.

6. The method for fabricating a gallium oxide-based power transistor with low ohmic contact resistance according to claim 2, wherein step 8 comprises: Step 8-1: Deposit Ni / Au metal stacks on top of the dielectric layer with thicknesses of 45 / 400 nm, respectively; Step 8-2: Etch the Al2O3 dielectric layer above the Ni / Au metal stack, with an etching thickness of 10-30 nm; Step 8-3: Deposit interconnect metal and bring out the source electrode, drain electrode, and gate electrode.

7. A gallium oxide-based power transistor device with low ohmic contact resistance, characterized in that, It is fabricated using the method for fabricating a gallium oxide-based power transistor with low ohmic contact resistance as described in any one of claims 1 to 6.

Images