A silicon-on-insulator structure and method of forming the same

Abstract

The application provides a silicon-on-insulator structure and a forming method thereof, and the forming method of the silicon-on-insulator structure increases the room-temperature bonding strength during a bonding process through an activation treatment, reduces the temperature required in a subsequent reinforcement process, thereby reducing the thermal diffusion of heterogeneous components in the etching stop layer, ensuring the clear interface between the etching stop layer and a device layer, and further avoiding the deterioration of the thickness uniformity of the device layer after the etching stop layer is removed in the subsequent process; the uniformity of the device layer after etching is controlled through two selective etching processes, so that the thickness uniformity of the device layer of the finally obtained silicon-on-insulator structure is less than 10%; and the formation and removal of a sacrificial oxide layer make the surface of the device layer not have a porous morphology of high-frequency etching undulation.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a silicon-on-insulator structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuits and the shrinking feature size of electronic components, FinFET and SOI (Silicon-On-Insulator, SOI) technologies have become the two mainstream approaches. As SOI technology continues to develop, the demand for SOI structures is also increasing. Typically, an SOI structure consists of a supporting substrate, an insulating layer, and a device layer. Current methods for fabricating SOI structures mainly include BESOI (bonding and back-side etching), SIMOX (oxygen-filled isolation), and Smartcut. TM BESOI effectively improves the thickness uniformity of the device layer by etching away the etch stop layer located on the device layer through different etch selectivity ratios of the etch stop layer and the device layer to the etch solution.

[0003] Currently, etch stop layers are mainly composed of heavily doped silicon (boron, carbon, nitrogen, etc.) or germanium-silicon alloys. When germanium-silicon alloys are used as etch stop layers, they need to be removed using a mixed solution of HF, HNO3, and Hac. This process forms a porous layer of tens of nanometers on the surface of the device layer. To avoid affecting the performance of subsequent devices, this porous layer needs to be effectively removed. Chemical mechanical polishing (CMP) can typically remove this porous layer, but it makes it difficult to control the thickness uniformity of the device layer. A mixed solution of HF and HNO3 can also be used for removal, but the micro-surface condition of the device layer after this removal process still does not meet the requirements of subsequent processes. Summary of the Invention

[0004] The purpose of this invention is to provide a silicon-on-insulator structure and a method for forming the same, which can effectively repair porous layers caused by the removal of corrosion stop layers and improve the thickness uniformity of the device layer surface.

[0005] To address the above problems, a method for forming a silicon-on-insulator structure is provided, comprising the following steps:

[0006] Step S1: Provide a first substrate and a second substrate. The first substrate has a first front side and a first back side disposed opposite to each other. An etching stop layer and a device layer are sequentially formed on the first front side. The second substrate has a second front side.

[0007] Step S2: Activate the surfaces of the second front side and the device layer, and bond the first substrate and the second substrate, with the second front side facing the device layer;

[0008] Step S3: Thin the first substrate from the first back side, and sequentially remove the remaining first substrate and the etching stop layer through two selective etching processes, so that the surface of the device layer has a porous layer; and

[0009] Step S4: A sacrificial oxide layer is generated on the device layer, the sacrificial oxide layer fills and covers the porous layer, and the sacrificial oxide layer and the porous layer are removed by a wet etching process to obtain a silicon-on-insulator structure.

[0010] Optionally, step S1 includes:

[0011] A first substrate is provided, the first substrate having a first front side and a first back side disposed opposite to each other;

[0012] A corrosion-stopping layer is formed on the first front surface;

[0013] A device layer is formed on the corrosion-stopping layer;

[0014] A second substrate is provided, wherein a polysilicon trapping layer is formed on the surface of the second substrate, and the surface of the polysilicon trapping layer is the second front side;

[0015] An insulating layer is formed through an oxidation process; and

[0016] The insulating layer is located on the surface of the device layer, or the insulating layer includes a first insulating layer and a second insulating layer, wherein the first insulating layer is located on the surface of the device layer and the second insulating layer is located on the second front side.

[0017] Furthermore, step S2 includes:

[0018] When the insulating layer is located on the surface of the device layer, the surfaces of the second front side and the insulating layer are activated using oxygen plasma treatment; and

[0019] The second front side faces the surface of the insulating layer and undergoes low-temperature hardening treatment.

[0020] Furthermore, step S2 includes:

[0021] When the first insulating layer is located on the surface of the device layer and the second insulating layer is located on the second front side, the surfaces of the first insulating layer and the second insulating layer are activated using oxygen plasma; and

[0022] The surface of the first insulating layer faces the surface of the second insulating layer and undergoes low-temperature hardening treatment.

[0023] Furthermore, the temperature for the reinforcement treatment is 300℃~500℃, and the treatment time is no more than 4 hours.

[0024] Optionally, step S3 includes:

[0025] The first substrate is thinned from the first back side using mechanical grinding;

[0026] The remaining first substrate is selectively etched for the first time by a first etchant, and the etching stops at the etching stop layer;

[0027] The corrosion stop layer is selectively etched a second time by a second etchant, and the etching stops on the surface of the device layer, so that the surface of the device layer has a porous layer.

[0028] Furthermore, the first etchant is TMAH, the concentration of the first etchant is not higher than 25%, and the corrosion temperature is 55℃~70℃.

[0029] Furthermore, the second corrosive agent is a mixed solution of HF, HNO3 and Hac, or a mixed solution of HF, H2O2 and Hac.

[0030] Optionally, step S4 includes:

[0031] The surface of the device layer is oxidized under dry oxygen, wet oxygen, or a combination of dry and wet oxygen atmospheres to generate a sacrificial oxide layer on the device layer, which fills and covers the porous layer.

[0032] The sacrificial oxide layer and porous layer are removed by a wet etching process to obtain a silicon-on-insulator structure; and

[0033] The surface roughness of the device layer is optimized by heat treatment.

[0034] Furthermore, the wet etching process uses an HF solution with a concentration of less than 20%.

[0035] On the other hand, the present invention also provides a silicon-on-insulator structure, which is prepared by the method for forming the silicon-on-insulator structure.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] This invention provides a silicon-on-insulator (SiI) structure and a method for forming the same. The method for forming the SiI structure includes the following steps: Step S1: providing a first substrate and a second substrate, the first substrate having a first front side and a first back side disposed opposite to each other, the first front side having an etch stop layer and a device layer formed sequentially thereon, and the second substrate having a second front side; Step S2: activating the surfaces of the second front side and the device layer, and bonding the first substrate and the second substrate, the second front side facing the device layer; Step S3: thinning the first substrate from the first back side, and sequentially removing the remaining first substrate and the etch stop layer through two selective etching processes, so that the surface of the device layer has a porous layer; and Step S4: generating a sacrificial oxide layer on the device layer, the sacrificial oxide layer filling and covering the porous layer, and removing the sacrificial oxide layer and the porous layer through a wet etching process to obtain the SiI structure. This invention increases the bonding strength at room temperature during the bonding process through activation treatment, thereby reducing the temperature required for the bonding process. This reduces the thermal diffusion of the heterogeneous component (germanium) in the etch stop layer, ensuring a clear interface between the etch stop layer and the device layer. This also prevents the device layer from deteriorating in thickness uniformity after the etch stop layer is subsequently removed. Furthermore, the uniformity of the device layer after etching is controlled through two selective etching processes, resulting in a final silicon-on-insulator structure device layer with a thickness uniformity of less than 10%. Additionally, the formation and removal of the sacrificial oxide layer ensures that there is no porous layer with high-frequency etch fluctuations on the device layer surface. Attached Figure Description

[0038] Figure 1 This is a schematic flowchart of a method for forming a silicon-on-insulator structure according to an embodiment of the present invention;

[0039] Figures 2-8 This is a schematic diagram of the formation process of a silicon-on-insulator structure according to an embodiment of the present invention;

[0040] Figure 9 This is a schematic diagram of AFM on the surface of a device layer of a silicon-on-insulator structure;

[0041] Figure 10 This is an AFM schematic diagram of the device layer surface of a silicon-on-insulator structure provided in an embodiment of the present invention.

[0042] Explanation of reference numerals in the attached figures:

[0043] 100 - First substrate; 100a - First front side; 100b - First back side; 110 - Etching stop layer; 120 - Device layer; 121 - Porous layer; 130 - Insulating layer; 140 - Sacrificial oxide layer;

[0044] 200 - Second substrate; 200a - Second front side; 210 - Polysilicon trapping layer. Detailed Implementation

[0045] The following will provide a more detailed description of a silicon-on-insulator structure and its formation method according to the present invention. The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0046] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would obscure the invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific objectives, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.

[0047] To make the objectives and features of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention.

[0048] Figure 1 This is a schematic flowchart of a method for forming a silicon-on-insulator structure provided in this embodiment. Figure 1 As shown, this embodiment provides a method for forming a silicon-on-insulator structure, including the following steps:

[0049] Step S1: Provide a first substrate and a second substrate. The first substrate has a first front side and a first back side disposed opposite to each other. An etching stop layer and a device layer are sequentially formed on the first front side. The second substrate has a second front side.

[0050] Step S2: Activate the surfaces of the second front side and the device layer, and bond the first substrate and the second substrate, with the second front side facing the device layer;

[0051] Step S3: Thin the first substrate from the first back side, and sequentially remove the remaining first substrate and the etching stop layer through two selective etching processes, so that the surface of the device layer has a porous layer; and

[0052] Step S4: A sacrificial oxide layer is generated on the device layer, the sacrificial oxide layer fills and covers the porous layer, and the sacrificial oxide layer and the porous layer are removed by a wet etching process to obtain a silicon-on-insulator structure.

[0053] The following combination Figures 2-10 This embodiment provides a detailed description of a method for forming a silicon-on-insulator structure.

[0054] like Figure 2 and 3 As shown, step S1 is first performed to provide a first substrate 100 and a second substrate 200. The first substrate has a first front side 100a and a first back side 100b disposed opposite to each other. An etching stop layer 110 and a device layer 120 are sequentially formed on the first front side 100a. The second substrate 200 has a second front side 200a.

[0055] This step specifically includes:

[0056] like Figure 2 As shown, firstly, a first substrate 100 is provided. The first substrate 100 can be a single-crystal silicon substrate, a germanium-silicon substrate, a silicon carbide substrate, or various III-V group semiconductor substrates. The first substrate 100 has a first front side 100a and a first back side 100b disposed opposite to each other. In this embodiment, the first substrate 100 can all be p-type silicon substrates, and the resistivity of the first substrate 100 is greater than 5 Ω·cm; preferably, the resistivity of the first substrate 100 is greater than 10 Ω·cm.

[0057] Next, a corrosion stop layer 110 is formed on the first front surface 100a. The corrosion stop layer 110 can be a germanium-silicon alloy; preferably, the germanium content in the corrosion stop layer 110 is 0.1–0.5%, and the silicon content is 0.2–0.3%. The thickness of the corrosion stop layer 110 is 10 nm–60 nm.

[0058] In this step, the temperature required to form the corrosion stop layer 110 is below 800°C, and the entire process of forming the corrosion stop layer 110 is reduced pressure epitaxy, with silicon and germanium epitaxial precursors being DCS and GeH4, respectively.

[0059] Next, a device layer 120 is formed on the etch stop layer 110. The device layer 120 is made of silicon and is doped with p-type or n-type ions. The type and concentration of doped ions in the device layer 120 depend on the specific requirements of the subsequently formed silicon-on-insulator structure. To ensure the uniformity of the thickness of the silicon-on-insulator structure, the thickness of the device layer 120 is no greater than 600 nm.

[0060] In this step, the temperature required to form the device layer 120 is below 800°C, and the entire process of forming the device layer 120 is depressurized epitaxy, and the epitaxial precursor of the device layer 120 is DCS.

[0061] like Figure 3 As shown, a second substrate 200 is provided. The second substrate 200 serves as a support substrate for the subsequently formed silicon-on-insulator structure and mainly plays a supporting role. The second substrate 200 can be a single-crystal silicon substrate, a germanium-silicon substrate, a silicon carbide substrate, various III-V semiconductor substrates, a silicon substrate with a polycrystalline trapping layer deposited, a sapphire substrate, a quartz substrate, and a glass substrate, etc.

[0062] In this embodiment, the first substrate 100 has the same shape as the second substrate 200, and the dimensions of the first substrate 100 and the second substrate 200 are the same. The second substrate 200 is a high-resistivity silicon substrate, on which a polycrystalline silicon trapping layer 210 is formed, and the resistivity of the second substrate 200 is greater than 1000 ohm·cm. The surface of the polycrystalline silicon trapping layer 210 is the second front side 200a.

[0063] Next, an insulating layer 130 is formed through an oxidation process.

[0064] like Figure 2 As shown, in this embodiment, the insulating layer 130 can be located on the surface of the device layer 120 and serve as the final insulating layer of the silicon-on-insulator structure. In this case, the surface of the polysilicon trapping layer 210 (i.e., the second front side 200a) is the bonding surface on the second substrate side during bonding, and the surface of the insulating layer 130 is the bonding surface on the first substrate side during bonding.

[0065] In other embodiments, the insulating layer includes a first insulating layer and a second insulating layer. The first insulating layer is formed on the surface of the device layer, and the second insulating layer is formed on the second front side 200a. The first insulating layer and the second insulating layer together serve as the final insulating layer of the silicon-on-insulator structure. In this case, the surface of the first insulating layer is the bonding surface on the first substrate side during bonding; and the surface of the second insulating layer is the bonding surface on the second substrate side during bonding.

[0066] To prevent thermal diffusion of doped ions in the device layer 120 and / or the second substrate 200, the oxidation temperature of the oxidation process is not higher than 850°C, preferably not higher than 800°C, while the oxidation time depends on the thickness requirement of the insulating layer 130.

[0067] like Figure 4As shown, step S2 is then performed to activate the surfaces of the second front surface 200a and the device layer 120, and to bond the first substrate 100 and the second substrate 200, with the second front surface 200a facing the device layer 120.

[0068] First, in this embodiment, since the insulating layer 130 is located on the surface of the device layer 120, oxygen plasma is used to activate the surface of the polysilicon trapping layer (i.e., the second front side 200a) and the surface of the insulating layer 130 to increase the bonding strength at room temperature.

[0069] In other embodiments, since the first insulating layer and the second insulating layer are located on the surface of the device layer and the second front side 200a, respectively, oxygen plasma activation treatment is used to treat the surfaces of the first insulating layer and the second insulating layer to increase the bonding strength at room temperature.

[0070] Next, in this embodiment, the second front surface 200a faces the surface of the insulating layer 130, and the insulating layer 130 is bonded as an intermediate layer and subjected to low-temperature hardening treatment. The temperature of the low-temperature hardening treatment is not higher than 700°C, preferably 300°C to 500°C, and the treatment time is not higher than 4 hours.

[0071] Because the surfaces of the second front side 200a and the device layer 120 are activated, the temperature during this reinforcement process is lower, which reduces the thermal diffusion of the heterogeneous component (germanium) in the corrosion stop layer 110 and ensures a clear interface between the corrosion stop layer 110 and the device layer 120. This avoids the deterioration of the thickness uniformity of the device layer 120 after the corrosion stop layer 110 is subsequently removed.

[0072] In other embodiments, the surface of the first insulating layer faces the surface of the second insulating layer, and the first and second insulating layers are bonded together as an intermediate layer and subjected to low-temperature hardening treatment. The temperature of the low-temperature hardening treatment is not higher than 700°C, preferably 300°C to 500°C, and the treatment time is not higher than 4 hours.

[0073] Because the surfaces of the first insulating layer and the second insulating layer are activated, the temperature during this reinforcement process is lower, which reduces the thermal diffusion of the heterogeneous component (germanium) in the corrosion stop layer 110 and ensures a clear interface between the corrosion stop layer 110 and the device layer 120. This avoids the deterioration of the thickness uniformity of the device layer 120 after the corrosion stop layer 110 is subsequently removed.

[0074] like Figure 5 and Figure 6As shown, step S3 is then performed, the first substrate 100 is thinned from the first back side 100b, and the remaining first substrate 100 and the etching stop layer 110 are removed sequentially by two selective etching processes, and the etching stop is etched on the surface of the device layer 120, so that the surface of the device layer 120 has a porous layer 121, so as to control the uniformity of the device layer 120 after etching by two selective etching processes, so that the thickness uniformity of the silicon-on-insulator thin film obtained in the end is less than 10%.

[0075] This step specifically includes:

[0076] like Figure 5 As shown, firstly, the first substrate 100 is thinned from the first back surface 100b using mechanical polishing, such as chemical mechanical polishing, wherein the thickness of the thinned first substrate 100 is controlled to be within 2 μm, and the thickness difference of the thinned first substrate 100 is less than 0.5 μm, that is, the thickness of the thinned first substrate 100 is 1.5 μm to 2 μm.

[0077] Next, the remaining first substrate 100 is selectively etched for the first time, and the etching stops on the surface of the etching stop layer 110. Specifically, the remaining first substrate 100 is selectively etched for the first time using a stress-sensitive first etchant, and the etching stops on the surface of the etching stop layer 110.

[0078] In this step, the first corrosive agent can be TMAH (tetramethylammonium hydroxide), the concentration of the first corrosive agent is not higher than 25%, and the corrosion temperature is 50℃~90℃, preferably 55℃~70℃.

[0079] like Figure 6 As shown, the etching stop layer 110 is then selectively etched a second time, and the etching stops on the surface of the device layer 120. Specifically, the etching stop layer 110 is selectively etched a second time using a second etchant with a high etching selectivity, and the etching stops on the surface of the device layer 120, resulting in a porous layer 121 on the surface of the device layer 120.

[0080] In this step, the second corrosive agent can be a mixed solution of HF, HNO3 and Hac or a mixed solution of HF, H2O2 and Hac.

[0081] As the device layer 120 is corroded by the second etchant in this step, a porous layer with a depth of tens of nanometers is formed on the surface of the device layer 120. The porous layer of the device layer 120 is made of silicon and silicon oxide compounds, wherein the silicon oxide compounds are formed by the reaction of H2O2 or HNO3 in the second etchant with the surface of the device layer.

[0082] like Figure 7 and Figure 8 As shown, step S4 is then performed to generate a sacrificial oxide layer 140 on the device layer 120. The sacrificial oxide layer 140 fills and covers the porous layer 121. The sacrificial oxide layer 140 and the porous layer 121 are then removed by a wet etching process to obtain a silicon-on-insulator structure.

[0083] This step specifically includes:

[0084] like Figure 7 As shown, firstly, in order to remove the porous layer 121, the surface of the device layer 120 is oxidized under a dry oxygen, wet oxygen, or a combination of dry and wet oxygen atmosphere to form a sacrificial oxide layer 140 on the device layer 120. The sacrificial oxide layer 140 fills and covers the porous layer 121. The oxidation temperature during the oxidation process is 700℃~1100℃, preferably 750℃~1000℃. The thickness of the sacrificial oxide layer 140 is 50nm~200nm, meaning that 50nm~200nm of silicon on the surface of the device layer 120 is oxidized into a sacrificial oxide layer. The oxidation time during the oxidation process is determined based on the thickness of the sacrificial oxide layer 140 and the oxidation temperature.

[0085] like Figure 8 As shown, the sacrificial oxide layer 140 and the porous layer 121 are then removed by a wet etching process to obtain a silicon-on-insulator structure.

[0086] In detail, firstly, the wet etching process uses an HF solution to remove the sacrificial oxide layer 140 and the porous layer 121. The concentration of the HF solution is less than 20%, preferably 5%, at which point the porous layer 121 is effectively removed.

[0087] Next, the surface roughness of the device layer 120 is optimized by heat treatment (i.e., rapid heat treatment, long-term heat treatment, or alternation of both), thereby further reducing the surface roughness of the device layer 120. The atmosphere during heat treatment is a hydrogen-argon mixed atmosphere or a pure argon atmosphere. This step removes the porous layer 121 with its high-frequency etched porous morphology by removing the sacrificial oxide layer 140, ensuring that the surface of the device layer 120 is free of the porous layer 121.

[0088] like Figure 9 As shown, in the prior art, a porous layer 121 is formed on the surface of the device layer of a silicon-on-insulator structure, which makes it difficult to control the thickness uniformity of the device layer. Figure 10As shown, the surface of the device layer of the silicon-on-insulator structure in this embodiment has high thickness uniformity due to the removal of the porous layer 121.

[0089] This embodiment also provides a silicon-on-insulator structure, which is prepared by the above-described method for forming a silicon-on-insulator structure.

[0090] In summary, the present invention provides a silicon-on-insulator (SiI) structure and a method for forming the same. The method for forming the SiI structure includes the following steps: Step S1: providing a first substrate and a second substrate, the first substrate having a first front side and a first back side disposed opposite to each other, the first front side having an etch stop layer and a device layer formed sequentially thereon, and the second substrate having a second front side; Step S2: activating the surfaces of the second front side and the device layer, and bonding the first substrate and the second substrate, the second front side facing the device layer; Step S3: thinning the first substrate from the first back side, and sequentially removing the remaining first substrate and the etch stop layer through two selective etching processes, so that the surface of the device layer has a porous layer; and Step S4: generating a sacrificial oxide layer on the device layer, the sacrificial oxide layer filling and covering the porous layer, and removing the sacrificial oxide layer and the porous layer through a wet etching process to obtain the SiI structure. This invention increases the bonding strength at room temperature during the bonding process through activation treatment, thereby reducing the temperature required for the bonding process. This reduces the thermal diffusion of the heterogeneous component (germanium) in the etch stop layer, ensuring a clear interface between the etch stop layer and the device layer. This also prevents the device layer from deteriorating in thickness uniformity after the etch stop layer is subsequently removed. Furthermore, the uniformity of the device layer after etching is controlled through two selective etching processes, resulting in a thickness uniformity of less than 10% for the final silicon-on-insulator structure device layer. Additionally, the formation and removal of the sacrificial oxide layer ensures that the surface of the device layer does not have a porous structure (i.e., a porous layer) with high-frequency etching fluctuations (porous morphology).

[0091] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

Claims

1. A method for forming a silicon-on-insulator structure, characterized in that, Includes the following steps: Step S1: Provide a first substrate and a second substrate. The first substrate has a first front side and a first back side disposed opposite to each other. An etching stop layer and a device layer are sequentially formed on the first front side. The second substrate has a second front side. Step S2: The surfaces of the second front side and the device layer are activated using oxygen plasma, and the first substrate and the second substrate are bonded together. The second front side faces the device layer and is subjected to low-temperature hardening treatment at a temperature of 300℃~500℃. Step S3: Thin the first substrate from the first back side using mechanical polishing; The remaining first substrate is selectively etched for the first time by a first etchant, and the etching stops at the etching stop layer; The corrosion stop layer is selectively etched a second time by a second etchant, and the etching stops on the surface of the device layer, so that the surface of the device layer has a porous layer; as well as Step S4: A sacrificial oxide layer is generated on the device layer, the sacrificial oxide layer fills and covers the porous layer, and the sacrificial oxide layer and the porous layer are removed by a wet etching process to obtain a silicon-on-insulator structure.

2. The forming method as described in claim 1, characterized in that, Step S1 includes: A first substrate is provided, the first substrate having a first front side and a first back side disposed opposite to each other; A corrosion-stopping layer is formed on the first front surface; A device layer is formed on the corrosion-stopping layer; A second substrate is provided, wherein a polysilicon trapping layer is formed on the surface of the second substrate, and the surface of the polysilicon trapping layer is the second front side; An insulating layer is formed through an oxidation process; and The insulating layer is located on the surface of the device layer, or the insulating layer includes a first insulating layer and a second insulating layer, wherein the first insulating layer is located on the surface of the device layer and the second insulating layer is located on the second front side.

3. The forming method as described in claim 1, characterized in that, The reinforcement treatment time should not exceed 4 hours.

4. The forming method as described in claim 1, characterized in that, The first etchant is TMAH, the concentration of the first etchant is not higher than 25%, and the corrosion temperature is 55℃~70℃.

5. The forming method as described in claim 1, characterized in that, The second corrosive agent is a mixed solution of HF, HNO3 and Hac, or a mixed solution of HF, H2O2 and Hac.

6. The forming method as described in claim 1, characterized in that, Step S4 includes: The surface of the device layer is oxidized under dry oxygen, wet oxygen, or a combination of dry and wet oxygen atmospheres to generate a sacrificial oxide layer on the device layer, which fills and covers the porous layer. The sacrificial oxide layer and porous layer are removed by a wet etching process to obtain a silicon-on-insulator structure; and The surface roughness of the device layer is optimized by heat treatment.

7. The forming method as described in claim 6, characterized in that, The wet etching process uses an HF solution with a concentration of less than 20%.

8. A silicon-on-insulator structure, characterized in that, It is prepared by the method for forming a silicon-on-insulator structure according to any one of claims 1 to 7.

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