Semiconductor structure and method of forming a semiconductor structure

Abstract

A semiconductor structure and a method of forming the same. The method includes providing a substrate having a plurality of first device structures and second device structures on the substrate on both sides of the first device structures; forming a first dielectric layer on the substrate, the first dielectric layer having a first opening therein, the first opening exposing a portion of a top surface of the first device structures; forming a first connection layer in the first opening; forming a passivation layer on a top surface of the first connection layer; after forming the passivation layer, forming a second opening in the first dielectric layer, the second opening exposing a portion of a surface of the second device structures; and forming a second connection layer in the second opening using a selective deposition process, the second connection layer having a growth rate on the second device structures that is greater than a growth rate on the passivation layer. The semiconductor structure formed by the method has improved performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the semiconductor structure. Background Technology

[0002] Metal interconnect structures are indispensable in semiconductor devices, used to interconnect active regions, transistors, or different layers of metal lines to achieve signal transmission and control. Therefore, the formation of metal interconnect structures has a significant impact on the performance and manufacturing cost of semiconductor devices during semiconductor manufacturing. To increase device density, the size of semiconductor devices in integrated circuits has been continuously reduced. To achieve electrical connections between these semiconductor devices, multi-layer interconnect structures are typically required.

[0003] Generally, in the back-end interconnect process of semiconductor device manufacturing, the first metal layer (M1) needs to form an electrical connection with the underlying active device structure (including source / drain regions and gate structure regions). Therefore, before forming the first metal layer, it is usually necessary to pre-form the local interconnect structure of the semiconductor device. The local interconnect structure includes: a zeroth metal layer (M0) electrically connected to the underlying source / drain regions, and a zeroth gate metal layer (M0G) electrically connected to the gate structure.

[0004] However, the manufacturing process of semiconductor structures with local interconnect structures in the prior art is complex, and the performance of the resulting semiconductor structures needs to be further improved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the semiconductor structure.

[0006] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate having a plurality of first device structures and second device structures located on substrates on both sides of the first device structures; forming a first dielectric layer on the substrate, the first dielectric layer having a first opening that exposes a portion of the top surface of the first device structures; forming a first interconnect layer within the first opening; forming a passivation layer on the top surface of the first interconnect layer; after forming the passivation layer, forming a second opening within the first dielectric layer that exposes a portion of the surface of the second device structures; and forming a second interconnect layer within the second opening using a selective deposition process, wherein the growth rate of the second interconnect layer on the second device structures is greater than the growth rate on the passivation layer.

[0007] Optionally, the method of forming a passivation layer on the top surface of the first interconnect layer includes: performing a passivation treatment on the top surface of the first interconnect layer, forming a passivation layer on the top surface of the first interconnect layer, wherein the material of the passivation layer includes the first interconnect layer material containing doped ions.

[0008] Optionally, the passivation process for the top surface of the first connection layer includes a plasma treatment process containing doped ions.

[0009] Optionally, the passivation process for the top surface of the first connection layer includes an ion implantation process containing doped ions.

[0010] Optionally, the doped ions may include nitrogen ions.

[0011] Optionally, while passivating the top surface of the first connecting layer, the method further includes: passivating the top surface of the first dielectric layer and forming a barrier layer on the top surface of the first dielectric layer.

[0012] Optionally, the thickness of the passivation layer ranges from 50 angstroms to 100 angstroms.

[0013] Optionally, the material of the first connecting layer includes a metal, including tungsten.

[0014] Optionally, the method of forming the second interconnect layer includes: forming an initial second interconnect layer within a second opening; planarizing the initial interconnect layer until the surface of the first dielectric layer is exposed, thereby forming the second interconnect layer.

[0015] Optionally, the passivation layer is also planarized while the initial connection layer is planarized.

[0016] Optionally, the material of the initial second bonding layer includes a metal, including tungsten.

[0017] Optionally, the process for forming the initial second bonding layer includes a selective deposition process; the temperature range is 300 degrees Celsius to 400 degrees Celsius, and the reaction gas is a mixture of hydrogen and tungsten hexafluoride.

[0018] Optionally, the method for planarizing the initial bonding layer and the passivation layer includes: forming a pad layer on the initial bonding layer, the passivation layer, and the first dielectric layer; forming a buffer layer on the pad layer; and planarizing the buffer layer, the pad layer, and the initial bonding layer using a chemical mechanical polishing process until the surface of the first dielectric layer is exposed.

[0019] Optionally, the material of the buffer layer is the same as that of the initial connection layer.

[0020] Optionally, the material of the liner layer includes one or both of a metal and a metal compound; the metal includes titanium or tantalum; the metal compound includes titanium nitride or tantalum nitride.

[0021] Accordingly, the present invention also provides a semiconductor structure, comprising: a substrate having a plurality of first device structures and second device structures located on both sides of the first device structures on the substrate; a first dielectric layer located on the substrate, the first dielectric layer having a first opening and a second opening, the first opening exposing a portion of the top surface of the first device structure, and the second opening exposing the top surface of the second device structure; a first interconnect layer located within the first opening; a passivation layer located on the top surface of the first interconnect layer; and a second interconnect layer located within the second opening.

[0022] Optionally, the passivation layer may be made of a first interconnecting layer material containing doped ions.

[0023] Optionally, the doping ions include nitrogen ions.

[0024] Optionally, it may also include: a barrier layer located on the top surface of the first dielectric layer, the barrier layer being made of a material comprising the first dielectric layer material containing doped ions, the barrier layer exposing the surface of the passivation layer.

[0025] Optionally, the first device structure includes a gate structure; the second device structure includes a conductive structure.

[0026] Optionally, the first device structure includes a gate structure; the second device structure includes a conductive structure.

[0027] Optionally, the material of the second device structure includes a metal, including cobalt.

[0028] Optionally, the substrate further includes: source / drain doped regions located within the substrates on both sides of the gate structure; the conductive structure is located on the source / drain doped regions.

[0029] Optionally, the substrate includes: a base, and a fin structure located on the base; the gate structure spans the fin structure, and the source / drain doped regions are located within the fin structures on both sides of the gate structure.

[0030] Optionally, the first device structure further includes a capacitor, an inductor, or a resistor; the second device structure further includes a capacitor, an inductor, or a resistor.

[0031] Optionally, the substrate further comprises a second dielectric layer, wherein a plurality of the first device structures and the second device structures are located within the second dielectric layer; the first dielectric layer is located on the second dielectric layer.

[0032] Optionally, the material of the first connecting layer includes a metal, the metal including tungsten; the material of the second connecting layer includes a metal, the metal including tungsten.

[0033] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0034] The method for forming the technical solution of the present invention involves forming a passivation layer on the top surface of a first interconnect layer, followed by forming a second interconnect layer within a second opening using a selective deposition process. The growth rate of the second interconnect layer on the second device structure is greater than its growth rate on the passivation layer. This reduces the likelihood of a large amount of material from the second interconnect layer growing on the first interconnect layer. Subsequent planarization yields a dense first and second interconnect layer, which is beneficial for improving the performance of the semiconductor structure.

[0035] Furthermore, the passivation process for the top surface of the first interconnect layer includes a treatment process using a doped ion gas or an ion implantation process using doped ions; the material of the passivation layer includes the material of the first interconnect layer containing doped ions. Thus, the passivation layer can be removed during the subsequent planarization process, thereby simplifying the process flow. Attached Figure Description

[0036] Figure 1 and Figure 2 This is a schematic diagram of the semiconductor structure formation process in one embodiment;

[0037] Figures 3 to 8 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention;

[0038] Figure 9 This is a schematic diagram of the semiconductor structure formation process in another embodiment of the present invention. Detailed Implementation

[0039] As described in the background section, the manufacturing process of semiconductor structures with local interconnect structures in the prior art is complex, and the performance of the resulting semiconductor structures needs further improvement. The following analysis and explanation will be provided with reference to specific embodiments.

[0040] Figure 1 and Figure 2 This is a schematic diagram of the semiconductor structure formation process in one embodiment.

[0041] Please refer to Figure 1A substrate 100 is provided; a gate structure 101 and source / drain doped regions 102 located in the substrate on both sides of the gate structure 101 are formed on the substrate 100; a first dielectric layer 103 is formed on the substrate 100 and the gate structure 101; a source / drain plug 104 is formed in the first dielectric layer 103, the source / drain plug 104 being electrically connected to the source / drain doped regions 102; a second dielectric layer 105 is formed on the first dielectric layer 103; a gate plug 106 is formed in the second dielectric layer 105, the gate plug 106 being located on the gate structure 101; after forming the gate plug 106, an opening 107 is formed in the second dielectric layer 105, the opening 107 exposing a portion of the top surface of the source / drain plug 104.

[0042] Please refer to Figure 2 A conductive layer 108 is formed inside the opening 107.

[0043] During the formation of the semiconductor structure, both the gate plug 106 and the conductive layer 108 are made of tungsten. Because the film structure of the gate structure 101 is complex, the process of etching to form the opening of the gate plug 106 is relatively complicated. Therefore, the gate plug 106 is formed first, followed by the conductive layer 108. The conductive layer 108 is formed using a selective deposition process, resulting in a dense structure and low resistance.

[0044] However, during selective deposition, the material forming the conductive layer 108 also grows on the gate plug 106, forming a top cap layer 109 on the gate plug 106. Subsequently, after forming a pad layer (not shown) and a buffer layer (not shown) on the second dielectric layer 105, during the planarization process of the top cap layer 109 and the conductive layer 108, the large volume of the top cap layer 109 can form large particles that scratch the substrate surface and affect the substrate performance.

[0045] To address the aforementioned problems, the present invention provides a semiconductor structure and a method for forming the semiconductor structure. By forming a passivation layer on the top surface of a first interconnect layer, a second interconnect layer is subsequently formed within a second opening using a selective deposition process. The growth rate of the second interconnect layer on the second device structure is greater than its growth rate on the passivation layer. This reduces the likelihood of material from the second interconnect layer growing on the first interconnect layer. Subsequent planarization yields a dense first and second interconnect layer, which is beneficial for improving the performance of the semiconductor structure.

[0046] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0047] Figures 3 to 8This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention.

[0048] Please refer to Figure 3 A substrate 200 is provided, wherein a plurality of first device structures 201 are provided on the substrate 200 and second device structures 202 are located on the substrate 200 on both sides of the first device structures 201.

[0049] In this embodiment, the first device structure 201 includes a gate structure; the second device structure 202 includes a conductive structure.

[0050] In this embodiment, the substrate 200 further includes: source / drain doped regions 203 located within the substrates 200 on both sides of the gate structure; the conductive structure is located on the source / drain doped regions 203.

[0051] The conductive structure is made of a metal, including cobalt.

[0052] The substrate 200 also has a second dielectric layer 204, and a plurality of the first device structures 201 and the second device structures 202 are located within the second dielectric layer 204.

[0053] In this embodiment, the substrate 200 is a planar substrate. The material of the substrate 200 includes silicon.

[0054] The material of the second dielectric layer 204 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride. In this embodiment, the material of the second dielectric layer 204 includes silicon oxide.

[0055] In other embodiments, the substrate includes: a base, and fin structures located on the base; the gate structure spans the fin structures, and the source / drain doped regions are located within the fin structures on both sides of the gate structure.

[0056] In other embodiments, the first device structure further includes a capacitor, an inductor, or a resistor; the second device structure further includes a capacitor, an inductor, or a resistor.

[0057] Please refer to Figure 4 A first dielectric layer 205 is formed on a substrate 200. The first dielectric layer 205 has a first opening (not shown) that exposes a portion of the top surface of the first device structure 201.

[0058] The first dielectric layer 205 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride. In this embodiment, the first dielectric layer 205 is made of silicon oxide.

[0059] The method for forming the first dielectric layer 205 and the first opening includes: forming an initial first dielectric layer (not shown) on a substrate 200; forming a patterned layer (not shown) on the initial first dielectric layer; etching the initial first dielectric layer using the patterned layer as a mask until the top surface of the first device structure 201 is exposed, thereby forming the first dielectric layer 205 and the first opening located within the first dielectric layer 205.

[0060] Please continue to refer to this. Figure 4 A first connecting layer 206 is formed within the first opening.

[0061] The material of the first connecting layer 206 includes metal, and the metal includes tungsten.

[0062] The method of forming the first connection layer 206 includes: forming a first connection material layer (not shown) in a first opening; planarizing the first connection material layer until the surface of the first dielectric layer 205 is exposed, thereby forming the first connection layer 206.

[0063] The process for forming the first bonding material layer includes selective deposition or chemical vapor deposition.

[0064] Please refer to Figure 5 A passivation layer 207 is formed on the top surface of the first connection layer 206.

[0065] The method of forming a passivation layer 207 on the top surface of the first connection layer 206 includes: performing a passivation treatment on the top surface of the first connection layer 206, and forming a passivation layer 207 on the top surface of the first connection layer 206, wherein the material of the passivation layer 207 includes the material of the first connection layer 206 containing doped ions.

[0066] The passivation layer 207 is made of the same material as the first interconnecting layer 206 containing doped ions. Therefore, the passivation layer 207 can be removed during subsequent planarization, thus simplifying the process flow.

[0067] In this embodiment, the passivation process for the top surface of the first connecting layer 206 includes a plasma treatment process containing doped ions.

[0068] In other embodiments, the passivation process for the top surface of the first interconnect layer includes an ion implantation process containing doped ions.

[0069] The doping ions include nitrogen ions. The nitrogen ions can suppress the growth of material subsequently forming the second interconnect layer on the top surface of the first interconnect layer 206.

[0070] The thickness of the passivation layer 207 ranges from 50 angstroms to 100 angstroms. If the passivation layer 207 is too thin, i.e., less than 50 angstroms, it is easy for the passivation layer 207 to lose its protective function for the first interconnect layer 206 after being damaged in subsequent processes. If the passivation layer 207 is too thick, i.e., greater than 100 angstroms, it will affect the height dimension of the first interconnect layer 206, and the passivation layer 207 will be difficult to remove completely during subsequent planarization, affecting the performance of the semiconductor structure.

[0071] While passivating the top surface of the first connecting layer 206, the method also includes: passivating the top surface of the first dielectric layer 205 and forming a barrier layer 208 on the top surface of the first dielectric layer 205.

[0072] If there is no barrier layer 208 on the surface of the first dielectric layer 205, when the second connection layer is subsequently formed in the second opening, the process time for forming the second connection layer is long due to the large depth-to-width ratio of the second opening. The process of forming the second connection layer can modify and consume the surface of the first dielectric layer 205 to a certain extent, and nucleate on the surface of the first dielectric layer 205 so that the second connection layer can grow on the surface of the first dielectric layer 205, which will affect the insulation performance of the first dielectric layer 205 and thus affect the performance of the semiconductor structure.

[0073] The top surface of the first dielectric layer 205 contains nitrogen ions, so the barrier layer 208 can protect the surface of the first dielectric layer 205. The nitrogen-containing surface can inhibit the growth of the second connecting layer, which has a long formation process, on the surface of the first dielectric layer 205 on the top surface of the second opening, thereby sealing the opening and affecting the quality of the second connecting layer.

[0074] Please refer to Figure 6 After the passivation layer 207 is formed, a second opening 209 is formed in the first dielectric layer 205, and the second opening 209 exposes part of the surface of the second device structure 202.

[0075] The method for forming the second opening 209 includes: forming a patterned layer (not shown) on the first dielectric layer 205; etching the first dielectric layer 205 using the patterned layer as a mask until the surface of the second device structure 202 is exposed, thereby forming the second opening 209.

[0076] The etching process for the first dielectric layer 205 includes a dry etching process, wherein the gas used in the dry etching process includes a fluorine-containing gas.

[0077] Next, a second connecting layer 211 is formed within the second opening. Please refer to [link / reference needed] for the formation process of the second connecting layer 211. Figure 7 and Figure 8 .

[0078] Please refer to Figure 7 An initial second connection layer 210 is formed in the second opening 209 using a selective deposition process. The growth rate of the initial second connection layer 210 on the second device structure 202 is greater than the growth rate on the passivation layer 207.

[0079] The initial growth rate of the second interconnect layer 210 on the second device structure 202 is greater than that on the passivation layer 207. This reduces the likelihood of the second interconnect layer material also growing extensively on the first interconnect layer 206. Subsequent planarization results in a denser first interconnect layer 206 and a denser second interconnect layer, which is beneficial for improving the performance of the semiconductor structure.

[0080] The material of the initial second connection layer 210 includes a metal, including tungsten.

[0081] The process for forming the initial second interconnect layer 210 includes a selective deposition process; the parameters of the selective deposition process include a temperature range of 300°C to 400°C and a reaction gas mixture of hydrogen and tungsten hexafluoride. Because a passivation layer 207 is formed on the top surface of the first interconnect layer 206 and a barrier layer 208 is formed on the top surface of the first dielectric layer 205, the material of the first interconnect layer 206 is more difficult to grow on the surfaces of the first interconnect layer 206 and the first dielectric layer 205, thereby improving the performance of the semiconductor structure.

[0082] Please refer to Figure 8 The initial connection layer 210 is planarized until the surface of the barrier layer 208 is exposed, forming the second connection layer 211.

[0083] The method for planarizing the initial connection layer 210 includes: forming a pad layer (not shown) on the initial connection layer 210, the passivation layer 207, and the barrier layer 208; forming a buffer layer (not shown) on the pad layer; and planarizing the buffer layer, the pad layer, and the initial connection layer 210 using a chemical mechanical polishing process until the surface of the barrier layer 208 is exposed, thereby forming the second connection layer 211.

[0084] The buffer layer and the initial connection layer 210 are made of the same material.

[0085] The materials of the buffer layer and the initial connection layer 210 include metals, including tungsten.

[0086] The material of the liner layer includes one or both of a metal and a metal compound; the metal includes titanium or tantalum; the metal compound includes titanium nitride or tantalum nitride.

[0087] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figure 8 ,include:

[0088] Substrate 200, wherein a plurality of first device structures 201 are provided on the substrate and second device structures 202 located on the substrates on both sides of the first device structures 201;

[0089] A first dielectric layer 205 is located on a substrate 200. The first dielectric layer 205 has a first opening and a second opening. The first opening exposes a portion of the top surface of the first device structure 201, and the second opening exposes the top surface of the second device structure.

[0090] The first connecting layer 206 is located within the first opening;

[0091] Passivation layer 207 located on the top surface of the first connection layer 206;

[0092] The second connecting layer 211 is located within the second opening.

[0093] In this embodiment, the material of the passivation layer 207 includes a first interconnect layer 206 material containing doped ions.

[0094] In this embodiment, the doping ions include nitrogen ions.

[0095] In this embodiment, it further includes a barrier layer 208 located on the top surface of the first dielectric layer 205, the material of the barrier layer 208 comprising the first dielectric layer material containing doped ions, the barrier layer 208 exposing the surface of the passivation layer 207.

[0096] In this embodiment, the first device structure 201 includes a gate structure; the second device structure 202 includes a conductive structure.

[0097] In this embodiment, the material of the second device structure 202 includes metal, and the metal includes cobalt.

[0098] In this embodiment, the substrate 200 further includes: source and drain doped regions located in the substrates on both sides of the gate structure; the conductive structure is located on the source and drain doped regions.

[0099] In this embodiment, the substrate includes a base and a fin structure located on the base; the gate structure spans the fin structure, and the source / drain doped regions are located within the fin structures on both sides of the gate structure.

[0100] In this embodiment, the first device structure 201 further includes a capacitor, an inductor, or a resistor; the second device structure 202 further includes a capacitor, an inductor, or a resistor.

[0101] In this embodiment, the substrate also has a second dielectric layer 204, and a plurality of the first device structures 201 and the second device structures 202 are located within the second dielectric layer 204; the first dielectric layer 205 is located on the second dielectric layer 204.

[0102] In this embodiment, the material of the first connecting layer 206 includes metal, and the metal includes tungsten; the material of the second connecting layer 211 includes metal, and the metal includes tungsten.

[0103] Figure 9 This is a schematic diagram of the semiconductor structure formation process in another embodiment of the present invention.

[0104] Please refer to Figure 9 , Figure 9 In order to be in Figure 7 Based on the schematic diagram, the initial connection layer 210 and passivation layer 207 are planarized until the surface of the first dielectric layer 205 is exposed, forming the second connection layer 311.

[0105] In this embodiment, while planarizing the initial connection layer 210 and the passivation layer 207, the barrier layer 208 is also removed.

[0106] The method for planarizing the initial connection layer 210 and the passivation layer 207 includes: forming a pad layer (not shown) on the initial connection layer 210, the passivation layer 207 and the barrier layer 208; forming a buffer layer (not shown) on the pad layer; and planarizing the buffer layer, the pad layer, the initial connection layer 210, the passivation layer 207 and the barrier layer 208 using a chemical mechanical polishing process until the surface of the first dielectric layer 205 is exposed, thereby forming the second connection layer 311.

[0107] The buffer layer and the initial connection layer 210 are made of the same material.

[0108] The materials of the buffer layer and the initial connection layer 210 include metals, including tungsten.

[0109] The material of the liner layer includes one or both of a metal and a metal compound; the metal includes titanium or tantalum; the metal compound includes titanium nitride or tantalum nitride.

[0110] The material of the passivation layer 207 includes the material of the first interconnecting layer 206 containing doped ions. On the one hand, it is not necessary to form a separate passivation layer. On the other hand, the passivation layer can be removed during the planarization process, thereby simplifying the process flow.

[0111] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, wherein the substrate has a plurality of first device structures and second device structures located on substrates on both sides of the first device structures; A first dielectric layer is formed on a substrate, the first dielectric layer having a first opening that exposes a portion of the top surface of a first device structure. A first connecting layer is formed within the first opening; A passivation layer is formed on the top surface of the first connection layer; A barrier layer is formed on the top surface of the first dielectric layer, the barrier layer being formed simultaneously with the passivation layer, and the barrier layer and the passivation layer being made of different materials; After the passivation layer is formed, a second opening is formed in the first dielectric layer, and the second opening exposes part of the surface of the second device structure. A second interconnect layer is formed in the second opening using a selective deposition process. The growth rate of the second interconnect layer on the second device structure is greater than that on the passivation layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method of forming a passivation layer on the top surface of the first interconnect layer and a barrier layer on the top surface of the first dielectric layer includes: passivating the top surface of the first interconnect layer and the top surface of the first dielectric layer, forming a passivation layer on the top surface of the first interconnect layer, and forming a barrier layer on the top surface of the first dielectric layer, wherein the material of the passivation layer includes the material of the first interconnect layer containing doped ions, and the material of the barrier layer includes the material of the first dielectric layer containing doped ions.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The passivation process for the top surface of the first connecting layer includes a plasma treatment process containing doped ions.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The passivation process for the top surface of the first connection layer includes an ion implantation process containing doped ions.

5. The method for forming a semiconductor structure as described in claim 2, characterized in that, The doped ions include nitrogen ions.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the passivation layer ranges from 50 angstroms to 100 angstroms.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first connecting layer includes a metal, including tungsten.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method of forming the second interconnect layer includes: forming an initial second interconnect layer within a second opening; planarizing the initial second interconnect layer until the surface of the first dielectric layer is exposed, thereby forming the second interconnect layer.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, While planarizing the initial second connection layer, the passivation layer is also planarized.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, The material of the initial second bonding layer includes a metal, including tungsten.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The process for forming the initial second bonding layer includes a selective deposition process; the parameters of the selective deposition process include a temperature range of 300 degrees Celsius to 400 degrees Celsius and a reaction gas mixture of hydrogen and tungsten hexafluoride.

12. The method for forming a semiconductor structure as described in claim 8, characterized in that, The method for planarizing the initial second connection layer and the passivation layer includes: forming a pad layer on the initial second connection layer, the passivation layer and the first dielectric layer; forming a buffer layer on the pad layer; and planarizing the buffer layer, the pad layer and the initial second connection layer using a chemical mechanical polishing process until the surface of the first dielectric layer is exposed.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The material of the buffer layer is the same as that of the initial second connecting layer.

14. The method for forming a semiconductor structure as described in claim 12, characterized in that, The material of the liner layer includes one or both of a metal and a metal compound; the metal includes titanium or tantalum; the metal compound includes titanium nitride or tantalum nitride.

15. A semiconductor structure, characterized in that, include: A substrate having a plurality of first device structures and second device structures located on substrates on both sides of the first device structures; A first dielectric layer is located on a substrate, the first dielectric layer having a first opening and a second opening, the first opening exposing a portion of the top surface of a first device structure, and the second opening exposing the top surface of a second device structure; The first connecting layer located within the first opening; A passivation layer located on the top surface of the first connection layer; A barrier layer located on the top surface of the first dielectric layer, the barrier layer being formed synchronously with the passivation layer, the barrier layer being made of a different material than the passivation layer; The second connecting layer is located within the second opening.

16. The semiconductor structure as claimed in claim 15, characterized in that, The passivation layer material includes a first interconnect layer material containing doped ions.

17. The semiconductor structure as claimed in claim 16, characterized in that, The doped ions include nitrogen ions.

18. The semiconductor structure as claimed in claim 15, characterized in that, The barrier layer is made of a first dielectric layer material containing doped ions, and the barrier layer exposes the surface of the passivation layer.

19. The semiconductor structure as described in claim 15, characterized in that, The first device structure includes a gate structure; the second device structure includes a conductive structure.

20. The semiconductor structure as claimed in claim 19, characterized in that, The material of the second device structure includes metals, including cobalt.

21. The semiconductor structure as claimed in claim 19, characterized in that, The substrate further includes: source and drain doped regions located within the substrates on both sides of the gate structure; the conductive structure is located on the source and drain doped regions.

22. The semiconductor structure as claimed in claim 21, characterized in that, The substrate includes: a base, and a fin structure located on the base; the gate structure spans the fin structure, and the source / drain doped regions are located within the fin structures on both sides of the gate structure.

23. The semiconductor structure as described in claim 22, characterized in that, The first device structure further includes a capacitor, an inductor, or a resistor; the second device structure further includes a capacitor, an inductor, or a resistor.

24. The semiconductor structure as claimed in claim 15, characterized in that, The substrate also has a second dielectric layer, and a plurality of the first device structures and the second device structures are located within the second dielectric layer; the first dielectric layer is located on the second dielectric layer.

25. The semiconductor structure as claimed in claim 15, characterized in that, The first connecting layer is made of a metal, including tungsten; the second connecting layer is made of a metal, including tungsten.

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