Method for manufacturing a semiconductor device

Abstract

The present invention discloses a method for manufacturing a semiconductor device, which relates to the field of semiconductor technology and is used to reduce the difficulty of manufacturing a CFET device when the materials of a first channel region and a second channel region are different. The method for manufacturing a semiconductor device includes: forming a fin-shaped structure on a semiconductor substrate. The fin-shaped structure includes a first channel forming portion, a sacrificial isolation portion, and a second channel forming portion arranged in sequence. Along the width direction of the fin-shaped structure, and under the protection of a first protective layer, only the first semiconductor layer included in the second channel forming portion is laterally thinned to form recesses on both sides of the first semiconductor layer included in the second channel forming portion. A second protective layer is formed in the recess. At least the first protective layer and the first semiconductor layer included in the sacrificial isolation portion are removed in sequence. Under the protection of a third protective layer, only the second semiconductor layer included in the sacrificial isolation portion and the second semiconductor layer included in the second channel forming portion are removed. The second protective layer is then removed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] Complementary Field Effect Transistor (CFET) devices include vertically stacked NMOS (N-Metal-Oxide-Semiconductor) transistors and PMOS (P-Metal-Oxide-Semiconductor) transistors to improve the integration density of CMOS devices.

[0003] However, when the channel regions of the NMOS transistor and the PMOS transistor are made of different materials, it is difficult to manufacture the CFET device using the existing manufacturing method. Summary of the Invention

[0004] An object of the present invention is to provide a method for manufacturing a semiconductor device, which is used to reduce the manufacturing difficulty of a CFET device and improve the yield of the CFET device when the materials of the first channel region and the second channel region are different.

[0005] In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, the method comprising:

[0006] A fin structure is formed on a semiconductor substrate. The fin structure includes a first channel forming portion, a sacrificial isolation portion, and a second channel forming portion, arranged sequentially along the thickness direction of the semiconductor substrate. The sacrificial isolation portion and the second channel forming portion each include at least one stacked layer, each stacked layer including a first semiconductor layer and a second semiconductor layer located on the first semiconductor layer. The first channel forming portion includes at least one second semiconductor layer. The second semiconductor layer and the first semiconductor layer are made of different materials.

[0007] Along the width direction of the fin structure and under the protection of the first protection layer, only the first semiconductor layer included in the second channel forming portion is thinned laterally to form notches on both sides of the first semiconductor layer included in the second channel forming portion.

[0008] A second protective layer is formed in the recess. The materials of the first protective layer and the first semiconductor layer are different from the material of the second protective layer.

[0009] At least the first protection layer and the first semiconductor layer included in the sacrificial isolation part are removed in sequence, so that the second semiconductor layer included in the first channel forming part forms the first channel region included in the first transistor.

[0010] Under the protection of the third protective layer, only the second semiconductor layer included in the sacrificial isolation portion and the second semiconductor layer included in the second channel formation portion are removed, so that the first semiconductor layer included in the second channel formation portion forms the second channel region of the second transistor. The second protective layer is then removed to isolate the second channel region from the first channel region. The first transistor and the second transistor have different conductivity types.

[0011] Compared with the prior art, in the method for manufacturing a semiconductor device provided by the present invention, the fin-shaped structure formed on the semiconductor substrate includes a first channel forming portion, a sacrificial isolation portion, and a second channel forming portion. The second semiconductor layer included in the first channel forming portion is used to manufacture the first channel region included in the first transistor. Furthermore, the first semiconductor layer included in the second channel forming portion is used to manufacture the second channel region included in the second transistor. Based on this, the conductivity types of the above-mentioned first transistor and the second transistor are different, and the second channel region is formed above the first channel region. Therefore, the semiconductor device formed by the method for manufacturing a semiconductor device provided by the present invention is a CFET device. Furthermore, since the materials of the first semiconductor layer and the second semiconductor layer are different, the materials of the first channel region and the second channel region are different, thereby realizing the integration of N-type transistors and P-type transistors with heterogeneous channels in the CFET device. In addition, at least under the protection of the above-mentioned first protective layer, the second protective layer and the third protective layer, the fin-shaped structure including the above-mentioned first channel forming part, the sacrificial isolation part and the second channel forming part can be manufactured only by the first semiconductor layer and the second semiconductor layer of different materials in an alternating stacking manner, which can meet the manufacturing requirements of forming the first channel region and the second channel region, and separating the first channel region and the second channel region, thereby solving the problem in the prior art that the fin-shaped structure includes at least three semiconductor layers of different materials, making it difficult to achieve high selectivity etching between different semiconductor layers, etc., resulting in greater difficulty in manufacturing CFET devices, reducing the difficulty of integrating the above-mentioned first transistor and the second transistor, and improving the yield of the manufactured CFET device.

[0012] In addition, after the fin structure is formed on the semiconductor substrate, only the first semiconductor layer included in the second channel forming portion is subjected to a lateral thinning process along the width direction of the fin structure. After the lateral thinning process, the widths of the first semiconductor layer included in the second channel forming portion and the second semiconductor layer included in the first channel forming portion are different. Moreover, as mentioned above, the first semiconductor layer included in the second channel forming portion is a film layer for manufacturing the second channel region, and the second semiconductor layer included in the first channel forming portion is a film layer for manufacturing the first channel region. Therefore, after the lateral thinning process, the widths of the first channel region and the second channel region obtained subsequently are different. When the widths of the first channel region and the second channel region are different, the conductive areas of the first channel region and the second channel region are different. In addition, because the conductivity types of the first channel region and the second channel region are different and the materials of the first channel region and the second channel region are different, the carrier mobility of the first channel region and the second channel region is different. Based on this, only the first semiconductor layer included in the second channel forming part is laterally thinned, which can also reduce the conductive area of ​​the first channel region, which is conducive to making the operating current of the first transistor and the second transistor the same, and improving the driving performance of the CFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0014] Figure 1 A flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0015] Figures 2 to 32 Schematic diagram of the structure of the semiconductor device manufacturing process in an embodiment of the present invention.

[0016] Reference numerals: 11 is a semiconductor base, 111 is a semiconductor substrate, 112 is a strain buffer layer, 12 is a first semiconductor material layer, 121 is a first semiconductor layer, 13 is a second semiconductor material layer, 131 is a second semiconductor layer, 14 is a Fin structure, 15 is a shallow trench isolation structure, 16 is a fin structure, 161 is a first semiconductor region, 162 is a second semiconductor region, 163 is a transition region, 17 is a sacrificial gate, 18 is a sidewall, 19 is a first source / drain region, 20 is a first source / drain region, is the second source / drain region, 21 is the mask layer, 22 is the isolation dielectric layer, 23 is the source / drain formation region, 24 is the dielectric layer, 25 is the fin structure, 251 is the first channel formation part, 252 is the sacrificial isolation part, 253 is the second channel formation part, 254 is the stack, 26 is the first protective layer, 27 is the recess, 28 is the second protective layer, 29 is the first channel region, 30 is the third protective layer, 31 is the second channel region, 32 is the first gate stack structure, and 33 is the second gate stack structure. DETAILED DESCRIPTION

[0017] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0018] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0019] In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intervening layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed. To further clarify the technical problems, technical solutions, and beneficial effects to be solved by the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended solely to explain the present invention and are not intended to limit the present invention.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0021] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and may encompass internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0022] Complementary Field Effect Transistor (CFET) devices include vertically stacked NMOS (N-Metal-Oxide-Semiconductor) transistors and PMOS (P-Metal-Oxide-Semiconductor) transistors to improve the integration density of CMOS devices.

[0023] However, it is not easy to integrate NMOS transistors and PMOS transistors with different channel materials using existing manufacturing methods, which makes the manufacturing of CFET devices more difficult and affects the operating performance of CFET devices. Specifically, the following uses the example of an NMOS transistor and a PMOS transistor both being gate-all-around transistors, and the PMOS transistor being located above the NMOS transistor, to illustrate the process of manufacturing a CFET device using existing manufacturing methods: First, a fin structure is formed on a substrate. Along the height direction of the substrate, the fin structure includes at least one first stack, an isolation layer, and at least one second stack arranged in sequence. Each first stack and second stack includes a sacrificial layer and a channel layer located on the sacrificial layer. Then, a sacrificial gate and sidewalls are formed across the fin structure, and the source / drain regions included in the NMOS transistor and the source / drain regions included in the PMOS transistor are respectively formed using source / drain epitaxy or ion implantation. Then, a dielectric layer is formed covering the formed structure, the top of the dielectric layer is flush with the top of the sacrificial gate, and the sacrificial gate is removed. The sacrificial layer and the isolation layer included in the first stack and the second stack are then selectively removed, so that the portion of the channel layer included in the first stack located in the gate formation region forms the nanowire or sheet included in the NMOS transistor, and the portion of the channel layer included in the second stack located in the gate formation region forms the nanowire or sheet included in the PMOS transistor.

[0024] It can be seen from the above manufacturing process that because the NMOS transistor and the PMOS transistor have different channel materials, the channel layers included in the first stack and the second stack are made of different materials. In addition, in order to obtain the nanowires or sheets included in the NMOS transistor and the PMOS transistor, the materials of the sacrificial layer included in the first stack and the sacrificial layer included in the second stack are required to be different from the materials of the channel layer included in the first stack and the channel layer included in the second stack, respectively. At the same time, in order to isolate the nanowires or sheets included in the NMOS transistor from the nanowires or sheets included in the PMOS transistor, the material of the isolation layer needs to be different from the material of the channel layer included in the first stack and the channel layer included in the second stack. Obviously, in order to achieve high selectivity etching between the above-mentioned multiple semiconductor materials, the integration of the above-mentioned NMOS transistor and PMOS transistor is more difficult and the process complexity is higher, which in turn leads to a reduction in the yield of the CFET device and affects the working performance of the CFET device.

[0025] To address the above technical issues, embodiments of the present invention provide a method for manufacturing a semiconductor device. In this method, at least under the protection of a first protective layer, a second protective layer, and a third protective layer, a fin-shaped structure comprising a first channel-forming portion, a sacrificial isolation portion, and a second channel-forming portion can be fabricated solely by alternating first and second semiconductor layers of different materials, thereby reducing the integration difficulty of the first and second transistors and improving the yield of the fabricated CFET device.

[0026] like Figure 1 As shown, an embodiment of the present invention provides a method for manufacturing a semiconductor device. The semiconductor device is a CFET device. Specifically, as Figure 32 As shown, the semiconductor device includes a first transistor formed on a semiconductor substrate 11, and a second transistor formed above the first transistor and spaced apart from the first transistor. The first transistor and the second transistor have different conductivity types. The first transistor can be a P-type transistor, in which case the second transistor is an N-type transistor. Alternatively, the first transistor can be an N-type transistor, in which case the second transistor is a P-type transistor.

[0027] The following will be based on Figures 2 to 32 The manufacturing process is described by a cross-sectional view or a stereoscopic view of the operation shown. Specifically, the manufacturing method of the semiconductor device includes:

[0028] like Figure 22 and Figure 23As shown, first, a fin structure 25 is formed on a semiconductor substrate 11. Along the thickness direction of the semiconductor substrate 11, the fin structure 25 includes a first channel forming portion 251, a sacrificial isolation portion 252, and a second channel forming portion 253, which are arranged in sequence. The sacrificial isolation portion 252 and the second channel forming portion 253 each include at least one stacked layer 254, each stacked layer 254 including a first semiconductor layer 121 and a second semiconductor layer 131 located on the first semiconductor layer 121. The first channel forming portion 251 includes at least one second semiconductor layer 131. The second semiconductor layer 131 and the first semiconductor layer 121 are made of different materials.

[0029] Specifically, the semiconductor substrate may be a semiconductor substrate without any structure formed thereon. For example, the semiconductor substrate may be a silicon substrate, a silicon-on-insulator substrate, a silicon-germanium substrate, or a germanium substrate. Alternatively, the semiconductor substrate may also be a semiconductor substrate with some structures formed thereon. For example, Figure 2 As shown, the semiconductor base 11 may include a semiconductor substrate 111 and a strain buffer layer 112 formed on the semiconductor substrate 111. In this case, during the process of manufacturing the semiconductor device, the presence of the strain buffer layer 112 can provide stress to the first semiconductor layer and the second semiconductor layer. In addition, the second semiconductor layer included in the first channel forming portion is used to manufacture the first channel region included in the first transistor, and the first semiconductor layer included in the second channel forming portion is used to manufacture the second channel region included in the second transistor. Therefore, the presence of the strain buffer layer 112 can improve the carrier mobility of the first channel region and the second channel region, and improve the driving performance of the manufactured semiconductor device. The material of the above-mentioned strain buffer layer 112 can be germanium silicon. Specifically, the content and thickness of germanium in the above-mentioned strain buffer layer 112 can be set according to the actual application scenario, and are not specifically limited here.

[0030] For the above-mentioned fin structure, as mentioned above, the second semiconductor layer in the first channel forming portion included in the fin structure is a film layer used to form the first channel region. Therefore, the number and thickness of the second semiconductor layer included in the first channel forming portion can be determined according to the specific structure of the first channel region in the actual application scenario. For example: Figure 3 and Figure 23 As shown, in the case where the first transistor is a gate-all-around transistor and the first channel region includes two layers of nanowires or sheets, the first channel forming portion 251 includes two layers of second semiconductor layers 131 spaced apart. Figure 4 and Figure 5 As shown, in the case where the first transistor is a fin field effect transistor, the first channel forming portion 251 includes a second semiconductor layer 131 with a relatively large thickness.

[0031] In addition, if Figure 23As shown, when the first transistor is a gate-all-around transistor, the first channel forming portion 251 includes at least one stacked layer 254. In this case, the first channel forming portion 251 also includes at least one first semiconductor layer 121. The first semiconductor layer 121 included in the first channel forming portion 251 is used to form a gap between two adjacent layers of nanowires or nanosheets in the first channel region. Therefore, the number and thickness of the first semiconductor layer 121 included in the first channel forming portion 251 can be determined based on the structure of the first channel region in actual application scenarios.

[0032] Similarly, since the first semiconductor layer in the second channel forming portion included in the fin structure is a film layer used to manufacture the second channel region, the number of stacked layers included in the second channel forming portion and the thickness of each first semiconductor layer can be determined according to the specific structure of the second channel region in the actual application scenario. For example: Figure 3 and Figure 23 As shown, in the case where the second transistor is a gate-all-around transistor and the second channel region includes two layers of nanowires or sheets, the second channel forming portion 253 includes two stacked layers 254. For another example: Figure 5 As shown, when the second transistor is a ring-gate transistor and the size ratio of the second channel region is similar to the size ratio of the channel region included in the fin field effect transistor, the second channel forming portion 253 includes a stacked layer 254, and the thickness of the first semiconductor layer 121 included in the stacked layer 254 is relatively large.

[0033] Furthermore, the second semiconductor layer in the second channel-forming portion is used to protect the first semiconductor layer included in the second channel-forming portion before forming the second channel region. Furthermore, when the second channel region includes two layers of nanowires or nanosheets, the second semiconductor layer also serves to form a gap between two adjacent layers of nanowires or nanosheets in the second channel region. Therefore, the number and thickness of the second semiconductor layer included in the second channel-forming portion can be determined based on the structure of the second channel region in actual application scenarios.

[0034] As for the sacrificial isolation portion included in the fin structure, such as Figures 23 to 30 As shown, the sacrificial isolation portion 252 is used to form a gap separating the first channel region 29 and the second channel region 31. Based on this, the number of layers of the stack 254 included in the sacrificial isolation portion 252 and the thickness of the first semiconductor layer 121 and the second semiconductor layer 131 in the sacrificial isolation portion 252 can be determined according to the spacing between the first channel region 29 and the second channel region 31 in the actual application scenario, and are not specifically limited here.

[0035] For the above-mentioned stack, the material of the first semiconductor layer included in the stack can be a semiconductor material such as silicon, silicon-germanium, germanium or Group III-V semiconductor materials. The material of the second semiconductor layer can be any semiconductor material different from the material of the first semiconductor layer. The specific materials of the first semiconductor layer and the second semiconductor layer can be set according to the conductivity type of the first transistor and the second transistor, as well as actual needs. For example: when the first transistor is a P-type transistor and the second transistor is an N-type transistor, the material of the first semiconductor layer can be Si and the material of the second semiconductor layer can be Ge, so as to improve the carrier mobility of the first channel region formed based on the second semiconductor layer included in the first channel forming portion, thereby improving the driving performance of the first transistor.

[0036] In addition, the different materials of the first semiconductor layer and the second semiconductor layer may mean that the elements included in the material of the first semiconductor layer are completely different or not completely the same as the elements included in the material of the second semiconductor layer. For example, the material of the first semiconductor layer may be Si, and the material of the second semiconductor layer may be Ge. For another example, the material of the first semiconductor layer may be Si, and the material of the second semiconductor layer may be Si. 0.5 Ge 0.5 .

[0037] Alternatively, it may also mean that the material of the first semiconductor layer includes the same elements as the material of the second semiconductor layer, but the stoichiometric ratios of the elements are different. For example, the material of the first semiconductor layer may be Si 0.8 Ge 0.2 The material of the second semiconductor layer can be Si 0.3 Ge 0.7 .

[0038] In actual applications, a replacement gate process is generally used to form the first gate stack structure included in the first transistor and the second gate stack structure included in the second transistor to improve the formation quality of the first gate stack structure and the second gate stack structure. In this case, the above-mentioned formation of the fin structure on the semiconductor substrate may include the following steps:

[0039] like Figure 8 As shown, a fin-shaped structure 16 is formed on a semiconductor substrate 11. Along the length direction of the fin-shaped structure 16, the fin-shaped structure 16 includes a first semiconductor region 161, a second semiconductor region 162, and a transition region 163 located between the first semiconductor region 161 and the second semiconductor region 162.

[0040] Specifically, the portion of the fin-shaped structure located in the transition region is used to form the above-mentioned fin-shaped structure. Based on this, for example, Figures 3 to 5As shown, a process such as epitaxial growth can be used to form alternating first and second semiconductor material layers 12 and 13 on the semiconductor substrate 11 along the thickness direction of the semiconductor substrate 11. The first semiconductor material layer 12 is a film layer used to form the first semiconductor layer, and the second semiconductor material layer 13 is a film layer used to form the second semiconductor layer. Therefore, the distribution of the first and second semiconductor material layers 12 and 13 on the semiconductor substrate 11 can be determined based on the distribution of the first and second semiconductor layers in the fin structure.

[0041] For example: Figure 3 As shown, in the case where the above-mentioned first channel forming part and the second channel forming part both include two stacked layers, and the sacrificial isolation part includes a single stacked layer, it is necessary to form five layers of the above-mentioned first semiconductor material layer 12 and five layers of the above-mentioned second semiconductor material layer 13 on the semiconductor substrate 11, wherein the film layer located on the top layer is the second semiconductor material layer 13, and the film layer located on the bottom layer is the first semiconductor material layer 12.

[0042] Another example: Figure 4 and Figure 5 As shown, when the first channel forming portion includes only one second semiconductor layer, and the sacrificial isolation portion and the second channel forming portion each include a stacked layer, three layers of the first semiconductor material layer 12 and two layers of the second semiconductor material layer 13 need to be formed on the semiconductor substrate 11. The two different layers of the second semiconductor material 13 are located at the top and bottom layers, respectively.

[0043] Then, if Figure 6 As shown, a process such as photolithography and etching can be used to etch from the second semiconductor material layer at the top layer downward to the semiconductor substrate 11 to form a Fin structure 14 on the semiconductor substrate 11. The cross-sectional shape of the Fin structure 14 can be rectangular. At this time, along the length direction of the Fin structure 14, the width of each part of the Fin structure 14 is the same. Alternatively, as shown in FIG. Figure 7 As shown, the width of the edge portions of the Fin structure 14 along the length direction can be greater than the width of the middle portion thereof, so as to provide sufficient support for the second semiconductor layer included in the first channel formation portion and the first semiconductor layer included in the second channel formation portion when the first channel region and the second channel region are subsequently formed, thereby improving the yield of the semiconductor device. The shape of the edge portions of the Fin structure 14 along the length direction can be a diamond, a circle, or other shape, which is not specifically limited here.

[0044] Then, if Figure 8As shown, a shallow trench isolation structure 15 can be formed on the portion of the semiconductor substrate 11 exposed outside the Fin structure using processes such as chemical vapor deposition and etching to isolate the manufactured semiconductor device from other conductive structures formed on the semiconductor substrate 11. The top height of the shallow trench isolation structure 15 is less than or equal to the bottom height of the underlying film layer in all first and second semiconductor material layers. The shallow trench isolation structure 15 can be made of an insulating material such as SiN, Si3N4, SiO2, or SiCO. The portion of the Fin structure exposed outside the shallow trench isolation structure 15 is the aforementioned fin strip structure 16.

[0045] like Figure 9 As shown, after obtaining the above-mentioned fin-shaped structure 16, a sacrificial gate 17 can be formed on the semiconductor substrate 11 by using processes such as chemical vapor deposition and etching. The sacrificial gate 17 spans the transition region included in the fin-shaped structure 16. The material of the sacrificial gate 17 can be a material that is easy to remove, such as polysilicon.

[0046] For example, Figure 10 and Figure 11 As shown, after forming the sacrificial gate 17, chemical vapor deposition and etching processes can be used to form sidewalls 18 at least on both sides of the sacrificial gate 17 along the length direction to isolate the subsequently formed first gate stack structure and second gate stack structure from other conductive structures, thereby improving the electrical stability of the semiconductor device. The length direction of the sacrificial gate 17 is parallel to the length direction of the fin-shaped structure 16. The thickness of the sidewall 18 can be set according to actual needs and is not specifically limited here. The material of the sidewall 18 can be an insulating material such as silicon oxide or silicon nitride.

[0047] For example, after forming a sacrificial gate on a semiconductor substrate, before performing subsequent operations, such as Figure 16 and Figure 20 As shown, the portions of the fin-shaped structure 16 located on both sides of the first channel forming portion can be processed to form the first source / drain region 19 included in the first transistor; and the portions of the fin-shaped structure 16 located on both sides of the second channel forming portion can be processed to form the second source / drain region 20 included in the second transistor. Specifically, the order of forming the first source / drain region 19 and the second source / drain region 20 can be determined according to the processing technology used. Based on this, the formation of the first source / drain region 19 and the second source / drain region 20 can be divided into at least the following two situations according to the different processing technologies used:

[0048] The first method is to form the first source / drain region and the second source / drain region by using source / drain epitaxy. Based on this, the above-mentioned processing of the portion of the fin-shaped structure located on both sides of the first channel forming portion and the processing of the portion of the fin-shaped structure located on both sides of the second channel forming portion may include the following steps: Figure 12 As shown, the portion of the fin-shaped structure located in the first semiconductor region and the second semiconductor region is removed. Figure 14 As shown, epitaxial growth and etching processes are used to form first source / drain regions 19 on both sides of the first channel forming portion along the length direction. Figure 15 As shown, an isolation dielectric layer 22 is formed on the first source / drain region 19. Figure 16 As shown, an epitaxial growth process is used to form second source / drain regions 20 on the isolation dielectric layer 22 and on both sides of the second channel forming portion along the length direction.

[0049] Specifically, the portion of the fin structure located in the first semiconductor region and the second semiconductor region can be removed by wet etching or dry etching under the masking effect of the sacrificial gate and the sidewall, and the structure formed is as follows: Figure 12 As shown. Figure 13 As shown, epitaxial growth and other processes are then used on the semiconductor substrate 11 to form source / drain epitaxial materials on both sides of the transition region 163. Figure 14 As shown, the source / drain epitaxial material is then etched back using an etching process so that the remaining source / drain epitaxial material forms the first source / drain region 19. Figure 15 As shown, a process such as chemical vapor deposition can be used to form an isolation dielectric layer 22 on the first source / drain region 19 to isolate the first source / drain region 19 from the second source / drain region formed subsequently. The thickness of the isolation dielectric layer 22 can be set according to actual needs and is not specifically limited here. The material of the isolation dielectric layer 22 can be an insulating material such as silicon oxide or silicon nitride. Finally, as Figure 16 As shown, the second source / drain region 20 may be formed by an epitaxial growth process.

[0050] The second method is to form the first source / drain region and the second source / drain region by ion implantation. Based on this, the above-mentioned processing of the portion of the fin-shaped structure located on both sides of the first channel forming portion and the processing of the portion of the fin-shaped structure located on both sides of the second channel forming portion include: Figure 17 As shown, the ion implantation process is used to process the portion of the fin strip structure 16 located on both sides of the second channel forming portion to at least form the second source / drain region 20. Figure 18 As shown, a mask layer 21 is formed on the second source / drain region 20. The mask layer 21 is used to expose the portion of the fin strip structure 16 located on the source / drain formation region 23. The source / drain formation region 23 corresponds to the region where the first source / drain region 19 is located. Figure 19 As shown, at least under the masking effect of the sacrificial gate 17 and the mask layer 21, the portion of the fin strip structure 16 located on the source / drain formation region 23 is selectively removed. Figure 20As shown, at least under the masking function of the sacrificial gate 17 and the mask layer 21, the portion of the fin strip structure 16 located in the source / drain formation region is processed by ion implantation to form the first source / drain region 19. Finally, the mask layer is removed.

[0051] Specifically, under the masking effect of the sacrificial gate and the sidewall, Figure 17 As shown, the ion implantation process is used to process the portion of the fin strip structure 16 located on both sides of the second channel forming portion to form the second source / drain region 20, and the portion of the fin strip structure 16 located on the source / drain forming region 23 is doped with conductive particles. Figure 18 As shown, a mask layer 21 is formed on the second source / drain region 20. The mask layer 21 can be a photoresist mask layer or a spin-on hard mask layer. The formation process of the mask layer 21 can be determined according to the material of the mask layer 21. For example, when the mask layer 21 is a photoresist mask layer, the mask layer 21 can be formed by processes such as photolithography and etching. Figure 19 As shown, then, under the masking action of at least the sacrificial gate 17 and the mask layer 21 (including the sidewall spacer 18 when the sidewall spacer 18 is formed), the portion of the fin strip structure 16 located on the source / drain formation region 23 is selectively removed to expose the portion of the fin strip structure 16 where the second source / drain region 20 is to be formed, that is, to expose the source / drain formation region 23. Figure 20 As shown, under the masking effect of at least the sacrificial gate 17 and the mask layer 21, an ion implantation process is used to process the portion of the fin structure 16 located in the source / drain formation region to form a first source / drain region 19. Finally, the mask layer can be removed by a wet etching or dry etching process.

[0052] like Figure 21 As shown, a dielectric layer 24 can be formed on the semiconductor substrate 11 by using processes such as chemical vapor deposition and chemical mechanical polishing. The dielectric layer 24 covers the semiconductor substrate 11, and the top of the dielectric layer 24 is flush with the top of the sacrificial gate 17. The dielectric layer 24 can be made of an insulating material such as silicon oxide.

[0053] like Figure 22 and Figure 23 As shown, a wet etching or dry etching process can be used to remove the sacrificial gate under the mask of the dielectric layer 24. The portion of the fin strip structure located in the transition region forms a fin structure 25. In addition, Figure 22 It is a structural cross-sectional view along the length direction of the fin-shaped structure 25. Figure 23 It is a structural cross-sectional view along the width direction of the fin structure 25.

[0054] like Figure 24As shown, after the fin structure 25 is formed, a first protective layer 26 can be formed on at least two sides of the fin structure 25 along the width direction by using processes such as chemical vapor deposition and etching. The top height of the first protective layer 26 is less than the bottom height of the second semiconductor layer 131 located at the bottom layer in the second channel forming portion 253, and is greater than the top height of the second semiconductor layer 131 located at the top layer in the sacrificial isolation portion 252. In addition, the material of the first protective layer 26 can be set according to actual needs and is not specifically limited here. For example, the material of the first protective layer 26 may include at least one of silicon oxide, silicon nitride, and silicon oxycarbide.

[0055] like Figure 25 As shown, then along the width direction of the fin structure 25 and under the protection of the first protective layer 26, only the first semiconductor layer 121 included in the second channel forming portion 253 is laterally thinned to form recesses 27 on both sides of the first semiconductor layer 121 included in the second channel forming portion 253.

[0056] Exemplarily, a process such as wet etching or dry etching can be used, and under the protection of the first protective layer, only the first semiconductor layer included in the second channel forming portion is subjected to a lateral thinning process. The etchant used in the etching process can be determined according to the material of the first semiconductor layer and the second semiconductor layer. For example, when the material of the first semiconductor layer is Si and the material of the second semiconductor layer is Ge, the lateral thinning process can be performed using a tetramethylammonium hydroxide (TMAH) solution. Because the etchant only has an etching effect on the first semiconductor layer included in the second channel forming portion, and does not affect or has a small effect on the second semiconductor layer included in the second channel forming portion, notches are formed on both sides of the first semiconductor layer included in the second channel forming portion after the lateral thinning process.

[0057] The remaining width of each first semiconductor layer included in the second channel forming portion after the above-mentioned lateral thinning process can be determined based on the conductivity type of the second transistor in the actual application scenario, the operating current of the second transistor, and other requirements, and is not specifically limited here. For example, when the second transistor is an NMOS transistor and the first transistor is a PMOS transistor, and the operating currents of the first transistor and the second transistor are equal, the remaining width of each first semiconductor layer included in the second channel forming portion after the above-mentioned lateral thinning process is equal to half the width of the second semiconductor layer.

[0058] like Figure 26As shown, chemical vapor deposition and etching processes can be used to form a second protective layer 28 within the recess. The materials of the first protective layer 26 and the first semiconductor layer 121 are different from those of the second protective layer 28. This prevents the second protective layer 28 from being removed along with the first protective layer 26. This ensures that the second protective layer 28 can protect the first semiconductor layer 121 included in the second channel forming portion 253 from being affected during the subsequent removal of at least the first semiconductor layer 121 included in the sacrificial isolation portion 252. Furthermore, this prevents the subsequent removal of at least a portion of the first semiconductor layer 121 included in the second channel forming portion 253 from being removed along with the second protective layer 28, thereby improving the precision of the second channel region formed based on the first semiconductor layer 121 included in the second channel forming portion 253.

[0059] Specifically, the material of the second protective layer can be set according to the actual application scenario, as long as it can be applied to the semiconductor device manufacturing method provided by the embodiment of the present invention. For example, the material of the second protective layer can be silicon germanium, germanium, silicon oxide, silicon nitride, or silicon oxycarbide.

[0060] like Figure 27 and Figure 28 As shown, at least the first protection layer and the first semiconductor layer 121 included in the sacrificial isolation part 252 are removed in sequence, so that the second semiconductor layer 131 included in the first channel forming part 251 forms the first channel region 29 included in the first transistor.

[0061] Specifically, such as Figure 27 As shown, the first protective layer can be removed by dry etching or wet etching to expose the sacrificial isolation portion 252 and the first channel forming portion 251. Then, the formation process of the first channel region included in the first transistor is determined according to the device type of the first transistor.

[0062] For example, when the first transistor is a fin field-effect transistor, the first channel-forming portion comprises only the second semiconductor layer. Therefore, after removing the first protective layer, the exposed first semiconductor layer only belongs to the sacrificial isolation portion. In this case, by removing only the first semiconductor layer in the sacrificial isolation portion, the second semiconductor layer in the first channel-forming portion can be formed into the first channel region.

[0063] For another example: when the first transistor is a gate-all-around transistor, Figure 23 As shown, the first channel forming portion 251 includes at least one stacked layer 254. Based on this, as shown in FIG. Figure 27 As shown, after the first protective layer is removed, the first semiconductor layer 121 included in the sacrificial isolation portion 252 and the first semiconductor layer 121 included in the first channel forming portion 251 are exposed. Figure 28As shown, the first semiconductor layer 121 included in the sacrificial isolation portion 252 and the first semiconductor layer 121 included in the first channel forming portion need to be removed to obtain the first channel region 29 .

[0064] like Figure 29 As shown, chemical vapor deposition and etching processes can then be used to form a third protective layer 30 at least on both sides of the fin structure 25 along the width direction. The top height of the third protective layer 30 is greater than the top height of the second semiconductor layer 131 located at the top layer in the first channel region 29, and is less than the bottom height of the second semiconductor layer 131 located at the bottom layer in the sacrificial isolation portion 252. The material of the third protective layer 30 can be set according to the actual application scenario, as long as it can be applied to the manufacturing method of the semiconductor device provided by the embodiment of the present invention. For example, the material of the third protective layer 30 includes at least one of silicon oxide, silicon nitride and silicon oxycarbide.

[0065] like Figure 30 As shown, under the protection of the third protective layer 30, only the second semiconductor layer included in the sacrificial isolation portion and the second semiconductor layer included in the second channel formation portion are removed, so that the first semiconductor layer included in the second channel formation portion forms the second channel region 31 included in the second transistor. The second protective layer is also removed to isolate the second channel region 31 from the first channel region 29.

[0066] Specifically, under the protection of the third protection layer, the removal order of the second semiconductor layer included in the sacrificial isolation part, the second semiconductor layer included in the second channel forming part, and the second protection layer can be set according to actual needs.

[0067] For example, under the protection of the third protective layer, wet etching or dry etching can be used to first remove the second semiconductor layer included in the sacrificial isolation portion and the second semiconductor layer included in the second channel forming portion, and then remove the second protective layer.

[0068] For another example, under the protection of the third protection layer, wet etching or dry etching can be used to first remove the second protection layer, and then the second semiconductor layer included in the sacrificial isolation portion and the second semiconductor layer included in the second channel forming portion are removed.

[0069] like Figure 31 As shown, after the second channel region 31 is formed and the second channel region 31 is isolated from the first channel region 29 , the third protection layer may be removed by a wet etching process or a dry etching process.

[0070] like Figure 32As shown, a process such as atomic layer deposition can be used to form a first gate stack structure 32 on the periphery of the first channel region 29, and a second gate stack structure 33 on the periphery of the second channel region 31. The material of the first gate dielectric layer included in the first gate stack structure 32 can be the same as or different from the material of the second gate dielectric layer included in the second gate stack structure 33. The material of the first work function layer included in the first stack structure can be the same as or different from the material of the second work function layer included in the second gate stack structure 33. Specifically, the specific materials of the first gate stack structure 32 and the second gate stack structure 33 can be set according to actual needs and are not specifically limited here.

[0071] In actual application, when the materials of the first gate dielectric layer and the first work function layer included in the first gate stack structure are respectively the same as the materials of the second gate dielectric layer and the second work function layer included in the second gate stack structure, the first gate stack structure and the second gate stack structure can be formed simultaneously.

[0072] When the material of the first gate dielectric layer included in the first gate stack structure is the same as the material of the second gate dielectric layer included in the second gate stack structure, and the first work function layer included in the first gate stack structure includes the second work function layer included in the second gate stack structure, the first gate dielectric layer and the second gate dielectric layer can be formed simultaneously by an atomic layer deposition process. Then, a first work function material layer is formed on the first gate dielectric layer and the second gate dielectric layer at the same time, and a filling layer is formed to fill the gate formation area. The top height of the filling layer is greater than the maximum top height of the first work function material layer formed on the first gate dielectric layer, and less than the minimum bottom height of the first work function material layer formed on the second gate dielectric layer. Then, under the masking action of the filling layer, the first work function material layer located on the second gate dielectric layer is removed. The filling layer is then removed, and a second work function material layer is formed on the remaining first work function material layer and the second gate dielectric layer by a process such as atomic layer deposition. The second work function material layer formed on the second gate dielectric layer is the second work function layer. The remaining first work function material layer and the second work function material layer formed on its surface constitute the first work function layer.

[0073] It should be noted that the first gate stack structure and the second gate stack structure can be formed in a variety of ways. How to form the first gate stack structure and the second gate stack structure is not a key feature of the present invention. Therefore, in this specification, only a brief description is given to facilitate implementation of the present invention by those skilled in the art. Those skilled in the art can readily conceive of other ways to fabricate the above-mentioned structure.

[0074] From the above content, it can be seen that in the method for manufacturing a semiconductor device provided by the embodiment of the present invention, if Figures 23 to 32As shown, the fin structure 25 formed on the semiconductor substrate 11 includes a first channel forming portion 251, a sacrificial isolation portion 252, and a second channel forming portion 253. Among them, the second semiconductor layer 131 included in the first channel forming portion is used to manufacture the first channel region 29 included in the first transistor. In addition, the first semiconductor layer 121 included in the second channel forming portion is used to manufacture the second channel region 31 included in the second transistor. Based on this, the conductivity types of the above-mentioned first transistor and the second transistor are different, and the second channel region 31 is formed above the first channel region 29. Therefore, the semiconductor device formed by the semiconductor device manufacturing method provided in the embodiment of the present invention is a CFET device. In addition, because the materials of the first semiconductor layer 121 and the second semiconductor layer 131 are different, the materials of the first channel region 29 and the second channel region 31 are different, thereby realizing the integration of N-type transistors and P-type transistors with heterogeneous channels in the CFET device. In addition, under the protection of the above-mentioned first protective layer 26, the second protective layer 28 and the third protective layer 30, the fin-shaped structure 25 including the first channel forming part 251, the sacrificial isolation part 252 and the second channel forming part 253 can be manufactured only by the first semiconductor layer 121 and the second semiconductor layer 131 of different materials in an alternating stacking manner, which can meet the manufacturing requirements of forming the first channel region 29 and the second channel region 31, and separating the first channel region 29 and the second channel region 31, thereby solving the problem in the prior art that the fin-shaped structure 25 includes at least three semiconductor layers of different materials, making it difficult to achieve high selectivity etching between different semiconductor layers, resulting in greater difficulty in manufacturing CFET devices, reducing the difficulty of integrating the above-mentioned first transistor and the second transistor, and improving the yield of the manufactured CFET device.

[0075] In addition, after the fin-shaped structure is formed on the semiconductor substrate, only the first semiconductor layer included in the second channel forming portion is subjected to a lateral thinning process along the width direction of the fin-shaped structure. After the lateral thinning process, the widths of the first semiconductor layer included in the second channel forming portion and the second semiconductor layer included in the first channel forming portion are different. Moreover, the first semiconductor layer included in the second channel forming portion is a film layer for manufacturing the second channel region, and the second semiconductor layer included in the first channel forming portion is a film layer for manufacturing the first channel region. Therefore, after the lateral thinning process, the widths of the first channel region and the second channel region obtained subsequently are different. Figure 32As shown, when the widths of the first channel region 29 and the second channel region 31 are different, the conductive areas of the first channel region 29 and the second channel region 31 are different. In addition, because the first channel region 29 and the second channel region 31 have different conductivity types and are made of different materials, the carrier mobility of the first channel region 29 and the second channel region 31 is different. Based on this, only the first semiconductor layer included in the second channel formation portion is laterally thinned, which can also reduce the conductive area of ​​the first channel region 29, thereby facilitating the equalization of the operating currents of the first and second transistors.

[0076] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0077] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: forming a fin structure on a semiconductor substrate; Along the thickness direction of the semiconductor substrate, the fin structure includes a first channel forming portion, a sacrificial isolation portion, and a second channel forming portion arranged in sequence; the sacrificial isolation portion and the second channel forming portion each include at least one stacked layer, each stacked layer including a first semiconductor layer and a second semiconductor layer located on the first semiconductor layer; the first channel forming portion includes at least one second semiconductor layer; the second semiconductor layer and the first semiconductor layer are made of different materials; Along the width direction of the fin structure and under the protection of the first protection layer, only the first semiconductor layer included in the second channel formation portion is thinned laterally to form notches on both sides of the first semiconductor layer included in the second channel formation portion; forming a second protective layer in the recess; the materials of the first protective layer and the first semiconductor layer are different from the material of the second protective layer; removing at least the first protection layer and the first semiconductor layer included in the sacrificial isolation portion in sequence, so that the second semiconductor layer included in the first channel forming portion forms a first channel region included in the first transistor; Under the protection of the third protective layer, only the second semiconductor layer included in the sacrificial isolation part and the second semiconductor layer included in the second channel forming part are removed, so that the first semiconductor layer included in the second channel forming part forms the second channel region included in the second transistor; and the second protective layer is removed to isolate the second channel region from the first channel region; the first transistor and the second transistor have different conductivity types.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The first transistor is a fin field effect transistor; the first channel forming portion includes a second semiconductor layer.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The first transistor is a gate-all-around transistor; the first channel forming portion includes at least one layer of the stacked layer; The sequentially removing at least the first protection layer and the first semiconductor layer included in the sacrificial isolation portion comprises: removing the first protective layer; The first semiconductor layer included in the sacrificial isolation portion and the first semiconductor layer included in the first channel formation portion are removed.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: The forming of the fin structure on the semiconductor substrate comprises: forming a fin-shaped structure on the semiconductor substrate; along the length direction of the fin-shaped structure, the fin-shaped structure includes a first semiconductor region, a second semiconductor region, and a transition region located between the first semiconductor region and the second semiconductor region; forming a sacrificial gate on the semiconductor substrate; the sacrificial gate spanning over a transition region included in the fin-shaped structure; forming a dielectric layer on the semiconductor substrate; the dielectric layer covers the semiconductor substrate, and the top of the dielectric layer is flush with the top of the sacrificial gate; The sacrificial gate is removed; and the portion of the fin-shaped structure located in the transition region forms the fin-shaped structure.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: After forming the sacrificial gate on the semiconductor substrate and before forming the dielectric layer on the semiconductor substrate, the method for manufacturing the semiconductor device further includes: The portions of the fin-shaped structure located on both sides of the first channel forming portion are processed to form first source / drain regions included in the first transistor; and the portions of the fin-shaped structure located on both sides of the second channel forming portion are processed to form second source / drain regions included in the second transistor.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: Processing the portion of the fin-shaped structure located on both sides of the first channel forming portion and processing the portion of the fin-shaped structure located on both sides of the second channel forming portion includes: removing portions of the fin-shaped structure located in the first semiconductor region and the second semiconductor region; forming the first source / drain regions on both sides of the first channel forming portion along the length direction by using an epitaxial growth process and an etching process; forming an isolation dielectric layer on the first source / drain region; The second source / drain regions are formed on the isolation dielectric layer and on both sides of the second channel forming portion along the length direction by adopting an epitaxial growth process.

7. The method for manufacturing a semiconductor device according to claim 5, wherein: Processing the portion of the fin-shaped structure located on both sides of the first channel forming portion and processing the portion of the fin-shaped structure located on both sides of the second channel forming portion includes: Using an ion implantation process to process the portion of the fin-shaped structure located on both sides of the second channel forming portion to at least form the second source / drain region; forming a mask layer on the second source / drain region, wherein the mask layer is used to expose a portion of the fin-shaped structure located on a source / drain formation region corresponding to a region where the first source / drain region is located; Under the masking effect of the mask layer, selectively removing the portion of the fin-shaped structure located on the source / drain formation region; Under the masking effect of the mask layer, an ion implantation process is used to process the portion of the fin strip structure located in the source / drain formation region to form the first source / drain region; The mask layer is removed.

8. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: The material of the first protective layer or the third protective layer includes at least one of silicon oxide, silicon nitride and silicon oxycarbide.

9. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: The second protective layer is made of silicon germanium, germanium, silicon oxide, silicon nitride or silicon oxycarbide.

10. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: The operating currents of the first transistor and the second transistor are equal.

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