Semiconductor structure and method of forming a semiconductor structure

Abstract

A semiconductor structure and a method of forming the same. The method includes providing a substrate including a first region and a second region, the substrate having a first dielectric layer and a first conductive structure in the first dielectric layer on the first region; forming a first barrier layer on the first dielectric layer; forming a resistive layer on the first barrier layer of the second region; forming a second barrier layer and a second dielectric layer on the resistive layer and the first barrier layer; etching the second dielectric layer to form an initial first opening exposing a surface of the first barrier layer on the first conductive structure and a second opening exposing a surface of the resistive layer; performing an enhancement process on the exposed resistive layer to form an enhancement layer; removing the first barrier layer to form a first opening exposing a top surface of the first conductive structure, the removal process having a removal rate of the first barrier layer greater than a removal rate of the enhancement layer; and forming an electrical connection layer in the first opening and the second opening. The semiconductor structure formed by the method has improved performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the semiconductor structure. Background Technology

[0002] Metal interconnect structures are indispensable in semiconductor devices, used to interconnect active regions, transistors, or different layers of metal lines to achieve signal transmission and control. Therefore, the formation of metal interconnect structures has a significant impact on the performance and manufacturing cost of semiconductor devices during semiconductor manufacturing. To increase device density, the size of semiconductor devices in integrated circuits has been continuously reduced. To achieve electrical connections between these semiconductor devices, multi-layer interconnect structures are typically required.

[0003] Generally, in the back-end interconnect process of semiconductor device manufacturing, the first conductive layer (M1) needs to form an electrical connection with the underlying active device structure (including source / drain regions and gate structure regions). Therefore, before forming the first conductive layer, it is usually necessary to pre-form the local interconnect structure of the semiconductor device. The local interconnect structure includes: a zeroth conductive layer (MO) electrically connected to the underlying source / drain regions, and a zeroth gate conductive layer (MOG) electrically connected to the gate structure.

[0004] However, the manufacturing process of semiconductor structures with local interconnect structures in the prior art is complex, and the performance of the resulting semiconductor structures needs to be further improved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the semiconductor structure.

[0006] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including a first region and a second region, the substrate having a first dielectric layer and a first conductive structure, the first conductive structure being located within the first dielectric layer on the first region; a first barrier layer located on the first dielectric layer; a resistive layer located on the first barrier layer in the second region; a second barrier layer located on the resistive layer and on the first barrier layer in the first region; a second dielectric layer located on the second barrier layer, the second dielectric layer having a first opening and a second opening, the first opening exposing a portion of the top surface of the first conductive structure, and the second opening exposing a portion of the top surface of the resistive layer; a reinforcement layer located within the resistive layer, the resistive layer exposing the surface of the reinforcement layer, and the thickness of the reinforcement layer being less than the thickness of the resistive layer; and an electrical connection layer located within the first opening and the second opening.

[0007] Optionally, the material of the reinforcing layer is a resistive layer material containing metallic materials.

[0008] Optionally, the metallic material includes one or more of tungsten, cobalt, cesium, ruthenium, rubidium, and molybdenum.

[0009] Optionally, the material of the resistive layer includes metal nitrides, which include one or more combinations of titanium nitride, tantalum nitride, tungsten nitride, and tungsten silicide.

[0010] Optionally, the ratio of the thickness of the reinforcing layer to the thickness of the resistive layer is in the range of 1:3 to 1:2.

[0011] Optionally, the material of the electrical connection layer includes a metal, including tungsten.

[0012] Optionally, the material of the first barrier layer is different from the material of the second dielectric layer; the material of the second barrier layer is different from the material of the second dielectric layer.

[0013] Optionally, the material of the first barrier layer includes silicon nitride, and the material of the second barrier layer includes silicon nitride.

[0014] Optionally, the first dielectric layer has a groove; the first conductive structure includes: an adhesive layer located on the sidewall surface and bottom surface of the groove, and a first conductive layer located on the adhesive layer.

[0015] Optionally, the material of the adhesion layer includes a metal nitride, such as titanium nitride; the material of the first conductive layer includes a metal, such as cobalt.

[0016] Optionally, the substrate includes: a base; a device layer on the base, the device layer including a third dielectric layer and a device structure located within the third dielectric layer, the device structure including a transistor, diode, triode, capacitor, inductor, or conductive structure; the first conductive structure is electrically connected to the device structure.

[0017] Optionally, the substrate may also have a fin structure.

[0018] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region, the substrate having a first dielectric layer and a first conductive structure, the first conductive structure being located within the first dielectric layer on the first region; forming a first barrier layer on the first dielectric layer; forming a resistive layer on the first barrier layer in the second region; forming a second barrier layer on the resistive layer and the first barrier layer in the first region; forming a second dielectric layer on the second barrier layer; etching the second dielectric layer and the second barrier layer to form an initial first opening and a second opening within the second dielectric layer and the second barrier layer, the initial first opening exposing a portion of the top surface of the first barrier layer on the first conductive structure, and the second opening exposing a portion of the top surface of the resistive layer; performing a reinforcement treatment on the exposed resistive layer to form a reinforcement layer on the surface of the resistive layer; after forming the reinforcement layer, removing the first barrier layer exposed by the initial first opening to form a first opening, the first opening exposing a portion of the top surface of the first conductive structure, the removal rate of the first barrier layer being greater than the removal rate of the reinforcement layer; and forming an electrical connection layer within the first opening and the second opening.

[0019] Optionally, the material of the reinforcing layer is a resistive layer material containing metallic materials.

[0020] Optionally, the metallic material includes one or more of tungsten, cobalt, cesium, ruthenium, rubidium, and molybdenum.

[0021] Optionally, the material of the resistive layer includes metal nitrides, which include one or more combinations of titanium nitride, tantalum nitride, tungsten nitride, and tungsten silicide.

[0022] Optionally, the process for forming the reinforcing layer includes a displacement reaction.

[0023] Optionally, the process for forming the reinforcement layer includes: an ion implantation process containing metal material ions.

[0024] Optionally, the ratio of the thickness of the reinforcing layer to the thickness of the resistive layer is in the range of 1:3 to 1:2.

[0025] Optionally, the material of the electrical connection layer includes a metal, including tungsten.

[0026] Optionally, the process of forming the electrical connection layer in the first opening and the second opening includes a selective deposition process; the parameters of the selective deposition process include: a temperature range of 300 degrees Celsius to 400 degrees Celsius, and a reaction gas of a mixture of hydrogen and tungsten hexafluoride.

[0027] Optionally, the method of forming an initial first opening and a second opening within the second dielectric layer includes: forming a transitional first opening and an initial second opening within the second dielectric layer, wherein the transitional first opening exposes a portion of the surface of the second barrier layer on the first conductive structure, and the initial second opening exposes a portion of the surface of the second barrier layer on the resistive layer; and removing the second barrier layer exposed by the transitional first opening and the initial second opening to form the initial first opening and the second opening.

[0028] Optionally, the material of the first barrier layer is different from the material of the second dielectric layer; the material of the second barrier layer is different from the material of the second dielectric layer.

[0029] Optionally, the material of the first barrier layer includes silicon nitride, and the material of the second barrier layer includes silicon nitride.

[0030] Optionally, the process for removing the second barrier layer exposed by the transition first opening and the initial second opening includes a dry etching process, wherein the etching gas in the dry etching process includes a fluorine-containing gas.

[0031] Optionally, the process for removing the first barrier layer exposed by the initial first opening includes a dry etching process, wherein the etching gas in the dry etching process includes a fluorine-containing gas.

[0032] Optionally, the first dielectric layer has a groove; the first conductive structure includes: an adhesive layer located on the sidewall surface and bottom surface of the groove, and a first conductive layer located on the adhesive layer.

[0033] Optionally, the material of the adhesion layer includes a metal nitride, such as titanium nitride; the material of the first conductive layer includes a metal, such as cobalt.

[0034] Optionally, the substrate includes: a base; a device layer on the base, the device layer including a third dielectric layer and a device structure located within the third dielectric layer, the device structure including a transistor, diode, triode, capacitor, inductor, or conductive structure; the first conductive structure is electrically connected to the device structure.

[0035] Optionally, the substrate may also have a fin structure.

[0036] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0037] The semiconductor structure formation method of this invention involves first forming an initial first opening and a second opening. The initial first opening exposes a portion of the top surface of a first barrier layer on a first conductive structure, and the second opening exposes a portion of the top surface of a resistive layer. Then, an enhancement layer is formed on the surface of the resistive layer. After forming the enhancement layer, the first barrier layer exposed by the initial first opening is removed to form the first opening. The removal rate of the first barrier layer is greater than the removal rate of the enhancement layer. Then, an electrical connection layer is formed within the first and second openings. The greater removal rate of the first barrier layer than the enhancement layer protects the resistive layer. Furthermore, during the subsequent formation of the electrical connection layer, the enhancement layer prevents the process from consuming the resistive layer, thereby improving the uniformity of the resistive layer thickness and minimizing the difference between the resistive layer's resistance and the design value, thus making the performance of the semiconductor structure controllable.

[0038] Furthermore, the material of the reinforcing layer is a resistive layer material containing metal, and the structure of the reinforcing layer is relatively dense. On the one hand, the process of forming the first opening is carried out in two steps, so that the reinforcing layer can protect the resistive layer during the process of removing the first blocking layer at the bottom of the initial first opening to form the first opening; on the other hand, it can improve the growth rate of the electrical connection layer formed on the surface of the reinforcing layer. Attached Figure Description

[0039] Figures 1 to 3 This is a schematic cross-sectional view of the semiconductor structure formation process in one embodiment;

[0040] Figures 4 to 9 This is a cross-sectional schematic diagram of the semiconductor structure formation process in an embodiment of the present invention. Detailed Implementation

[0041] As described in the background section, the manufacturing process of semiconductor structures with local interconnect structures in the prior art is complex, and the performance of the resulting semiconductor structures needs further improvement. The following analysis and explanation will be provided with reference to specific embodiments.

[0042] Figures 1 to 3 This is a cross-sectional schematic diagram of the semiconductor structure formation process in one embodiment.

[0043] Please refer to Figure 1A substrate 100 is provided, the substrate 100 including a first region I and a second region II; a first dielectric layer 101 is formed on the substrate 100; a first conductive structure 102 is formed in the first dielectric layer 101 in the first region I; a first barrier layer 103 is formed on the first conductive structure 102 and the first dielectric layer 101; a resistive layer 104 is formed on the first barrier layer 103 in the second region II; a second barrier layer 105 is formed on the first barrier layer 103 and the resistive layer 104; a second dielectric layer 106 is formed on the second barrier layer 105; a first opening 108 and a second opening 107 are formed in the second dielectric layer 106, the first opening 108 exposing a portion of the surface of the first conductive structure 102 in the first region I, and the second opening 107 exposing a portion of the surface of the resistive layer 104 in the second region II.

[0044] Please refer to Figure 2 The semiconductor structure is then transferred into the deposition chamber.

[0045] Please refer to Figure 3 A first connecting layer 110 is formed in the first opening 108, and a second connecting layer 111 is formed in the second opening 107.

[0046] In the semiconductor structure, the first region I is the device region and the second region II is the peripheral region. In order to adjust the electrical performance of the semiconductor structure on the device region, a high-resistance resistive layer 104 is formed on the peripheral region. Then, the resistive layer 104 on the second region II is connected to the device on the first region I through a subsequent connection process to achieve the purpose of adjusting the electrical performance of the semiconductor structure.

[0047] During the formation of the semiconductor structure, forming the first opening 108 requires removing the first barrier layer 103 and the second barrier layer 105 on the first conductive structure 102, and forming the second opening 107 requires removing the second barrier layer 105 on the resistive layer 109. Since the first opening 108 and the second opening 107 are formed simultaneously, the process of forming the first opening 108 will damage the previously exposed resistive layer 104. During the process of transferring the semiconductor structure into the deposition chamber, the damaged resistive layer 104 is easily oxidized to form an oxide layer 109 (see reference). Figure 2 When the second interconnect layer 111 is formed in the second opening 107 using a selective deposition process, the process of forming the second interconnect layer 111 will consume the oxide layer 109, resulting in uneven thickness of the resistive layer 104. This causes the resistance of the resistive layer 104 to differ significantly from the preset value, thereby affecting the electrical performance of the formed semiconductor device. Consequently, the performance of the semiconductor device becomes uncontrollable and will differ significantly from the design.

[0048] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure. This involves first forming an initial first opening and a second opening. The initial first opening exposes a portion of the top surface of a first barrier layer on a first conductive structure, and the second opening exposes a portion of the top surface of a resistive layer. Then, an enhancement layer is formed on the surface of the resistive layer. After forming the enhancement layer, the first barrier layer exposed by the initial first opening is removed, forming the first opening again. The removal rate of the first barrier layer is greater than the removal rate of the enhancement layer. Finally, an electrical connection layer is formed within the first and second openings. The greater removal rate of the first barrier layer compared to the enhancement layer protects the resistive layer. Furthermore, during the subsequent formation of the electrical connection layer, the enhancement layer prevents the process from consuming the resistive layer, thereby improving the uniformity of the resistive layer thickness and minimizing the difference between the resistive layer's resistance and the design value, thus ensuring controllable semiconductor structure performance.

[0049] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0050] Figures 4 to 9 This is a cross-sectional schematic diagram of the semiconductor structure formation process in an embodiment of the present invention.

[0051] Please refer to Figure 4 A substrate 200 is provided, the substrate including a first region I and a second region II, the substrate 200 having a first dielectric layer 201 and a first conductive structure 202, the first conductive structure 202 being located within the first dielectric layer 201 on the first region I.

[0052] The first dielectric layer 201 has a groove (not shown), and the first conductive structure 202 includes: an adhesive layer (not shown) located on the sidewall surface and bottom surface of the groove, and a first conductive layer located on the adhesive layer.

[0053] The material of the adhesion layer includes a metal nitride, and the material of the first conductive layer includes a metal or a metal nitride, wherein the metal nitride includes titanium nitride or tantalum nitride, and the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum.

[0054] In this embodiment, the material of the adhesion layer includes titanium nitride, and the material of the first conductive layer includes cobalt.

[0055] In this embodiment, the substrate 200 includes: a substrate (not shown); a device layer (not shown) located on the substrate, the device layer including a third dielectric layer and a device structure located within the third dielectric layer, the device structure including a transistor, diode, triode, capacitor, inductor or conductive structure.

[0056] In this embodiment, the substrate is made of silicon.

[0057] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0058] In this embodiment, the substrate is a planar substrate.

[0059] In other embodiments, the substrate also has a fin structure.

[0060] The material of the first dielectric layer 201 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0061] In this embodiment, the material of the first dielectric layer 201 includes silicon oxide.

[0062] Please refer to Figure 5 A first barrier layer 203 is formed on the first dielectric layer 201.

[0063] The material of the first barrier layer 203 is different from the material of the second dielectric layer that is subsequently formed, so that the first barrier layer 203 can act as an etching stop layer when etching the second dielectric layer.

[0064] The material of the first barrier layer 203 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0065] In this embodiment, the material of the first barrier layer 203 includes silicon nitride.

[0066] Please continue to refer to this. Figure 5 A resistive layer 204 is formed on the first barrier layer 203 of the second region II.

[0067] The method of forming the resistive layer 204 includes: forming a second conductive material layer (not shown) on a substrate 200; removing the second conductive material layer on the first region I; and forming the resistive layer 204 on the first barrier layer 203 in the second region II.

[0068] The resistive layer 204 is made of a metal nitride, which includes one or more combinations of titanium nitride, tantalum nitride, tungsten nitride, and tungsten silicide. The resistive layer 204 formed from the above materials has a high resistivity and is also conducive to the subsequent growth of an enhancement layer on the resistive layer 204, making it suitable for adjusting the performance of semiconductor devices formed on the first region I.

[0069] In this embodiment, the metal nitride includes titanium nitride. The titanium nitride material is simple to form, can be formed using physical vapor deposition (PVD), has a fast film formation rate, and is relatively inexpensive, thus helping to save on production costs.

[0070] Please continue to refer to this. Figure 5 A second barrier layer 205 is formed on the resistive layer 204 and on the first barrier layer 203 of the first region I.

[0071] The material of the second barrier layer 205 is different from the material of the second dielectric layer subsequently formed, so that the second barrier layer 205 can serve as an etching stop layer for etching the second dielectric layer.

[0072] The material of the second barrier layer 205 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0073] In this embodiment, the material of the second barrier layer 205 includes silicon nitride.

[0074] In other embodiments, the second barrier layer may not be formed.

[0075] Please refer to Figure 6 A second dielectric layer 206 is formed on the second barrier layer 205.

[0076] The material of the second dielectric layer 206 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0077] In this embodiment, the material of the second dielectric layer 206 includes silicon oxide.

[0078] Please continue to refer to this. Figure 6 The second dielectric layer 206 and the second barrier layer 205 are etched to form an initial first opening 207 and a second opening 208 within the second dielectric layer 206 and the second barrier layer 205. The initial first opening 207 exposes a portion of the top surface of the first barrier layer 203 on the first conductive structure, and the second opening 208 exposes a portion of the top surface of the resistive layer 204.

[0079] The method of forming an initial first opening 207 and a second opening 208 within the second dielectric layer 206 includes: forming a transitional first opening (not shown) and an initial second opening (not shown) within the second dielectric layer, wherein the transitional first opening exposes a portion of the surface of the second barrier layer 205 on the first conductive structure, and the initial second opening exposes a portion of the surface of the second barrier layer 205 on the resistive layer 204; and removing the second barrier layer 205 exposed by the transitional first opening and the initial second opening to form the initial first opening 207 and the second opening 208.

[0080] The process for removing the second barrier layer exposed by the transition first opening and the initial second opening includes a dry etching process, wherein the etching gas in the dry etching process includes a fluorine-containing gas.

[0081] The etching process for the second dielectric layer 206 includes a dry etching process, wherein the etching gas used in the dry etching process includes a fluorine-containing gas.

[0082] The initial first opening 207 exposes part of the top surface of the first barrier layer 203 on the first conductive structure, and the second opening 208 exposes part of the top surface of the resistive layer 204, so that a reinforcement layer will only be formed on the surface of the resistive layer 204, and the first barrier layer 203 can protect the surface of the first conductive structure.

[0083] Please refer to Figure 7 The exposed resistive layer 204 is reinforced by forming a reinforcement layer 209 on the surface of the resistive layer 204.

[0084] The material of the reinforcing layer 209 includes the material of the resistive layer 204 containing metallic material, and the material of the reinforcing layer 209 includes titanium nitride or tantalum nitride containing metallic material.

[0085] The metallic material includes one or more of tungsten, cobalt, cesium, ruthenium, rubidium, and molybdenum. In this embodiment, the metallic material includes a rare metal, which includes tungsten.

[0086] The material of the reinforcement layer 209 includes the material of the metal resistive layer 204, thereby increasing the growth rate when an electrical connection layer is formed on the surface of the reinforcement layer 209.

[0087] In this embodiment, the process for forming the reinforcing layer 209 includes a displacement reaction. The parameters of the displacement reaction include: the reaction gas includes a mixture of tungsten hexafluoride and hydrogen; or the reaction gas includes a mixture of tungsten pentachloride and hydrogen; or the reaction gas includes tungsten hexafluoride, and the temperature range is 300 degrees Celsius to 400 degrees Celsius.

[0088] The tungsten element in the displacement reaction gas can be replaced by the titanium element in the resistive layer 204, so that the material of the formed reinforcing layer 209 is the same as that of the metallic resistive layer 204.

[0089] In other embodiments, the process for forming the reinforcement layer includes an ion implantation process containing metal material ions.

[0090] In this embodiment, the ratio of the thickness of the reinforcement layer 209 to the thickness of the resistor layer 204 is in the range of 1:3 to 1:2. If the thickness of the reinforcement layer 209 is too small, i.e., the ratio is less than 1:3, the protection effect of the reinforcement layer 209 on the resistor layer 204 is weak. In the subsequent process of forming the electrical connection layer, the process of blocking the formation of the electrical connection layer has a poor effect on the consumption of the resistor layer 204. If the thickness of the reinforcement layer 209 is too large, i.e., the ratio is greater than 1:2, the process time for forming the reinforcement layer 209 is long. As a result, the process of forming the reinforcement layer 209 will have a certain degree of modification and consumption on the surface of the second dielectric layer 206, so that the reinforcement layer 209 will also grow on the surface of the second dielectric layer 206. Subsequently, the electrical connection layer will also grow on the second dielectric layer 206, affecting the insulation of the second dielectric layer 206, thereby affecting the performance of the semiconductor structure.

[0091] Please refer to Figure 8 The first barrier layer 203 exposed by the initial first opening 207 is removed to form a first opening 210. The first opening 210 exposes part of the top surface of the first conductive structure 202. The removal rate of the first barrier layer 203 is greater than the removal rate of the reinforcement layer 209.

[0092] The process of removing the first barrier layer 203 has a greater removal rate for the first barrier layer 203 than for the reinforcement layer 209, so that the reinforcement layer 209 can protect the resistive layer 204.

[0093] The process for removing the first barrier layer 203 exposed by the initial first opening 207 includes a dry etching process, wherein the etching gas in the dry etching process includes a fluorine-containing gas.

[0094] The process of forming the first opening 210 is carried out in two steps. The material of the reinforcing layer 209 is a resistive layer material containing metal. The structure of the reinforcing layer 209 is relatively dense. Thus, during the process of removing the first blocking layer 203 at the bottom of the initial first opening 207 to form the first opening 210, the reinforcing layer 209 can protect the resistive layer 204.

[0095] Please refer to Figure 9 An electrical connection layer 211 is formed within the first opening 210 and the second opening 208.

[0096] The material of the electrical connection layer 211 includes metal, including tungsten.

[0097] The process of forming the electrical connection layer 211 within the first opening 210 and the second opening 208 includes a selective deposition process; the parameters of the selective deposition process include: a temperature range of 300 degrees Celsius to 400 degrees Celsius, and a reaction gas mixture of hydrogen and tungsten hexafluoride.

[0098] The material of the enhancement layer 209 is a resistive layer material containing metal. The structure of the enhancement layer 209 is relatively dense. The enhancement layer 209 can block the consumption of the resistive layer 208 by the process of forming the electrical connection layer 211, thereby improving the thickness uniformity of the resistive layer 208, making the resistance of the resistive layer 208 less different from the design value, and making the performance of the semiconductor structure controllable.

[0099] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figure 9 ,include:

[0100] Substrate 200, the substrate 200 includes a first region I and a second region II, the substrate 200 has a first dielectric layer 201 and a first conductive structure 202, the first conductive structure 202 is located in the first dielectric layer 201 on the first region I;

[0101] A first barrier layer 203 located on the first dielectric layer 201;

[0102] Resistive layer 204 located on first barrier layer 203 in second zone II;

[0103] A second barrier layer 205 is located on the resistive layer 204 and on the first barrier layer 203 of the first region I;

[0104] A second dielectric layer 206 is located on the second barrier layer 205. The second dielectric layer 206 has a first opening and a second opening. The first opening exposes the top surface of the first conductive structure 202, and the second opening exposes a portion of the top surface of the resistive layer 204.

[0105] A reinforcement layer 209 is located within a resistive layer 204, the resistive layer 204 exposes the surface of the reinforcement layer 209, and the thickness of the reinforcement layer 209 is less than the thickness of the resistive layer 204.

[0106] Electrical connection layer 211 located within the first opening and the second opening.

[0107] In this embodiment, the material of the reinforcing layer 209 is a resistive layer material containing metal.

[0108] In this embodiment, the metallic material includes one or more of tungsten, cobalt, cesium, ruthenium, rubidium, and molybdenum.

[0109] In this embodiment, the material of the resistive layer 204 includes metal nitrides, which include one or more combinations of titanium nitride, tantalum nitride, tungsten nitride, and tungsten silicide.

[0110] In this embodiment, the ratio of the thickness of the reinforcing layer 209 to the thickness of the resistive layer 204 is in the range of 1:3 to 1:2.

[0111] In this embodiment, the material of the electrical connection layer 211 includes metal, and the metal includes tungsten.

[0112] In this embodiment, the material of the first barrier layer 203 is different from the material of the second dielectric layer 206; the material of the second barrier layer 205 is different from the material of the second dielectric layer 206.

[0113] In this embodiment, the material of the first barrier layer 203 includes silicon nitride, and the material of the second barrier layer 205 includes silicon nitride.

[0114] In this embodiment, the first dielectric layer 201 has a groove; the first conductive structure includes: an adhesive layer located on the sidewall surface and bottom surface of the groove, and a first conductive layer located on the adhesive layer.

[0115] In this embodiment, the material of the adhesion layer includes a metal nitride, which includes titanium nitride; the material of the first conductive layer includes a metal, which includes cobalt.

[0116] In this embodiment, the substrate 200 includes: a substrate; a device layer located on the substrate, the device layer including a third dielectric layer and a device structure located within the third dielectric layer, the device structure including a transistor, diode, triode, capacitor, inductor or conductive structure; the first conductive structure is electrically connected to the device structure.

[0117] In other embodiments, the substrate also has a fin structure.

[0118] In the semiconductor structure, the material of the enhancement layer 209 is a resistive layer material containing metal. The structure of the enhancement layer 209 is relatively dense. The enhancement layer 209 can block the consumption of the resistive layer 208 by the process of forming the electrical connection layer 211, thereby improving the thickness uniformity of the resistive layer 208, making the resistance of the resistive layer 208 less different from the design value, and making the performance of the semiconductor structure controllable.

[0119] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate including a first region and a second region, the substrate having a first dielectric layer and a first conductive structure, the first conductive structure being located within the first dielectric layer on the first region; A first barrier layer located on the first dielectric layer; The resistive layer is located on the first barrier layer in the second region; A second barrier layer located on the resistive layer and on the first barrier layer of the first region; A second dielectric layer is located on the second barrier layer, the second dielectric layer having a first opening and a second opening, the first opening exposing a portion of the top surface of the first conductive structure, and the second opening exposing a portion of the top surface of the resistive layer; A reinforcing layer is located within a resistive layer, the resistive layer exposes the surface of the reinforcing layer, and the thickness of the reinforcing layer is less than the thickness of the resistive layer. The material of the reinforcing layer is a resistive layer material containing metal. The process for removing the first barrier layer has a greater removal rate for the first barrier layer than for the reinforcing layer. Electrical connection layer located within the first opening and the second opening.

2. The semiconductor structure as described in claim 1, characterized in that, The metallic material includes one or more of tungsten, cobalt, cesium, ruthenium, rubidium, and molybdenum.

3. The semiconductor structure as described in claim 2, characterized in that, The resistive layer is made of metal nitrides, including one or more combinations of titanium nitride, tantalum nitride, tungsten nitride, and tungsten silicide.

4. The semiconductor structure as described in claim 1, characterized in that, The ratio of the thickness of the reinforcing layer to the thickness of the resistive layer is in the range of 1:3 to 1:

2.

5. The semiconductor structure as described in claim 1, characterized in that, The material of the electrical connection layer includes metal, including tungsten.

6. The semiconductor structure as described in claim 1, characterized in that, The material of the first barrier layer is different from the material of the second dielectric layer; the material of the second barrier layer is different from the material of the second dielectric layer.

7. The semiconductor structure as described in claim 6, characterized in that, The first barrier layer is made of silicon nitride, and the second barrier layer is made of silicon nitride.

8. The semiconductor structure as described in claim 1, characterized in that, The first dielectric layer has a groove; the first conductive structure includes: an adhesive layer located on the sidewall surface and bottom surface of the groove, and a first conductive layer located on the adhesive layer.

9. The semiconductor structure as described in claim 8, characterized in that, The material of the adhesion layer includes a metal nitride, which includes titanium nitride; the material of the first conductive layer includes a metal, which includes cobalt.

10. The semiconductor structure as claimed in claim 1, characterized in that, The substrate includes: a substrate; a device layer on the substrate, the device layer including a third dielectric layer and a device structure located within the third dielectric layer, the device structure including a transistor, diode, triode, capacitor, inductor or conductive structure; the first conductive structure is electrically connected to the device structure.

11. The semiconductor structure as claimed in claim 10, characterized in that, The base also has a fin structure.

12. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first region and a second region, the substrate having a first dielectric layer and a first conductive structure, the first conductive structure being located within the first dielectric layer on the first region; A first barrier layer is formed on the first dielectric layer; A resistive layer is formed on the first barrier layer in the second region; A second barrier layer is formed on the resistive layer and on the first barrier layer of the first region; A second dielectric layer is formed on the second barrier layer; The second dielectric layer and the second barrier layer are etched to form an initial first opening and a second opening within the second dielectric layer and the second barrier layer. The initial first opening exposes a portion of the top surface of the first barrier layer on the first conductive structure, and the second opening exposes a portion of the top surface of the resistive layer. The exposed resistive layer is reinforced by forming a reinforcement layer on the surface of the resistive layer. The material of the reinforcement layer is a resistive layer material containing metal. After the reinforcement layer is formed, the first barrier layer exposed by the initial first opening is removed to form the first opening. The first opening exposes part of the top surface of the first conductive structure. The process of removing the first barrier layer has a greater removal rate for the first barrier layer than for the reinforcement layer. An electrical connection layer is formed within the first opening and the second opening.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The metallic material includes one or more of tungsten, cobalt, cesium, ruthenium, rubidium, and molybdenum.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The resistive layer is made of metal nitrides, including one or more combinations of titanium nitride, tantalum nitride, tungsten nitride, and tungsten silicide.

15. The method for forming a semiconductor structure as described in claim 13, characterized in that, The process for forming the reinforcing layer includes: displacement reaction.

16. The method for forming a semiconductor structure as described in claim 13, characterized in that, The process for forming the reinforcement layer includes: ion implantation process containing metal material ions.

17. The method for forming a semiconductor structure as described in claim 12, characterized in that, The ratio of the thickness of the reinforcing layer to the thickness of the resistive layer is in the range of 1:3 to 1:

2.

18. The method for forming a semiconductor structure as described in claim 12, characterized in that, The material of the electrical connection layer includes metal, including tungsten.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The process of forming an electrical connection layer within the first opening and the second opening includes a selective deposition process; the parameters of the selective deposition process include a temperature range of 300 degrees Celsius to 400 degrees Celsius and a reaction gas mixture of hydrogen and tungsten hexafluoride.

20. The method for forming a semiconductor structure as described in claim 12, characterized in that, A method for forming an initial first opening and a second opening within a second dielectric layer includes: forming a transitional first opening and an initial second opening within a second dielectric layer, wherein the transitional first opening exposes a portion of the surface of a second barrier layer on a first conductive structure, and the initial second opening exposes a portion of the surface of a second barrier layer on a resistive layer; and removing the second barrier layer exposed by the transitional first opening and the initial second opening to form the initial first opening and the second opening.

21. The method for forming a semiconductor structure as described in claim 12, characterized in that, The material of the first barrier layer is different from the material of the second dielectric layer; the material of the second barrier layer is different from the material of the second dielectric layer.

22. The method for forming a semiconductor structure as described in claim 21, characterized in that, The first barrier layer is made of silicon nitride, and the second barrier layer is made of silicon nitride.

23. The method for forming a semiconductor structure as described in claim 22, characterized in that, The process for removing the second barrier layer exposed by the transition first opening and the initial second opening includes a dry etching process, wherein the etching gas in the dry etching process includes a fluorine-containing gas.

24. The method for forming a semiconductor structure as described in claim 23, characterized in that, The process for removing the first barrier layer exposed by the initial first opening includes a dry etching process, wherein the etching gas in the dry etching process includes a fluorine-containing gas.

25. The method for forming a semiconductor structure as described in claim 12, characterized in that, The first dielectric layer has a groove; the first conductive structure includes: an adhesive layer located on the sidewall surface and bottom surface of the groove, and a first conductive layer located on the adhesive layer.

26. The method for forming a semiconductor structure as described in claim 25, characterized in that, The material of the adhesion layer includes a metal nitride, which includes titanium nitride; the material of the first conductive layer includes a metal, which includes cobalt.

27. The method for forming a semiconductor structure as described in claim 12, characterized in that, The substrate includes: a substrate; a device layer on the substrate, the device layer including a third dielectric layer and a device structure located within the third dielectric layer, the device structure including a transistor, diode, triode, capacitor, inductor or conductive structure; the first conductive structure is electrically connected to the device structure.

28. The method for forming a semiconductor structure as described in claim 27, characterized in that, The base also has a fin structure.

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