Array substrate, manufacturing method and display panel

Abstract

The application provides an array substrate, a preparation method thereof and a display panel with the array substrate, and relates to the technical field of display. The preparation method comprises the following steps: providing a substrate and forming a thin film transistor layer on the substrate, wherein the thin film transistor layer comprises an interlayer dielectric layer and a first conductive layer on the surface of the side of the interlayer dielectric layer away from the substrate, the interlayer dielectric layer comprises a first sub-layer and a second sub-layer which are sequentially deposited, the deposition temperature of the first sub-layer is less than the deposition temperature of the second sub-layer, so that the lattice density of the second sub-layer is greater than the lattice density of the first sub-layer. A photosensitive functional layer is formed on the side of the first conductive layer away from the substrate. A passivation layer film covering the photosensitive functional layer is deposited, and the passivation layer film is subjected to a patterning treatment to form a passivation layer with an opening, and the orthographic projection of the opening on the substrate overlaps the orthographic projection of the photosensitive functional layer on the substrate. The probability of the resistance of the sidewall of the photosensitive functional layer jumping is reduced, and the electrical performance of the photosensitive functional layer is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate, a method for fabricating the same, and a display panel having the array substrate. Background Technology

[0002] Optical fingerprint recognition technology has been widely used in display panels. Specifically, optical fingerprint recognition technology uses the principle of light reflection. When a finger is placed above a photosensitive sensor, the valleys and ridges of the fingerprint reflect light differently, resulting in varying intensities of reflected light received by the sensor. This generates different amounts of photocurrent, which is then used to capture the fingerprint's feature points for identification. Currently, most optical fingerprint recognition functions in display panels on the market are integrated under the screen. However, due to limitations in manufacturing processes, the sidewalls of the photosensitive sensor may exhibit a "step-like" structure, leading to leakage current and affecting fingerprint recognition accuracy. Summary of the Invention

[0003] A first aspect of this application provides a method for fabricating an array substrate. The method includes providing a substrate and forming a thin-film transistor layer on the substrate. The thin-film transistor layer includes an interlayer dielectric layer and a first conductive layer located on a surface of the interlayer dielectric layer facing away from the substrate. The interlayer dielectric layer includes a first sublayer and a second sublayer deposited sequentially. The deposition temperature of the first sublayer is lower than that of the second sublayer, such that the lattice density of the second sublayer is greater than that of the first sublayer. A photosensitive functional layer is formed on the side of the first conductive layer facing away from the substrate. A passivation layer film covering the photosensitive functional layer is deposited, and the passivation layer film is patterned to form a passivation layer with openings. The orthographic projection of the openings on the substrate overlaps with the orthographic projection of the photosensitive functional layer on the substrate.

[0004] In the above scheme, by reducing the risk of adverse effects on the sidewall shape of the photosensitive functional layer due to different etching processes under different conditions for multiple film layers, the probability of resistance jumps in the sidewalls of the photosensitive functional layer is reduced, thereby improving the electrical performance of the photosensitive functional layer, mitigating leakage current, and ultimately improving the accuracy of image recognition. Furthermore, the interlayer dielectric layers obtained at different deposition temperatures reduce the risk of hydrogen atoms affecting the quality of the array substrate due to the reduction in the passivation layer.

[0005] In conjunction with the first aspect, in some embodiments, the formation process of the thin-film transistor layer further includes forming an active layer on a substrate, the active layer including a channel region and source and drain regions disposed on opposite sides of the channel region. The first conductive layer includes a source electrode and a drain electrode, the source electrode and / or drain electrode being formed such that their orthogonal projections on the substrate at least partially overlap with the orthogonal projections of the channel region on the substrate.

[0006] In the above scheme, the source electrode and / or drain electrode can block the diffusion of hydrogen atoms toward the substrate, so that the source electrode and / or drain electrode can shield the channel region as much as possible, which can further improve the protection of the channel region.

[0007] In conjunction with the first aspect, in some embodiments, the photosensitive functional layer includes a photosensitive layer and a photosensitive electrode. Forming the photosensitive functional layer on the side of the first conductive layer away from the substrate includes depositing a photosensitive material on the side of the first conductive layer away from the substrate to form the photosensitive layer. The first conductive layer also includes a first electrode connected to a source electrode or a drain electrode. The photosensitive layer is formed on the surface of the first electrode on the side away from the substrate. A second conductive layer is formed on the side of the photosensitive layer away from the substrate, and the second conductive layer is etched to form the photosensitive electrode. At least a portion of the photosensitive electrode is filled within the opening. The orthogonal projection of the photosensitive electrode onto the substrate falls within the orthogonal projection of the photosensitive layer onto the substrate, and the orthogonal projection of the photosensitive layer onto the substrate and the orthogonal projection of the channel region onto the substrate are spaced apart.

[0008] In the above scheme, the photosensitive layer is directly disposed on the first electrode formed by the first conductive layer, which simplifies the structure of the array substrate.

[0009] In conjunction with the first aspect, in some embodiments, a second conductive layer is etched to form a photosensitive electrode, and the sidewalls of the photosensitive electrode are controlled to be smoothly connected to the sidewalls of the photosensitive layer.

[0010] In the above scheme, the "step" structure at the connection between the sidewall of the second conductive layer and the sidewall of the photosensitive layer is reduced, thereby reducing the leakage current at the connection and improving the accuracy of image recognition.

[0011] A second aspect of this application provides an array substrate, comprising a substrate, a thin-film transistor layer disposed on the substrate, a photosensitive functional layer, and a passivation layer disposed on a side of the photosensitive functional layer facing away from the substrate. The thin-film transistor layer includes an interlayer dielectric layer and a first conductive layer stacked sequentially, and the interlayer dielectric layer includes a first sublayer and a second sublayer stacked sequentially on the substrate, wherein the lattice density of the second sublayer is greater than the lattice density of the first sublayer. The photosensitive functional layer is disposed on the side of the first conductive layer facing away from the substrate, and the passivation layer has an opening whose orthogonal projection on the substrate overlaps with the orthogonal projection of the photosensitive functional layer on the substrate.

[0012] In the above scheme, the sidewall quality of the photosensitive functional layer is improved while the structure of the array substrate does not significantly affect the blocking effect of hydrogen atoms diffusing towards the substrate, thereby improving the electrical performance of the photosensitive functional layer.

[0013] In conjunction with the second aspect, in some embodiments, the thin-film transistor layer includes an active layer, which includes a channel region and source and drain regions disposed on opposite sides of the channel region. The first conductive layer includes a source electrode and a drain electrode, and the orthogonal projection of the source electrode and / or drain electrode onto the substrate at least partially overlaps with the orthogonal projection of the channel region onto the substrate.

[0014] In the above scheme, the channel region is further protected, thereby further improving the performance of the array substrate.

[0015] In conjunction with the second aspect, in some embodiments, the photosensitive functional layer includes a photosensitive layer and a photosensitive electrode. The photosensitive layer is located on the side of the first conductive layer opposite to the substrate, the first conductive layer including a first electrode connected to a source electrode or a drain electrode, and the photosensitive layer is formed on the surface of the first electrode. The photosensitive electrode is located on the side of the photosensitive layer opposite to the substrate, at least a portion of the photosensitive electrode is filled within an opening, and the orthographic projection of the photosensitive electrode onto the substrate falls within the orthographic projection of the photosensitive functional layer onto the substrate.

[0016] In the above scheme, different functional modules achieve the sharing of electrodes, which simplifies the structure of the array substrate.

[0017] In conjunction with the second aspect, in some embodiments, the orthogonal projection of the photosensitive layer on the substrate falls within the orthogonal projection of the first electrode on the substrate.

[0018] In the above scheme, the relative sizes of the first electrode and the photosensitive functional layer enhance the blocking effect of the first electrode on the leakage current generated between them, thereby reducing the impact of leakage current on the quality of the array substrate. In conjunction with the second aspect, in some embodiments, the sidewall of the photosensitive electrode is smoothly connected to the sidewall of the photosensitive layer.

[0019] In the above scheme, there is no "step" structure at the connection between the sidewalls of the photosensitive electrode and the photosensitive layer, which further improves the accuracy of image recognition.

[0020] A third aspect of this application provides a display panel, which includes an array substrate of any one of the first aspects described above, and a display functional layer, which includes a plurality of light-emitting devices, and a photosensitive functional layer is provided around at least one light-emitting device. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below.

[0022] Figure 1 This is a cross-sectional view of an array substrate according to an embodiment of this application.

[0023] Figure 2 This is a cross-sectional view of an array substrate according to another embodiment of this application.

[0024] Figure 3 This is a cross-sectional view of an array substrate according to another embodiment of this application.

[0025] Figure 4 This is a cross-sectional view of an array substrate according to another embodiment of this application.

[0026] Figure 5 This is a schematic diagram of a method for fabricating an array substrate according to an embodiment of this application.

[0027] Figure 6 This is a schematic diagram of a method for fabricating an array substrate according to another embodiment of this application.

[0028] Figure 7 This is a schematic diagram of a method for fabricating an array substrate according to an embodiment of this application.

[0029] Figure 8 This is a schematic diagram of a method for fabricating an array substrate according to another embodiment of this application.

[0030] Figure 9 This is a cross-sectional view of a display panel according to an embodiment of this application. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] Optical image recognition technology typically identifies fingerprints by detecting the light reflected from a touching object (e.g., a finger) to the image recognition unit, thus determining the ridges and valleys of the fingerprint. Optical image recognition is fast and convenient, and has become an essential function in modern smart devices. To achieve this function, photosensors can be applied to display substrates containing light-emitting devices and thin-film transistors (TFTs). However, during the fabrication of these display substrates, hydrogen atoms in the photosensitive sensor manufacturing process have a significant impact on the active layer of the TFT. To reduce the influence of hydrogen atoms on the active layer, multiple films, such as active layers and passivation layers, are placed between the photodiode and the active layer to block the diffusion of hydrogen atoms. However, the openings in these films, such as the passivation layer, affect the sidewalls of the photodiode, causing abrupt changes in its resistance, thereby affecting the accuracy of image recognition.

[0033] This application provides a method for fabricating an array substrate and the array substrate obtained by this method, which can improve the problem of the sidewalls of the photodiode being affected by adding multiple film layers between the photodiode and the active layer to block hydrogen atom diffusion. The embodiments of this application are illustrated below with reference to the accompanying drawings.

[0034] This application provides an array substrate, such as... Figure 1 As shown, the array substrate includes a substrate 100, a thin-film transistor layer 200 disposed on the substrate 100, a photosensitive functional layer 300, and a passivation layer 400 disposed on the side of the photosensitive functional layer 300 facing away from the substrate 100. The thin-film transistor layer 200 includes an interlayer dielectric layer 210 and a first conductive layer 220 stacked sequentially, and the interlayer dielectric layer 210 includes a first sublayer 211 and a second sublayer 212 stacked sequentially on the substrate 100, and the lattice density of the second sublayer 212 is greater than the lattice density of the first sublayer 211. The photosensitive functional layer 300 is disposed on the side of the first conductive layer 220 facing away from the substrate 100. The passivation layer 400 has an opening 401, the orthographic projection of the opening 401 on the substrate 100 overlapping the orthographic projection of the photosensitive functional layer 300 on the substrate 100.

[0035] The accuracy of image recognition based on the array substrate is affected by the electrical properties of the photosensitive functional layer 300, which are directly influenced by its sidewall shape. Therefore, by directly depositing the photosensitive functional layer 300 on the first conductive layer 220 and reducing the passivation layer 400 between them, the number of etching steps for different film layers is reduced. This reduces the adverse effects of different etching steps on the sidewalls of the photosensitive functional layer 300 during array substrate fabrication, thereby reducing the risk of "step" structures appearing on the sidewalls of the photosensitive functional layer 300. In other words, it reduces the probability of abrupt changes in the resistance of the sidewalls of the photosensitive functional layer 300, thus improving the electrical properties of the photosensitive functional layer 300 and the accuracy of image recognition on the array substrate. Simultaneously, the second sublayer 212 of the interlayer dielectric layer 210 in the thin-film transistor layer 200, with its high lattice density, strengthens the barrier against hydrogen atoms diffusing towards the substrate 100, thereby improving the quality of the array substrate. In addition, the interlayer dielectric layer 210 serves multiple functions as a functional film layer, which simplifies the film structure of the array substrate and facilitates the thinning of the array substrate.

[0036] Besides improving the electrical performance of the photosensitive sensor to enhance the overall performance of the array substrate, in some embodiments, the thin-film transistor layer 200 includes an active layer 230, which includes a channel region 231 and source regions 232 and drain regions 233 respectively disposed on both sides of the channel region 231. The first conductive layer 220 includes a source electrode 221 and a drain electrode 222, the orthographic projections of the source electrode 221 and / or drain electrode 222 on the substrate 100 at least partially overlapping the orthographic projection of the channel region 231 on the substrate 100. The source electrode 221 and / or drain electrode 222 shield the channel region 231, further preventing hydrogen atoms from diffusing into the channel region 231, thus providing further protection for the channel region 231.

[0037] There are various implementation schemes for protecting the trench area 231, which can be selected according to production conditions and the functional requirements of the array substrate.

[0038] For example, such as Figure 2 As shown, the thin-film transistor layer 200 also includes an active layer 230 located between the interlayer dielectric layer 210 and the substrate 100, a gate insulating layer 240 located on the side of the active layer 230 facing away from the substrate 100, and a gate electrode 250 located between the gate insulating layer 240 and the interlayer dielectric layer 210. The active layer 230 includes a channel region 231 and a source region 232 and a drain region 233 disposed on both sides of the channel region 231. The gate electrode 250 is disposed facing the channel region 231. The first conductive layer 220 includes a source electrode 221 electrically connected to the source region 232 and a drain electrode 222 electrically connected to the drain region 233. The orthographic projection of the source electrode 221 on the substrate 100 and the orthographic projection of the photosensitive functional layer 300 on the substrate 100 are respectively disposed and at least partially overlap with the orthographic projection of the channel region 231 on the substrate 100. This is equivalent to lengthening the source electrode 221 so that it can block the channel region 231 over a larger area, thereby strengthening the protection of the channel region 231.

[0039] For example, such as Figure 3 As shown, based on Figure 2 The thin film structure of the thin film transistor layer 200 is configured such that the orthographic projection of the thin film transistor layer 200 on the substrate 100 overlaps with the orthographic projection of the photosensitive functional layer 300 on the substrate 100. The drain electrode 222 is extended so that its orthographic projection on the substrate 100 overlaps with the orthographic projection of the channel region 231 on the substrate 100 as much as possible, thereby providing more comprehensive protection for the channel region 231.

[0040] For example, such as Figure 4 As shown, based on Figure 2The thin-film transistor layer 200 has a film structure in which the orthogonal projections of the source electrode 221 and the drain electrode 222 onto the substrate 100 at least partially overlap with the orthogonal projection of the channel region 231 onto the substrate, thereby providing relatively comprehensive protection for the channel region 231.

[0041] It should be understood that the thin-film transistor can be a top-gate thin-film transistor or a bottom-gate thin-film transistor, and can be a P-type thin-film transistor or an N-type thin-film transistor. In the above example, the thin-film transistor is described as an N-type top-gate thin-film transistor, but it is not limited thereto.

[0042] In some embodiments, such as Figure 2 , Figure 3 and Figure 4 As shown, the photosensitive functional layer 300 includes a photosensitive layer 310 and a photosensitive electrode 510. The photosensitive layer 310 is located on the side of the first conductive layer 220 facing away from the substrate 100. The first conductive layer 220 includes a first electrode connected to a source electrode 221 or a drain electrode 222. Here, the first electrode is connected to the drain electrode 222. Alternatively, the drain electrode 222 can be understood as extending below the corresponding photosensitive layer 310 and contacting the photosensitive layer 310. The photosensitive layer 310 is formed on the surface of the first electrode. The photosensitive electrode 510 is located on the side of the photosensitive layer 310 facing away from the substrate 100. At least a portion of the photosensitive electrode 510 is filled within the opening 401, and the orthographic projection of the photosensitive electrode 510 on the substrate 100 falls within the orthographic projection of the photosensitive functional layer 300 on the substrate 100. In this array substrate, the photosensitive layer 310 is formed directly on the surface of the drain electrode 222 away from the substrate 100, so that the photosensitive functional module of the array substrate and its pixel driving module share the drain electrode 222. That is, the same film layer, i.e. electrode, is shared by different working modules, which helps to simplify the structure of the array substrate and achieve its thinness.

[0043] In at least one embodiment, the orthogonal projection of the photosensitive layer 310 onto the substrate 100 falls within the orthogonal projection of the first electrode onto the substrate 100. With the drain electrode 222 lengthened so that its orthogonal projection onto the substrate 100 at least partially overlaps with the orthogonal projection of the channel region 231 onto the substrate 100, the drain electrode 222 is enlarged relative to the photosensitive layer 310. This enhances the blocking effect on leakage current generated between the photosensitive layer 310 and the drain electrode 222, thereby improving the quality of the array substrate.

[0044] In some embodiments, such as Figure 2 , Figure 3 and Figure 4As shown, the sidewall of the photosensitive electrode 510 is smoothly connected to the sidewall of the photosensitive layer 310. The photosensitive device includes the photosensitive electrode 510 and the photosensitive layer 310, and there is no "step" structure at the connection between their sidewalls. This reduces the risk of leakage at the sidewall of the junction between the photosensitive electrode 510 and the photosensitive layer 310, and improves the performance of the photosensitive device.

[0045] It should be understood that the sidewalls of the photosensitive layer are not limited to the inclined surfaces shown in the example figures above; they can also be curved surfaces or have gently changing patterns. This reduces the probability of abrupt changes in the resistance of the photosensitive sensor, thereby improving the electrical performance of the photosensitive sensor and enhancing its image recognition accuracy. Furthermore, other structures can be provided between the photosensitive layer and the photosensitive electrodes in the array substrate, depending on the needs of the array substrate or manufacturing process requirements, such as an electrode protective layer. In addition, the above embodiments do not limit the method by which the photosensitive functional layer of the array substrate achieves image recognition; it can employ any of the following methods: optical image recognition, capacitive image recognition, and ultrasonic image recognition, which will not be elaborated upon here.

[0046] This application also provides a method for fabricating an array substrate, such as... Figure 5 As shown, the fabrication method of this array substrate includes the following steps.

[0047] Step S01: Provide a substrate 100 and form a thin-film transistor layer 200 on the substrate 100. The thin-film transistor layer 200 includes an interlayer dielectric layer 210 and a first conductive layer 220 located on the surface of the interlayer dielectric layer 210 facing away from the substrate 100. The interlayer dielectric layer 210 includes a first sublayer 211 and a second sublayer 212 deposited sequentially. The deposition temperature of the first sublayer 211 is lower than the deposition temperature of the second sublayer 212, such that the lattice density of the second sublayer 212 is greater than the lattice density of the first sublayer 211.

[0048] Specifically, the first sublayer 211 was formed by low-temperature deposition with parameters of B_SiOx (170℃). The second sublayer 212 was formed by high-temperature deposition with the following parameters: T_SiOx (290℃). A back-up process is performed between the two depositions. This back-up process involves dehydrogenation and oxygen replenishment, which releases stress, repairs interface defects, and increases the electrical stability of the film. The lattice density of the second sublayer 212 is greater than that of the first sublayer 211, which can better prevent hydrogen atoms from diffusing towards the substrate 100, thus protecting the thin-film transistor layer 200. Furthermore, the fabrication process of the interlayer dielectric layer 210 is simple, simplifying the manufacturing process and saving production costs.

[0049] Step S02: A photosensitive functional layer 300 is formed on the side of the first conductive layer 220 that is away from the substrate 100.

[0050] Step S03: Deposit a passivation layer 400 thin film covering the photosensitive functional layer 300, and pattern the passivation layer 400 thin film to form a passivation layer 400 with an opening 401. The orthographic projection of the opening 401 on the substrate 100 overlaps with the orthographic projection of the photosensitive functional layer 300 on the substrate 100.

[0051] Only one passivation layer 400 is provided on the side of the first conductive layer 220 facing the photosensitive functional layer 300 and on the sidewall of the photosensitive functional layer 300. This reduces the risk of adverse effects on the sidewall shape of the photosensitive functional layer 300 due to different etching processes of multiple film layers, and reduces the probability of abrupt changes in the resistance of the sidewall of the photosensitive functional layer 300. This improves the electrical performance of the photosensitive functional layer 300, reduces leakage current, and thus improves the accuracy of image recognition.

[0052] The process of forming the thin-film transistor layer 200 is described in some embodiments using a top-gate structure as an example, such as... Figure 9 As shown, in step S01, the formation process of the thin film transistor layer 200 further includes the following steps.

[0053] Step S011: An active layer 230 is formed on the substrate 100. The active layer 230 includes a channel region 231 and a source region 232 and a drain region 233 disposed on both sides of the channel region 231.

[0054] Step S012: A gate insulating layer 240 is sequentially deposited on the active layer 230. The gate insulating layer 240 can be made of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0055] Step S013: A gate electrode 250 is formed on the side of the gate insulating layer 240 facing away from the active layer 230. Specifically, a metal layer is sequentially deposited on the gate insulating layer 240, and then a photoresist layer is coated on the metal layer. The photoresist layer is then imaged to form the pattern of the gate electrode 250.

[0056] Step S014: An interlayer dielectric layer 210 is formed on the side of the gate electrode 250 facing away from the substrate 100.

[0057] Step S014: A first conductive layer 220 is formed on the surface of the interlayer dielectric layer 210 on the side facing away from the substrate 100. The first conductive layer 220 includes a source electrode 221 and a drain electrode 222, and the source electrode 221 and / or the drain electrode 222 are formed such that their orthogonal projections on the substrate 100 at least partially overlap with the orthogonal projections of the channel region 231 on the substrate 100. The source electrode 221 and / or the drain electrode 222 can block the diffusion of hydrogen atoms toward the substrate 100, thereby shielding the channel region 231 as much as possible and further improving the protection of the channel region 231.

[0058] Specifically, a metal layer is sequentially deposited on the side of the interlayer dielectric layer 210 facing away from the active layer 230. The material of the metal layer can be metals such as Mo, Al, Ti, Au, Hf, and Ta, or an alloy of some of these metals. A metal layer pattern is formed on the metal layer, and the formed metal layer pattern includes a source electrode 221 and a drain electrode 222. The metal layer pattern is adjusted so that the orthogonal projection of the source electrode 221 and / or the drain electrode 222 on the substrate 100 at least partially overlaps with the orthogonal projection of the channel region 231 on the substrate 100.

[0059] It should be understood that the fabrication method of the thin-film transistor layer is not limited to the method in the above example. It may also include other film layer fabrication steps, such as forming an insulating dielectric layer, such as a capacitor insulating layer, between the gate electrode and the interlayer dielectric layer. These can be adjusted according to the actual production needs of the array substrate, and will not be elaborated here.

[0060] In some embodiments, in step S02, the photosensitive functional layer 300 includes a photosensitive layer 310 and a photosensitive electrode 510. Forming the photosensitive functional layer 300 on the side of the first conductive layer 220 away from the substrate 100 includes the following steps.

[0061] Step S021: Deposit photosensitive material on the side of the first conductive layer 220 away from the substrate 100 to form a photosensitive layer 310. The first conductive layer 220 also includes a first electrode connected to the source electrode 221 or the drain electrode 222. The photosensitive layer is formed on the surface of the first electrode on the side away from the substrate 100.

[0062] Step S022: A second conductive layer 500 is formed on the side of the photosensitive layer 310 facing away from the substrate 100. The second conductive layer 500 is etched to form a photosensitive electrode 510, with at least a portion of the photosensitive electrode 510 filling the opening 401. The orthogonal projection of the photosensitive electrode 510 onto the substrate 100 falls within the orthogonal projection of the photosensitive layer 310 onto the substrate 100, and the orthogonal projections of the photosensitive layer 310 onto the substrate 100 and the channel region 231 onto the substrate 100 are spaced apart.

[0063] In some embodiments, in step S022, the second conductive layer 500 is etched to form a photosensitive electrode 510, and the sidewall of the photosensitive electrode 510 is smoothly connected to the sidewall of the photosensitive layer 310, including the following steps.

[0064] Step S0221: During the etching of the photosensitive material layer to form the photosensitive layer 310, the second conductive layer 500 is simultaneously etched to form the initial electrode 511. Specifically, this etching can be dry etching, where the films used to form the photosensitive layer 310 and the photosensitive electrode 510 are etched simultaneously. Since the materials used to form the photosensitive layer 310 and the film used to form the photosensitive electrode 510 are different, their etching rates are also different, with the photosensitive layer 310 being etched at a faster rate. This results in a "step" forming at the connection between the photosensitive electrode 510 and the photosensitive layer 310, and this "step" structure can cause leakage problems.

[0065] Step S0222: Etch the initial electrode 511 to form the photosensitive electrode 510, and the sidewall of the photosensitive electrode 510 is smoothly connected to the sidewall of the photosensitive layer 310. Wet etching can be used this time, mainly to etch the part of the sidewall of the second electrode layer that protrudes relative to the photosensitive layer 310 after the first etching, to eliminate the "step" structure on the sidewall at the connection between the two, and to make the sidewalls of the two smoothly connected, thereby improving the leakage problem.

[0066] This application embodiment also provides a display panel, such as Figure 9 As shown, the display panel includes an array substrate and a display functional layer 600 of any of the above embodiments. The display functional layer 600 includes a plurality of light-emitting devices 610. Each light-emitting device 610 includes an anode 611, a cathode 612 and a light-emitting functional layer 613 located between the two. At least one light-emitting device 610 is provided with a photosensitive functional layer 300 around its periphery.

[0067] It should be understood that, Figure 9 The document only shows a portion of the structure of the light-emitting device, such as one electrode; other structures are omitted. Besides the electrode, the light-emitting device also includes other structures, such as another electrode. The light-emitting functional layer located between the two electrodes includes, but is not limited to, a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer. Furthermore, the embodiments of this application do not limit the order in which the light-emitting device and the photosensitive device are fabricated. In practical applications, the design can be selected based on the impact of different processes on the quality of the array substrate and product requirements, which will not be elaborated upon here.

[0068] In some embodiments, the array substrate further includes multiple light-emitting devices, each of which has a photosensitive functional layer around its periphery. The multiple light-emitting devices may emit light of the same color, or may include multiple light-emitting devices that emit light of different colors, such as multiple red light-emitting devices, multiple blue light-emitting devices, and multiple green light-emitting devices.

[0069] In at least one embodiment, when the array substrate includes multiple light-emitting devices that emit light of the same color, and the display panel needs to display a color effect, a color filter or other color devices such as a quantum dot film can be provided in any layer or multiple layers of any panel of the display panel.

[0070] In at least one embodiment, the display panel further includes a touch sensor, a touch chip, and a flexible circuit board for implementing touch control. To achieve a thinner and lighter touch display panel, the touch sensor is disposed in the encapsulation layer of the display panel, the touch chip is disposed on the flexible circuit board, and signals are transmitted to the touch sensor through touch signal lines.

[0071] In at least one embodiment, the display panel can be any product or component with display and touch functions, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Implementations of this display panel can refer to the embodiments of the array substrate described above; repeated details will not be repeated.

[0072] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for fabricating an array substrate, characterized in that, include: A substrate is provided and a thin-film transistor layer is formed on the substrate, the thin-film transistor layer including an interlayer dielectric layer and a first conductive layer located on a surface of the interlayer dielectric layer opposite to the substrate; A photosensitive functional layer is formed on the side of the first conductive layer that is away from the substrate; A passivation layer film is deposited to cover the photosensitive functional layer, and the passivation layer film is patterned to form a passivation layer with openings, wherein the orthographic projection of the openings on the substrate overlaps with the orthographic projection of the photosensitive functional layer on the substrate. The interlayer dielectric layer includes a first sublayer and a second sublayer deposited sequentially. The deposition temperature of the first sublayer is lower than that of the second sublayer, so that the lattice density of the second sublayer is greater than that of the first sublayer.

2. The preparation method according to claim 1, characterized in that, The process of forming the thin-film transistor layer also includes: An active layer is formed on the substrate, the active layer including a channel region and a source region and a drain region respectively disposed on both sides of the channel region; The first conductive layer includes a source electrode and a drain electrode, wherein the source electrode and / or the drain electrode are formed such that their orthogonal projections on the substrate at least partially overlap with the orthogonal projections of the channel region on the substrate.

3. The preparation method according to claim 2, characterized in that, The photosensitive functional layer includes a photosensitive layer and a photosensitive electrode, wherein forming the photosensitive functional layer on the side of the first conductive layer opposite to the substrate includes: A photosensitive material is deposited on the side of the first conductive layer away from the substrate to form the photosensitive layer. The first conductive layer also includes a first electrode connected to the source electrode or the drain electrode. The photosensitive layer is formed on the surface of the first electrode on the side away from the substrate. A second conductive layer is formed on the side of the photosensitive layer opposite to the substrate, and the second conductive layer is etched to form the photosensitive electrode, with at least a portion of the photosensitive electrode filling the opening; Wherein, the orthogonal projection of the photosensitive electrode on the substrate falls within the orthogonal projection of the photosensitive layer on the substrate, and the orthogonal projection of the photosensitive layer on the substrate and the orthogonal projection of the channel region on the substrate are distributed alternately.

4. The preparation method according to claim 3, characterized in that, The second conductive layer is etched to form the photosensitive electrode, and the sidewall of the photosensitive electrode is controlled to be smoothly connected to the sidewall of the photosensitive layer.

5. An array substrate, characterized in that, include: Substrate, A thin-film transistor layer is disposed on the substrate, the thin-film transistor layer comprising an interlayer dielectric layer and a first conductive layer stacked sequentially; A photosensitive functional layer is disposed on the side of the first conductive layer that faces away from the substrate; A passivation layer is disposed on the side of the photosensitive functional layer away from the substrate. The passivation layer has an opening, and the orthographic projection of the opening on the substrate overlaps with the orthographic projection of the photosensitive functional layer on the substrate. The interlayer dielectric layer includes a first sublayer and a second sublayer stacked sequentially on the substrate, wherein the lattice density of the second sublayer is greater than that of the first sublayer.

6. The array substrate according to claim 5, characterized in that, The thin-film transistor layer includes an active layer, which includes a channel region and a source region and a drain region disposed on both sides of the channel region. The first conductive layer includes a source electrode and a drain electrode, wherein the orthogonal projection of the source electrode and / or the drain electrode on the substrate at least partially overlaps with the orthogonal projection of the channel region on the substrate.

7. The array substrate according to claim 6, characterized in that, The photosensitive functional layer includes: A photosensitive layer is located on the side of the first conductive layer opposite to the substrate. The first conductive layer includes a first electrode connected to the source electrode or drain electrode, and the photosensitive layer is formed on the surface of the first electrode. A photosensitive electrode is located on the side of the photosensitive layer opposite to the substrate, at least a portion of the photosensitive electrode is filled in the opening, and the orthogonal projection of the photosensitive electrode on the substrate falls within the orthogonal projection of the photosensitive functional layer on the substrate.

8. The array substrate according to claim 7, characterized in that, The orthogonal projection of the photosensitive layer onto the substrate falls within the orthogonal projection of the first electrode onto the substrate.

9. The array substrate according to claim 7, characterized in that, The sidewall of the photosensitive electrode is smoothly connected to the sidewall of the photosensitive layer.

10. A display panel, characterized in that, include: The array substrate according to any one of claims 5-9; as well as The display functional layer includes multiple light-emitting devices, and the photosensitive functional layer is provided around at least one of the light-emitting devices.

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