Display panel and manufacturing method thereof

Abstract

The present application provides a display panel and a method for manufacturing the same. The display panel includes a thin film transistor (TFT), which includes a channel, a first conductor portion and a second conductor portion disposed on either side of the channel, an interlayer insulating layer, and a first electrode and a second electrode. The display panel further includes a first via hole and a second via hole, wherein the first via hole penetrates the interlayer insulating layer and exposes the surface and side surfaces of the first conductor portion, a first light-shielding conductive member is filled within the first via hole, and a second via hole penetrates the interlayer insulating layer and exposes the surface and side surfaces of the second conductor portion, and a second light-shielding conductive member is filled within the second via hole. The first and second light-shielding conductive members in the display panel provided by the present application can more effectively protect the channel of the thin film transistor, significantly reducing the probability of device performance degradation and reduced reliability of the thin film transistor due to side light irradiating the channel, thereby improving the device performance of the thin film transistor and the display stability of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for preparing the same. Background Art

[0002] Compared with liquid crystal displays, organic light emitting diode (OLED) display panels have the advantages of being thinner and lighter, having better display effects, higher resolution, wider color gamut, lower power consumption, and flexible display. As a result, they have developed rapidly in recent years and have become the preferred display panel type for mobile terminals.

[0003] The driving circuit layer in the OLED display panel is equipped with thin-film transistors. The channel region in the active layer of the thin-film transistor has light-sensitive characteristics and is easily illuminated by external ambient light and light emitted by the OLED light-emitting unit directly or after reflection, which leads to the problem of deterioration of the performance of the thin-film transistor device and reduced reliability. This problem needs to be solved urgently. Summary of the Invention

[0004] The present application provides a display panel and a method for manufacturing the same, which can effectively solve the problem of device performance deterioration and reduced reliability of thin film transistors in existing OLED display panels due to the channel being easily exposed to light.

[0005] In one aspect, the present application provides a display panel, comprising: a substrate layer and a thin film transistor disposed on one side of the substrate layer; wherein the thin film transistor comprises:

[0006] an active layer, disposed on one side of the substrate layer, comprising a channel, a first conductor portion and a second conductor portion disposed on both sides of the channel;

[0007] an interlayer insulating layer, disposed on a side of the substrate layer facing the active layer and a side of the active layer facing away from the substrate layer;

[0008] A first electrode and a second electrode are arranged on a side of the interlayer insulating layer away from the substrate layer;

[0009] The display panel further includes a first via hole and a second via hole, a first light-shielding conductive member and a second light-shielding conductive member.

[0010] The first via hole penetrates the interlayer insulating layer and exposes the surface and side surfaces of the first conductor portion. The first light-shielding conductive member is filled in the first via hole. The first electrode is electrically connected to the first conductor portion through the first light-shielding conductive member.

[0011] The second via hole penetrates the interlayer insulating layer and exposes the surface and side surfaces of the second conductor portion. The second light-shielding conductive member is filled in the second via hole. The second electrode is electrically connected to the second conductor portion through the second light-shielding conductive member.

[0012] Optionally, the display panel also includes a base substrate and a light-shielding metal layer arranged on one side of the base substrate, the base layer is arranged on the side of the base substrate facing the light-shielding metal layer and the side of the light-shielding metal layer away from the base substrate, wherein the second via also penetrates the base layer and exposes the light-shielding metal layer, and the second electrode is electrically connected to the second conductor portion and the light-shielding metal layer through the second light-shielding conductive member.

[0013] Optionally, the second light-shielding conductive component includes a first part and a second part, the orthographic projection of the first part on the base substrate overlaps with the orthographic projection of the second conductor part on the base substrate, the orthographic projection of the second part on the base substrate is offset from the orthographic projection of the second conductor part on the base substrate, and the first part and the second part are adjacent to each other.

[0014] Optionally, the side surface of the first conductor part and the side surface of the second conductor part are both inclined surfaces.

[0015] Optionally, the thin film transistor further includes a gate insulating layer and a gate, the gate insulating layer is arranged on the side of the active layer facing away from the substrate layer, the gate is arranged on the side of the gate insulating layer facing away from the substrate layer, and the interlayer insulating layer is arranged on the side of the gate insulating layer facing the gate and the side of the gate facing away from the substrate layer, wherein the orthographic projection of the gate on the substrate is offset from the orthographic projections of the first electrode and the second electrode on the substrate.

[0016] Optionally, the orthographic projection of the first electrode on the active layer completely covers the first conductor portion; and the orthographic projection of the second electrode on the active layer completely covers the second conductor portion.

[0017] Optionally, the first electrode is one of the source and the drain, the second electrode is the other of the source and the drain, and the first electrode, the second electrode, the first light-shielding conductive component, and the second light-shielding conductive component are made of the same material.

[0018] In another aspect, the present application provides a method for manufacturing a display panel, comprising the following steps:

[0019] forming a patterned active layer on one side of a substrate layer;

[0020] Conducting the patterned active layer to form a channel and a first conductor portion and a second conductor portion disposed on both sides of the channel;

[0021] forming an interlayer insulating layer on a side of the substrate layer facing the active layer and a side of the active layer facing away from the substrate layer, and forming a first via hole and a second via hole penetrating the interlayer insulating layer, wherein the first via hole exposes a surface and a side surface of the first conductor portion, and the second via hole exposes a surface and a side surface of the second conductor portion;

[0022] A patterned conductive layer is formed on the side of the interlayer insulating layer facing away from the substrate layer, wherein the conductive layer includes a first light-shielding conductive member filled in the first via hole, a second light-shielding conductive member filled in the second via hole, and a first electrode and a second electrode arranged on the side of the interlayer insulating layer facing away from the substrate layer, the first electrode is electrically connected to the first conductor portion through the first light-shielding conductive member, and the second electrode is electrically connected to the second conductor portion through the second light-shielding conductive member.

[0023] Optionally, before forming a patterned active layer on one side of a substrate layer, the method further includes the following steps:

[0024] Providing a base substrate, and forming a patterned light-shielding metal layer on one side of the base substrate;

[0025] forming the substrate layer on a side of the base substrate facing the light-shielding metal layer and a side of the light-shielding metal layer facing away from the base substrate;

[0026] The second via hole also penetrates the substrate layer and exposes the light-shielding metal layer, and the second electrode is electrically connected to the second conductor portion and the light-shielding metal layer through the second light-shielding conductive component.

[0027] Optionally, before the patterned active layer is subjected to conductorization, the following steps are further included:

[0028] forming a patterned gate insulating layer and a patterned gate on a side of the patterned active layer away from the substrate layer, wherein the gate is located on a side of the gate insulating layer away from the substrate layer;

[0029] The orthographic projections of the first electrode and the second electrode on the base substrate are staggered with the orthographic projection of the gate on the base substrate.

[0030] The present application provides a display panel and a method for preparing the same. The first light-shielding conductive member and the second light-shielding conductive member in the display panel can more effectively protect the channel of the thin-film transistor, greatly reducing the probability of the thin-film transistor experiencing device performance deterioration and reliability reduction due to side light irradiating the channel, thereby improving the device performance of the thin-film transistor and the display stability of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 A schematic cross-sectional view of a display panel provided in an embodiment of the present application, in a region where a thin film transistor is provided;

[0033] Figure 2 A schematic cross-sectional view of a patterned light-shielding metal layer formed on one side of a base substrate according to an embodiment of the present application;

[0034] Figure 3 A schematic cross-sectional view of forming a substrate layer on a side of the substrate facing the light-shielding metal layer and a side of the light-shielding metal layer facing away from the substrate, provided in an embodiment of the present application;

[0035] Figure 4 A schematic cross-sectional view of a patterned active layer formed on a side of a substrate layer facing away from a substrate substrate according to an embodiment of the present application;

[0036] Figure 5 A schematic cross-sectional view of forming a patterned gate insulating layer and a gate on a side of an active layer facing away from a substrate layer and then conducting the patterned gate insulating layer and the gate on a side of an active layer facing away from a substrate layer according to an embodiment of the present application;

[0037] Figure 6 A schematic cross-sectional view of a first via hole and a second via hole provided in an embodiment of the present application;

[0038] Figure 7 A schematic cross-sectional view of a patterned conductive layer formed on a side of an interlayer insulating layer facing away from a substrate layer according to an embodiment of the present application;

[0039] Figure 8 A cross-sectional schematic diagram of forming a passivation layer on the side of the interlayer insulating layer facing the conductive layer and the side of the conductive layer facing away from the substrate layer provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0041] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, examples of various specific processes and materials are provided in the present application, but a person of ordinary skill in the art will recognize the application of other processes and / or the use of other materials. Each of the following is described in detail. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0042] Figure 1 This is a cross-sectional diagram of a display panel provided in an embodiment of the present application in a region where a thin film transistor is provided. Figure 1As shown, the present application provides a display panel, which includes: a substrate layer 30 and a thin film transistor arranged on one side of the substrate layer 30; wherein the thin film transistor includes: an active layer 40, arranged on one side of the substrate layer 30, including a channel 43, a first conductor portion 41 and a second conductor portion 42 arranged on both sides of the channel 43; an interlayer insulating layer 70, arranged on the side of the substrate layer 30 facing the active layer 40 and the side of the active layer 40 away from the substrate layer 30; a first electrode 81 and a second electrode 82, arranged on the side of the interlayer insulating layer 70 away from the substrate layer 30. In which, the display panel also includes a first via hole 71 and a second via hole 72, a first light-shielding conductive member 83 and a second light-shielding conductive member 84, the first via hole 71 penetrates the interlayer insulating layer 70 and exposes the surface 411 and the side 412 of the first conductor part 41, the first light-shielding conductive member 83 is filled in the first via hole 71, the first electrode 81 is electrically connected to the first conductor part 41 through the first light-shielding conductive member 83, the second via hole 72 penetrates the interlayer insulating layer 70 and exposes the surface 421 and the side 422 of the second conductor part 42, the second light-shielding conductive member 84 is filled in the second via hole 72, and the second electrode 82 is electrically connected to the second conductor part 42 through the second light-shielding conductive member 84.

[0043] In the display panel provided by the present application, since the first via hole 71 penetrates the interlayer insulating layer 70 and exposes the surface 411 and the side surface 412 of the first conductor portion 41, the first light-shielding conductive member 83 filled in the first via hole 71 can establish a stable electrical connection between the first electrode 81 and the first conductor portion 41, and the side light-blocking range of the first light-shielding conductive member 83 can extend from the first electrode 81 to the substrate layer 30, greatly enhancing the light shielding from the side of the first conductor portion 41 away from the channel 43. Since the second via 72 penetrates the interlayer insulating layer 70 and exposes the surface 421 and the side 422 of the second conductor portion 42, the second light-shielding conductive member 84 filled in the second via 72 can establish a stable electrical connection between the second electrode 82 and the second conductor portion 42, and the side light-shielding range of the second light-shielding conductive member 84 can extend from the second electrode 82 to the substrate layer 30, greatly enhancing the light-shielding ability of the light from the side of the second conductor portion 42 away from the channel 43. Accordingly, since the first light-shielding conductive member 83 and the second light-shielding conductive member 84 can achieve the electrical connection function while having a larger side light-shielding range and stronger side light-shielding ability, the channel 43 of the thin-film transistor can be more effectively protected, greatly reducing the probability of the thin-film transistor having the problem of device performance deterioration and reliability reduction caused by the side light irradiating the channel 43, thereby improving the device performance of the thin-film transistor and the display stability of the display panel.

[0044] In addition, since the first via 71 and the second via 72 expose the side surfaces of the first conductor portion 41 and the second conductor portion 42 respectively, the first light-shielding conductive member 83 filled in the first via 71 can be overlapped with the surface 411 and the side surface 412 of the first conductor portion 41 at the same time, and the second light-shielding conductive member 84 filled in the second via 72 can be overlapped with the surface 421 and the side surface 422 of the second conductor portion 42 at the same time. Each light-shielding conductive member and the corresponding conductor portion has a larger overlap area and stronger overlap stability, thereby effectively reducing the contact resistance, reducing the resistance-capacitance (RC) delay of the display panel, and improving the display effect of the display panel.

[0045] Furthermore, the display panel is an OLED display panel, including a flexible OLED display panel or a rigid OLED display panel, but the present application does not limit the type of the display panel, and the display panel can also be a liquid crystal display panel or an inorganic light emitting diode (LED) display panel; the substrate layer 30 is a buffer functional layer; the first electrode 81 is one of the source or the drain, and the second electrode 82 is the other of the source or the drain, and the first electrode 81, the second electrode 82, the first light-shielding conductive member 83, and the second light-shielding conductive member 84 are made of the same material, that is, the first electrode 81, the second electrode 82, the first light-shielding conductive member 83, and the second light-shielding conductive member 84 can be formed by a film forming process.

[0046] Furthermore, the thin film transistor is a top-gate thin film transistor, and the thin film transistor also includes a gate insulating layer 50 and a gate 60, wherein the gate insulating layer 50 is arranged on the side of the active layer 40 away from the substrate layer 30, the gate 60 is arranged on the side of the gate insulating layer 50 away from the substrate layer 30, and the interlayer insulating layer 70 is arranged on the side of the substrate layer 30 toward the active layer 40, the active layer 40 toward the gate insulating layer 50, the gate insulating layer 50 toward the gate 60, and the gate 60 away from the substrate layer 30.

[0047] In some embodiments of the present application, the display panel also includes a base substrate 10 and a light-shielding metal layer 20 arranged on one side of the base substrate 10, and the base layer 30 is arranged on the side of the base substrate 10 facing the light-shielding metal layer 20 and the side of the light-shielding metal layer 20 away from the base substrate 10; wherein, the second via 72 also penetrates the base layer 30 and exposes the light-shielding metal layer 20, and the second electrode 82 is electrically connected to the second conductor portion 42 and the light-shielding metal layer 20 through the second light-shielding conductive member 84.

[0048] In the prior art, the second electrode 82 needs to be electrically connected to the electrode region in the active layer 40 and the light-shielding metal layer 20 through two spaced-apart vias. This makes the hole-making process more complicated, and the gap between the two spaced-apart vias is filled with a transparent interlayer insulating layer 70. The presence of this gap creates conditions for external light to illuminate the channel 43 of the active layer 40, which has an adverse effect on the device performance and reliability of the thin film transistor. However, in the display panel provided by the present application, since the second via 72 also penetrates the substrate layer 30 and exposes the light-shielding metal layer 20, the second light-shielding conductive member 84 filled in the second via 72 can achieve electrical connection with the light-shielding metal layer 20 and the second conductor portion 42 while maintaining an integrated structure. While ensuring electrical connection and achieving the light-shielding function, the gap region in the prior art is eliminated, further reducing the probability of device performance deterioration and reliability problems of the thin film transistor, further improving the device performance of the thin film transistor and the display stability of the display panel.

[0049] The structure of the second light-shielding conductive member 84 is further described below. Specifically, the second via 72 is a complete, integrated hole-like structure. The second light-shielding conductive member 84, which fills the second via 72, includes a first portion 841 and a second portion 842. The orthographic projection of the first portion 841 on the substrate 10 overlaps with the orthographic projection of the second conductor portion 42 on the substrate 10, while the orthographic projection of the second portion 842 on the substrate 10 is offset from the orthographic projection of the second conductor portion 42 on the substrate 10. Furthermore, the first portion 841 and the second portion 842 are adjacent to each other. In other words, the first portion 841 and the second portion 842 form a complete, integrated structure, effectively eliminating the gap region found in prior art and reducing the likelihood of device performance degradation and reliability issues in the thin-film transistor. Furthermore, the first portion 841 overlaps the surface 421 and side surface 422 of the second conductor portion 42, while the second portion 842 overlaps the surface of the light-shielding metal layer 20 exposed by the second via 72.

[0050] Moreover, since the second via 72 penetrates the interlayer insulating layer 70 and exposes the surface 411 and side surface 412 of the first conductor portion 41, and also penetrates the substrate layer 30 and exposes the light-shielding metal layer 20, the side light-blocking range of the second light-shielding conductive member 84 filled in the second via 72 can extend from the second electrode 82 to the light-shielding metal layer 20, further enhancing the light-blocking ability of the light from the side of the second conductor portion 42 away from the channel 43, thereby being able to more effectively protect the channel 43 of the thin film transistor.

[0051] In some embodiments of the present application, the first via 71 not only exposes the surface 411 and side surface 412 of the first conductor portion 41, but also exposes the surface of the substrate layer 30. Accordingly, the first light-shielding conductive member 83 filled in the first via 71 includes not only a portion overlapping the first conductor portion 41, but also a portion located on the side of the first conductor portion 41 facing away from the channel 43. This structure of the first light-shielding conductive member 83 can also increase the horizontal light-shielding area to a certain extent, thereby enhancing its light-shielding effect. Furthermore, the orthographic projection of the first light-shielding conductive member 83 on the substrate 10 at least partially does not overlap with the orthographic projection of the light-shielding metal layer 20 on the substrate 10.

[0052] In some embodiments of the present application, the side surface 412 of the first conductor portion 41 and the side surface 422 of the second conductor portion 42 are both inclined surfaces. Since the side surfaces 412 of the first conductor portion 41 and the side surfaces 422 of the second conductor portion 42 are both inclined surfaces, the first light-shielding conductive member 83 can have a larger overlap area with the side surface 412 of the first conductor portion 41, and the second light-shielding conductive member 84 can have a larger overlap area with the side surface 422 of the second conductor portion 42, thereby further reducing contact resistance, lowering the resistance-capacitance delay of the display panel, and improving the display effect of the display panel.

[0053] In some embodiments of the present application, the orthographic projection of the gate 60 on the base substrate 10 is staggered with the orthographic projections of the first electrode 81 and the second electrode 82 on the base substrate 10. In the prior art, overlap between the gate 60 and the source and drain electrodes generates overlap capacitance, increasing the RC delay in the display panel. However, by staggering the orthographic projection of the gate 60 on the base substrate 10 with the orthographic projections of the first electrode 81 and the second electrode 82 on the base substrate 10, the present application effectively eliminates the overlap capacitance between the gate 60 and the first electrode 81 and the second electrode 82, thereby reducing the RC delay of the display panel and improving the display quality of the display panel.

[0054] In some embodiments of the present application, the orthographic projection of the first electrode 81 on the active layer 40 completely covers the first conductor portion 41; the orthographic projection of the second electrode 82 on the active layer 40 completely covers the second conductor portion 42. Because the orthographic projections of the first electrode 81 and the second electrode 82 on the active layer 40 completely cover the first conductor portion 41 and the second conductor portion 42, the first electrode 81 and the second electrode 82 can effectively improve their ability to block light from the side of the first electrode 81 and the second electrode 82 facing away from the substrate layer 30, greatly reducing the probability of device performance degradation and reliability reduction of the thin film transistor due to top-surface light irradiating the channel 43, thereby improving the device performance of the thin film transistor and the display stability of the display panel.

[0055] In some embodiments of the present application, the display panel further includes a passivation layer 90 , which is disposed on a side of the interlayer insulating layer 70 facing away from the substrate layer 30 and on a side of the first electrode 81 and the second electrode 82 facing away from the substrate layer 30 .

[0056] In some embodiments of the present application, the display panel also includes a light-emitting functional layer arranged on the side of the passivation layer 90 away from the substrate layer 30, the light-emitting functional layer includes light-emitting units arranged in an array, the thin film transistor is used to control the light emission of the light-emitting unit, and the light-emitting unit is used to realize the display function.

[0057] In some embodiments of the present application, the display panel further includes an encapsulation layer disposed on the side of the light-emitting functional layer away from the substrate layer 30. The encapsulation layer can prevent external water and oxygen from invading the interior of the display panel, thereby improving the display stability of the display panel and increasing the service life of the display panel.

[0058] In some embodiments of the present application, the display panel may further include a touch function layer and an optical function layer. The touch function layer is, for example, arranged on the side of the encapsulation layer away from the substrate layer, so that the display panel also has a touch function. The optical function layer can be an anti-reflection layer arranged on the side of the encapsulation layer or the touch function layer away from the substrate layer 30, such as a polarizer or a color filter.

[0059] On the other hand, the present application also provides a method for preparing a display panel. Figure 2-Figure 8 , the method for preparing the display panel comprises the following steps:

[0060] Step S01: providing a base substrate 10 and forming a patterned light-shielding metal layer 20 on one side of the base substrate 10;

[0061] Step S02: forming the underlayer 30 on a side of the base substrate 10 facing the light-shielding metal layer 20 and a side of the light-shielding metal layer 20 facing away from the base substrate 10;

[0062] Step S03: forming a patterned active layer 40 on a side of the substrate layer 30 facing away from the base substrate 10;

[0063] Step S04: Conducting the patterned active layer 40 to form a channel 43 and a first conductor portion 41 and a second conductor portion 42 disposed on both sides of the channel 43;

[0064] Step S05: forming an interlayer insulating layer 70 on the side of the substrate layer 30 facing the active layer 40 and on the side of the active layer 40 facing away from the substrate layer 30, and forming a first via hole 71 and a second via hole 72 penetrating the interlayer insulating layer 70 by using a photolithography process;

[0065] Step S06: forming a patterned conductive layer 80 on a side of the interlayer insulating layer 70 away from the substrate layer 30;

[0066] Step S07 : forming a passivation layer 90 on the side of the interlayer insulating layer 70 facing the conductive layer 80 and on the side of the conductive layer 80 facing away from the substrate layer 30 .

[0067] Figure 2 This is a cross-sectional diagram of a patterned light-shielding metal layer formed on one side of a base substrate according to an embodiment of the present application. Figure 2 In step S01, the base substrate 10 is, for example, a glass substrate. Before forming a patterned light-shielding metal layer 20 on one side of the base substrate 10, the base substrate 10 is cleaned. The light-shielding metal layer 20 may be a single metal layer or a composite metal layer formed of at least one of Mo, Al, Cu, and Ti. The composite metal layer may be Mo / Cu, MoTi / Cu, Mo / Al, MoTi / Cu / MoTi, or the like. Furthermore, the thickness of the light-shielding metal layer 20 is 500-10,000 angstroms.

[0068] Figure 3 The cross-sectional diagram of the substrate layer formed on the side of the substrate facing the light-shielding metal layer and the side of the light-shielding metal layer facing away from the substrate is provided in the embodiment of the present application. Figure 3 In step S02, the substrate layer 30 is a buffer functional layer. The substrate layer 30 may be made of a single-layer inorganic film or a double-layer inorganic film formed of at least one of Si3N4, SiO2, and SiON. Furthermore, the substrate layer 30 may have a thickness of 1000-10000 angstroms.

[0069] Figure 4This is a cross-sectional diagram of a patterned active layer formed on the side of the substrate layer facing away from the substrate provided in an embodiment of the present application. Figure 4 In step S03, the active layer 40 is made of, for example, a metal oxide, such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), or indium gallium zinc tin oxide (IGZTO). Furthermore, the active layer 40 has a thickness of 100-1000 angstroms.

[0070] Figure 5 This is a schematic cross-sectional view of forming a patterned gate insulating layer and a gate on the side of the active layer facing away from the substrate layer and then conducting the patterned gate insulating layer and the gate. Figure 5 In the step S04, before the patterned active layer 40 is conductively converted, a gate insulating layer 50 is first formed on the entire surface of the substrate layer 30 facing the patterned active layer 40 and on the side of the patterned active layer 40 away from the substrate layer 30, and then a gate metal layer is formed on the entire surface of the gate insulating layer 50 away from the substrate layer 30. Then, a photomask is used to define the gate region in the thin film transistor, and the entire surface of the gate metal layer is wet-etched to form the patterned gate 60; and then, the gate 60 is used as a mask and a gate self-alignment process is used to dry-etch the entire surface of the gate insulating layer 50 to form the patterned gate insulating layer 50. Furthermore, the material of the gate insulating layer 50 is SiO2, and the thickness of the gate insulating layer 50 is 1000-3000 angstroms; the gate metal layer and the gate 60 can be a single metal layer or a composite metal layer formed by at least one of Mo, Al, Cu, and Ti, and the type of the composite metal layer can be Mo / Al / Mo, Al / Mo, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, etc., and the thickness of the gate metal layer and the gate 60 is 500-1000 angstroms.

[0071] Furthermore, in step S04, after forming the patterned gate insulating layer 50 and the patterned gate 60, the patterned active layer 40 is subjected to a plasma process for conductorization using the patterned gate 60 and the patterned gate insulating layer 50 as masks, thereby forming a channel 43 in the active layer 40 and a first conductor portion 41 and a second conductor portion 42 located on either side of the channel 43. Specifically, the first conductor portion 41 and the second conductor portion 42 are formed by conductorization of a metal oxide semiconductor prepared together with the channel 43, and thus have conductive properties; while under the shielding effect of the gate 60 and the gate insulating layer 50, the material of the channel 43 of the active layer 40 remains a metal oxide semiconductor and has semiconductor properties.

[0072] Figure 6 This is a cross-sectional diagram of the first via hole and the second via hole provided in the embodiment of the present application. Figure 6 In the step S05, the material of the interlayer insulating layer 70 is SiO2, the thickness of the interlayer insulating layer 70 is 3000-10000 angstroms, the yellow light process includes an etching process, and the first via hole 71 and the second via hole 72 are formed by the etching process, wherein the first via hole 71 exposes the surface 411 and the side surface 412 of the first conductor portion 41, and the second via hole 72 exposes the surface 421 and the side surface 422 of the second conductor portion 42.

[0073] Figure 7 A schematic cross-sectional view of a patterned conductive layer formed on the side of the interlayer insulating layer facing away from the substrate layer provided in an embodiment of the present application. Figure 7 In step S06, the conductive layer 80 may be a single metal layer or a composite metal layer formed of at least one of Mo, Al, Cu, and Ti. The composite metal layer may be formed of Mo / Al / Mo, Al / Mo, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, or the like. The conductive layer 80 includes a first light-shielding conductive member 83 filling the first via 71, a second light-shielding conductive member 84 filling the second via 72, and a first electrode 81 and a second electrode 82 disposed on a side of the interlayer insulating layer 70 facing away from the substrate layer 30. The first electrode 81 is electrically connected to the first conductor portion 41 via the first light-shielding conductive member 83, and the second electrode 82 is electrically connected to the second conductor portion 42 via the second light-shielding conductive member 84. Furthermore, the first and second electrodes 81 and 82 have the same thickness, for example, 500-10,000 angstroms.

[0074] Furthermore, the second via hole 72 also penetrates the substrate layer 30 and exposes the light-shielding metal layer 20 , and the second electrode 82 is electrically connected to the second conductor portion 42 and the light-shielding metal layer 20 through the second light-shielding conductive member 84 .

[0075] Furthermore, the orthographic projections of the first electrode 81 and the second electrode 82 on the base substrate 10 are staggered with the orthographic projection of the gate 60 on the base substrate 10 .

[0076] Furthermore, the orthographic projection of the first electrode 81 on the active layer 40 completely covers the first conductor portion 41 ; the orthographic projection of the second electrode 82 on the active layer 40 completely covers the second conductor portion 42 .

[0077] Figure 8 A schematic cross-sectional view of forming a passivation layer on the side of the interlayer insulating layer facing the conductive layer and the side of the conductive layer facing away from the substrate layer provided in an embodiment of the present application. Figure 8 In the step S07, the material of the passivation layer 90 is SiO2, and the thickness of the passivation layer 90 is 1000-5000 angstroms.

[0078] In summary, the present application provides a display panel and a method for manufacturing the same. The display panel includes a thin film transistor, which includes a channel, a first conductor portion and a second conductor portion disposed on either side of the channel, an interlayer insulating layer, and a first electrode and a second electrode. The display panel further includes a first via hole and a second via hole, wherein the first via hole penetrates the interlayer insulating layer and exposes the surface and side surfaces of the first conductor portion, a first light-shielding conductive member is filled in the first via hole, and a second via hole penetrates the interlayer insulating layer and exposes the surface and side surfaces of the second conductor portion, and a second light-shielding conductive member is filled in the second via hole. The first and second light-shielding conductive members in the display panel provided by the present application can more effectively protect the channel of the thin film transistor, greatly reducing the probability of device performance degradation and reduced reliability of the thin film transistor due to side light irradiating the channel, thereby improving the device performance of the thin film transistor and the display stability of the display panel.

[0079] The above is a detailed introduction to a display panel and a preparation method thereof provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: The display panel includes: a base substrate, a base layer, and a thin film transistor disposed on one side of the base layer, wherein the base substrate is located on a side of the base layer away from the thin film transistor; wherein the thin film transistor includes: an active layer, disposed on one side of the substrate layer, comprising a channel, a first conductor portion and a second conductor portion disposed on both sides of the channel; an interlayer insulating layer, disposed on a side of the substrate layer facing the active layer and a side of the active layer facing away from the substrate layer; A first electrode and a second electrode are arranged on a side of the interlayer insulating layer away from the substrate layer; a gate, wherein the orthographic projection of the gate on the substrate is staggered with the orthographic projections of the first electrode and the second electrode on the substrate; The display panel further includes a first via hole and a second via hole, a first light-shielding conductive member, a second light-shielding conductive member, and a light-shielding metal layer, wherein the light-shielding metal layer is located between the base substrate and the base layer, and the light-shielding metal layer overlaps with the channel, the first conductor portion, and the second conductor portion; The first via hole penetrates the interlayer insulating layer and exposes the surface and side surfaces of the first conductor portion. A portion of the first via hole is staggered from the light-shielding metal layer. The first light-shielding conductive member is filled in the first via hole. The first electrode is electrically connected to the first conductor portion via the first light-shielding conductive member. The first light-shielding conductive member overlaps the surface and side surfaces of the first conductor portion. An orthographic projection of the first light-shielding conductive member on the base substrate at least partially does not overlap with an orthographic projection of the light-shielding metal layer on the base substrate. An orthographic projection of the first electrode on the active layer completely covers the first conductor portion. The second via penetrates the interlayer insulating layer and exposes the surface and side of the second conductor part. The second via also penetrates the substrate layer and exposes the light-shielding metal layer. The second light-shielding conductive member is filled in the second via. The second electrode is electrically connected to the second conductor part through the second light-shielding conductive member. The second light-shielding conductive member is overlapped with the surface and side of the second conductor part at the same time. The orthographic projection of the second electrode on the active layer completely covers the second conductor part.

2. The display panel according to claim 1, wherein: The second via hole also penetrates the substrate layer and exposes the light-shielding metal layer. The second electrode is electrically connected to the second conductor portion and the light-shielding metal layer through the second light-shielding conductive component.

3. The display panel according to claim 2, wherein: The second light-shielding conductive component includes a first part and a second part, the orthographic projection of the first part on the base substrate is overlapped with the orthographic projection of the second conductor part on the base substrate, the orthographic projection of the second part on the base substrate is staggered with the orthographic projection of the second conductor part on the base substrate, and the first part and the second part are adjacent to each other.

4. The display panel according to claim 3, wherein: The side surfaces of the first conductor portion and the second conductor portion are both inclined surfaces.

5. The display panel according to claim 2, wherein: The thin film transistor also includes a gate insulating layer, which is arranged on the side of the active layer facing away from the substrate layer, the gate is arranged on the side of the gate insulating layer facing away from the substrate layer, and the interlayer insulating layer is arranged on the side of the gate insulating layer facing the gate and the side of the gate facing away from the substrate layer.

6. The display panel according to claim 1, wherein: The first electrode is one of the source and the drain, the second electrode is the other of the source and the drain, and the first electrode, the second electrode, the first light-shielding conductive member, and the second light-shielding conductive member are made of the same material.

7. A method for preparing a display panel, characterized in that: The method for preparing the display panel comprises the following steps: providing a substrate; forming a patterned light-shielding metal layer on one side of the base substrate; forming a substrate layer on a side of the light-shielding metal layer facing away from the substrate; forming a patterned active layer on a side of the substrate layer facing away from the substrate base; Conducting the patterned active layer to form a channel and a first conductor portion and a second conductor portion disposed on both sides of the channel, wherein the light-shielding metal layer overlaps the channel, the first conductor portion, and the second conductor portion; forming an interlayer insulating layer on a side of the active layer facing away from the base substrate, and forming a first via hole penetrating the interlayer insulating layer and a second via hole penetrating the interlayer insulating layer and the base layer, wherein the first via hole exposes the surface and side surfaces of the first conductor portion and a portion of the first via hole is staggered from the light-shielding metal layer, and the second via hole exposes the surface and side surfaces of the second conductor portion and the light-shielding metal layer; forming a patterned gate insulating layer and a patterned gate on a side of the patterned active layer away from the base substrate, wherein the gate is located on a side of the gate insulating layer away from the base substrate; A patterned conductive layer is formed on the side of the interlayer insulating layer facing away from the base substrate, wherein the conductive layer includes a first light-shielding conductive member filled in the first via hole, a second light-shielding conductive member filled in the second via hole, and a first electrode and a second electrode arranged on the side of the interlayer insulating layer facing away from the base substrate, the first electrode is electrically connected to the first conductor portion through the first light-shielding conductive member, the first light-shielding conductive member is simultaneously overlapped with the surface and side of the first conductor portion, the orthographic projection of the first light-shielding conductive member on the base substrate and the orthographic projection of the light-shielding metal layer on the base substrate at least partially do not overlap, the second electrode is electrically connected to the second conductor portion through the second light-shielding conductive member, the second light-shielding conductive member is simultaneously overlapped with the surface and side of the second conductor portion, the second electrode is electrically connected to the second conductor portion and the light-shielding metal layer through the second light-shielding conductive member, the orthographic projection of the first electrode on the active layer completely covers the first conductor portion, and the orthographic projection of the second electrode on the active layer completely covers the second conductor portion; the orthographic projections of the first electrode and the second electrode on the base substrate are staggered with the orthographic projection of the gate on the base substrate.

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