Charge amplification circuit and method

Abstract

Embodiments of the present disclosure relate to charge amplification circuits and methods. A circuit includes an amplifier, a bias voltage node, and a first set of switches configured to couple first and second input nodes to the bias voltage node and to couple first and second output nodes of the amplifier based on a first reset signal having a first value. The first and second feedback branches each include a corresponding RC network comprising a plurality of capacitors. The first and second feedback branches also include a second set of switches between the input node and the capacitor and a third set of switches between the input node and the plurality of capacitors. These switches selectively couple the capacitor to the input node and the output node based on a second reset signal having a first value. The second reset signal maintains the first value for a determined time interval exceeding a time interval during which the first reset signal has the first value.

Description

Technical Field

[0001] This specification relates to charge amplifier circuits and methods thereof.

[0002] One or more embodiments may be applied to a capacitive sensor, such as a pressure sensor. Background Art

[0003] Charge amplifier circuits are suitable for various electronic applications. For example, charge amplifier circuits can be used in the readout chain of capacitive micro-electromechanical system (MEMS) sensors (ie, sensors configured to convert changes in a given physical quantity into capacitive displacement).

[0004] In this case, the charge amplifier is used to convert the change in charge stored in the capacitive element into a voltage signal, thereby facilitating the signal processing by another signal processing chain. For example, in the case of a digital signal processing chain, the charge amplifier is coupled to an analog-to-digital converter (ADC for short), which is configured to provide a digital representation of the input voltage signal, optionally with anti-aliasing filtering applied.

[0005] Existing charge amplifier arrangements may suffer from one or more of the following disadvantages:

[0006] There is an offset error that deteriorates the accuracy.

[0007] The detrimental effect of increasing offset error due to a reduction in the capacitance used in the feedback branch of the amplifier,

[0008] The deleterious effects of offset error grow based on the increase in gain from the offset source. Summary of the Invention

[0009] One or more embodiments of the present disclosure help to overcome the above-mentioned shortcomings.

[0010] According to one or more embodiments, technical benefits may be realized by a charge amplifier circuit having the features set forth and described herein.

[0011] One or more embodiments may relate to corresponding capacitive sensors (eg, pressure sensors).

[0012] One or more embodiments may be directed to a corresponding method of operating a circuit / apparatus.

[0013] One or more embodiments may reduce power consumption and facilitate integration of charge amplifiers in low-power applications.

[0014] One or more embodiments may facilitate compensating for, and even eliminating, offset errors in an output voltage signal produced by a charge amplifier circuit.

[0015] In one or more embodiments, the offset is eliminated in an improved manner, such as faster. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] One or more embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0017] Figure 1 and Figure 2 is an exemplary diagram of a charge amplifier,

[0018] Figure 3 Yes Operation Figure 2 An exemplary time diagram of the charge amplifier signal,

[0019] Figure 4 is an exemplary circuit diagram of an alternative charge amplifier,

[0020] Figure 5 is an exemplary circuit diagram of a charge amplifier circuit according to the present disclosure,

[0021] Figure 6 is an exemplary timing diagram of signals when operating the circuit diagram according to the present disclosure,

[0022] Figure 7A 、 Figure 7B and Figure 7C yes Figure 5 An exemplary circuit diagram of the operating stages of the circuit is shown in FIG. DETAILED DESCRIPTION

[0023] In the following description, one or more specific details are shown to provide a deeper understanding of the examples of the embodiments of this specification. The embodiments can be obtained without one or more specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure certain aspects of the embodiments.

[0024] References to "an embodiment" or "one embodiment" within the scope of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more points of this specification do not necessarily refer to the same embodiment.

[0025] Furthermore, the particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0026] In all the drawings attached hereto, the same parts or elements are denoted by the same reference numerals / numbers, and the corresponding description will not be repeated for the sake of brevity.

[0027] The reference signs used herein are provided for convenience only and therefore do not limit the degree of protection or scope of the embodiments.

[0028] For simplicity, in the following detailed description, the same reference numerals may be used to represent nodes / lines in a circuit and signals that may appear at the nodes or lines.

[0029] like Figure 1 As illustrated in FIG. , a (e.g., continuous-time) charge amplifier circuit 10 includes:

[0030] Capacitive sensor C S (eg, a MEMS sensor), which for example includes a pair of (eg, parallel) sensing capacitors C0, a sensor C S With a first input node V IN1 , the first input node is configured to: respond to the voltage applied to the first input node V IN1 The first voltage signal V0 (eg, having an amplitude V R and frequency F R =1 / T R square waveform), converting the change of physical quantity (e.g., acceleration, position, or pressure) into capacitance displacement ±ΔC,

[0031] An operational transconductance amplifier (OTA) 100 having:

[0032] The first (eg, non-inverting) input node V INp , coupled (eg, directly) to the sensor C S and via a first RC network R F 、C F The first feedback branch is coupled to the first output node V of the OTA 100. OUTn ,and

[0033] The second (eg, inverting) input node V INn , coupled (eg, directly) to the sensor C S and coupled to the second output node V via a second feedback branch comprising a second RC network. OUTp , the second RC network is for example connected to the first RC network R F 、C F same.

[0034] As mentioned above, existing charge amplifiers can suffer from offset errors whose recovery time can exceed design constraints due to the large time constant defined by the large feedback resistors used to bias the virtual ground of such circuits.

[0035] Reducing the startup time in the sensor interface is particularly relevant in situations where there is a cyclic transition from a "normal" operating mode to a "power-down" mode (and vice versa). This so-called "low-power mode" is relevant for applications where power consumption is to be reduced, such as mobile devices with limited battery life.

[0036] like Figure 1 As illustrated in FIG, the charge amplifier 10 is configured to sense differential charge injected toward its virtual ground. Figure 1 In the exemplary case, the differential charge has a value of 2V R ΔC. For example, the differential charge is integrated in the feedback capacitor C of this stage F On, a differential output voltage signal V OUT (e.g., also having a square waveform), the differential output voltage signal can be expressed as:

[0037]

[0038] like Figure 1 As illustrated in FIG, the amplifier circuit 10 includes a reference branch, referred to as a “dummy” capacitor C R For example, the dummy capacitor C R includes a copy of the sensing capacitor C0 at rest (ie, without any signal applied to it) and having a corresponding input node V IN2 , the input node is configured to receive a second “test” voltage signal V0 ′, for example, orthogonal to the first voltage signal V0 , such that V0 ′=not( V0 ).

[0039] For example, the capacitance displacement ΔC represents the sensed capacitance C in response to an external change in the physical quantity to be measured. S For example, the sensitivity of 1fF (1fF = 1 femtofarad = 10 -15 This capacitance change ΔC is associated with a full-scale measurement space of 100 fF to 10s of fF.

[0040] Considering the differential output voltage signal V discussed earlier OUT The expression and reduced sensitivity ΔC, particularly relevant for certain types of capacitive sensors such as MEMS sensors, results in a high input voltage amplitude V R and a small feedback capacitor C F It helps to provide an appropriate amplification factor. For example, an appropriate amplification factor refers to a gain value that properly addresses the performance involved in the entire readout chain.

[0041] In order to desirably limit the total power consumption of the entire system, the input voltage V R The value of can be limited below the power supply level. This results in the amplifier's feedback capacitor C F Hold is the main design knob that can be used to increase the gain of the stage.

[0042] like Figure 1 As shown in FIG, the feedback branch R of OTA 100 is used. F 、C F The resistor R F To set the input common mode V CM In the example considered, the feedback resistor R F The size can be determined so that the feedback capacitance C F In the half-cycle interval T R / 2 and the discharge at the signal frequency F R For this purpose, taking into account the order of magnitude of the capacitances involved, the result is the feedback resistor R F Must be selected as GΩ (1GΩ=1Gigaohm=10 9 Ω), so at the signal frequency F R There is negligible thermal noise.

[0043] like Figure 2 As illustrated in FIG. 1 , the charge amplifier circuit 10 may further include:

[0044] Common mode node V CM , the common-mode node is configured to receive a common-mode voltage level V CM ,as well as

[0045] A set of reset switches S IN1 、S IN2 、S INp 、S INn 、S OUT ,include:

[0046] First reset switch S IN1 , is configured to selectively convert the common-mode V CM coupled to the first input node V IN1 ,

[0047] Second reset switch S IN2 , is configured to selectively convert the common-mode V CM coupled to the second input node V IN2 ,

[0048] The third reset switch S INp , is configured to selectively convert the common-mode V CM coupled to the first V of the OTA 100 INp Input node,

[0049] Fourth reset switch S INn , is configured to selectively convert the common-mode V CMcoupled to the second V of the OTA 100 INn Input node,

[0050] Fifth reset switch S OUT , configured to selectively couple between the output nodes of the OTA 100.

[0051] like Figure 2 As shown in the example, the reset switch S is driven by the reset signal RST. IN1 、S IN2 、S INp 、S INn 、S OUT For example, switch S IN1 、S IN2 、S INp 、S INn 、S OUT Configured to be in a first (eg, closed) state when the reset signal RST has a first value (eg, “1”) and in a second (eg, open) state when the signal RST has a second value (eg, “0”).

[0052] like Figure 2 Examples in:

[0053] The third and fourth switches S INp 、S INn is configured to connect the input node V INp 、V INn "Short circuit" to the common mode voltage V CM ,

[0054] Fifth switch SW OUT is configured to short the output nodes of the OTA together,

[0055] Therefore, the first and second switches S IN1 and S IN2 is configured to reset the sensor and the dummy capacitor C S 、C R .

[0056] Figure 2 A possible disadvantage of the arrangement illustrated in FIG is that a fast startup may be almost impossible because there is hardly any charge stored in the circuit 10 that can reach the desired common mode bias point V suitable for such a fast startup. CM .

[0057] Figure 3 yes Figure 2 An exemplary illustration of the signals involved in the startup phase of a circuit.

[0058] like Figure 3 As exemplified in, for example:

[0059] At an initial time t0, the power-down signal PD is set to a first value (e.g., "1"), starting a portion P0 of the startup phase; for example, during the portion P0, the circuit 10 is in a power-down state (e.g., an "off" state);

[0060] At time t1, in the second portion P1, the power-off signal is set to a second value (e.g., "0") and the reset signal RST is set to a first value (e.g., "1"); in other words, after power-off, power-on and resetting of the circuit 10 begin during the phase portion P1; in particular, the sensor capacitance C of the sensor S and the OTA input node via switch SW RST Coupled to V CM , and the output of the amplifier is coupled between them;

[0061] At time t2, in the third portion P2, the reset signal RST is set to a second value (eg, “0”) and the sensor C S and dummy C R The capacitance is coupled to the corresponding drive signal V0, V0', and the offset level V at the input node OFS Based on the input node V of OTA 100 INp , V INn The total capacitance C of the virtual ground at VG (exist Figure 2 The dotted line in the figure shows the change of the

[0062] For example, the total capacitance C VG It can be expressed as:

[0063] C vG =2C0+C G +C pAR

[0064] in:

[0065] C0 is sensor C S The sensing capacitance of the sensing branch and the dummy capacitance C R The value of

[0066] C G is the input capacitance of OTA 100, and

[0067] C PAR This is, for example, the parasitic capacitance of the sensor and routing.

[0068] In one or more embodiments, the sensing capacitance C0 may have a value between 100 fF and 1 pF (1 pF = 1 pF = 10-100 fF). 12 value within the range of .

[0069] In one or more embodiments, particularly for low-noise OTAs with low flicker and high input transconductance, the (gate) capacitance C of the OTA 100 may be G It can have a value of about several hundred fF.

[0070] In one or more embodiments, the parasitic capacitance C PAR It may have a value in the range of about 100 fF-1 pF, especially since contributions from parasitic capacitances of the sensor (eg, in the pF scale) and wiring (eg, hundreds of fF) are taken into account.

[0071] The feedback capacitor C F The total offset charge Q transferred FOS Expressed as:

[0072] QoF s =VOF s CVG.

[0073] Results, such as Figure 3 As illustrated in FIG, the output signal in phase P2 can be expressed as:

[0074]

[0075] like Figure 3 As illustrated in FIG, at the beginning of the portion P2, after time t2, once the reset signal RST reaches the second value, the feedback capacitor C F There is an offset charge Q OFS Once the output signal value is reached The circuit then moves to a steady-state condition where the output signal is equal to the offset voltage V OFS , that is, V OUT =V OFS For example, achieving this steady-state condition involves the feedback resistor R F For feedback capacitor C F The discharge is carried out with a time constant τ F =R F C F occur.

[0076] like Figure 3 As illustrated in the example, this time constant can produce an output voltage V OUT The relatively slow downward trend of the output voltage (relative to the upward trend of the output voltage).

[0077] like Figure 3 As illustrated in , with respect to the “ideal” steady-state evolution (shown by the dashed line), Figure 2 The circuit can achieve steady-state conditions at output values ​​V OFS OUTThis may be due to, for example, an offset factor equal to the total capacitance C VG Ratio of feedback capacitance C VG / C F For example, as mentioned above, based on the sensor technology used and based on the amplifier's feedback capacitor C F As a result of this startup, the output signal may take a relatively long time to decrease from the peak value. Return to the steady-state offset value V OFS .

[0078] Figure 4 A possible solution to the offset problem is shown in FIG.

[0079] like Figure 4 As illustrated in FIG. 1 , the third and fourth reset switches S INp 、S INn is coupled across the input and output nodes of the amplifier 100 to replace the common-mode voltage V CM (like Figure 2 In this way, for example during a reset phase (eg, RST="1"), the offset is stored in the total capacitance C VG However, no charge is transferred to the feedback capacitor C F Thus, once reset is released (eg, RST="0"), circuit 40 already has an offset voltage applied at its output node, thereby accelerating startup.

[0080] Figure 4 The solution exemplified in may still have some drawbacks and limited applicability in low power applications. For example, the capacitor C VG and C F The ratio C VG / C F It is a parameter related to the offset amplification factor and feedback gain attenuation.

[0081] For example, feedback gain reduction has a positive effect on circuit stability, reducing the closed-loop amplifier's gain-bandwidth product (GBWP) by a factor equal to the ratio C VG / C F This helps, for example, to reduce the current consumption of the output stage when using a multi-stage OTA.

[0082] Existing solutions can use an OTA buffer configuration to eliminate offset-related errors. However, this approach lacks capacitor partitioning and therefore has no positive impact on GBWP. This leads to an increased risk of instability. To combat this increased instability, existing solutions increase current consumption. However, these solutions are difficult to integrate with low-power applications.

[0083] The solution discussed herein facilitates offset cancellation while involving reduced effort relative to the effort associated with stabilizing the OTA 100 at its GBWP frequency, thus counteracting the increase in current consumption that would otherwise be involved.

[0084] In one or more embodiments, introducing a delayed reset phase can facilitate overcoming the aforementioned limitations in stability and power consumption.

[0085] like Figure 5 As shown in FIG. 5 , the charge amplifier circuit 50 includes an operational transconductance amplifier (OTA) 500, which includes:

[0086] The first (eg, non-inverting) input node V INp , is configured to be coupled (eg directly) to the capacitive sensor C S and coupled to the first output node V of the OTA 100 via the first feedback branch. OUTn The first feedback branch includes a first RC network R F 、C F1 、C F2 , the first RC network includes, for example, at least a first capacitor C connected in parallel therebetween F1 and the second capacitor C F2 ,as well as

[0087] The second (eg, inverting) input node V INn , coupled (eg, directly) to the capacitive sensor C S and coupled to the second output node V via a second feedback branch comprising a second RC network. OUTp , the second RC network is for example connected to the first RC network R F 、C F1 、C F2 same,

[0088] Common mode node V CM , the common-mode node is configured to receive a common-mode voltage level V CM ,

[0089] The first set of reset switches S IN1 、S IN2 、S INp 、S INn 、S OUT , is configured to be driven by the first reset signal RST, the first set of reset switches S IN1 、S IN2 、S INp 、S INn 、S OUT Arranged and configured along the above Figure 2 The discussed line operates similarly to the reference reset switch,

[0090] The second set of switches S F1A 、S F1B 、S F1C 、S F1D 、S F2A 、S F2B 、S F2C 、S F2D , is configured to be driven by the second “delayed” reset signal RSTD, the second set of switches S F1A 、S F1B 、S F1C 、S F1D 、S F2A 、S F2B 、S F2C 、S F2D The switches in the OTA 500 are configured to couple the capacitors CF1 and CF2 in the first feedback branch and the second feedback branch of the OTA 500 to their inputs V Inp 、V INn and / or output node V OUTp 、V OUTn .

[0091] For example, the feedback capacitor C in the feedback branch of OTA 500 F1 、C F2 Can be equal, for example C F1 =C F2 =C F .

[0092] A circuit as exemplified herein comprises:

[0093] An amplifier (eg, 500) having a first input node (eg, V INp ) and a second input node (e.g., V INn ), configured to be coupled to at least one capacitor (e.g., C S , C D ) to detect a capacitance change signal (e.g., ΔC) indicating a change in the value of the at least one capacitor from the capacitor, the amplifier (e.g., a single-stage or multi-stage OTA) having a first output node (e.g., V OUTp ) and a second output node (e.g., V OUTn ),

[0094] Bias voltage node (e.g., V CM ), configured to provide a bias voltage level,

[0095] The first set of switches (e.g., S INp 、S Inn 、S OUT), configured to: couple the first input node and the second input node of the amplifier to the bias voltage node based on a first reset signal (e.g., RST) having a first value, and couple between a first output node and a second output node of the amplifier,

[0096] The first feedback branch (eg, R F 、C F1 、C F2 ), including a first RC network including a first capacitor and a second capacitor (e.g., C F1 、C F2 ), the first feedback branch is coupled between the first output node and the first input node of the amplifier,

[0097] The second feedback branch (eg, R F 、C F1 、C F2 ), including a second RC network, wherein the second RC network includes a third capacitor and a fourth capacitor (for example, C F1 、C F2 ), the second feedback branch is coupled between the second output node and the second input node of the amplifier,

[0098] The first and second feedback branches also include:

[0099] a second set of switches (e.g., SF1A, SF1C, SF2A, SF2C) intermediate the first and second input nodes of the amplifier and the first, second, third, and fourth capacitors, and

[0100] A third set of switches (e.g., SF1B, SF1D, SF2B, SF2D) is provided between the first and second output nodes of the amplifier and the first, second, third, and fourth capacitors.

[0101] in,

[0102] The switches in the second set of switches are configured to selectively couple one of the first and second capacitors in the first feedback branch and one of the third and fourth capacitors in the second feedback branch to the first and second input nodes of the amplifier based on a second reset signal (e.g., RSTD) having a first value,

[0103] The switches in the third set of switches are configured to selectively couple the one of the first and second capacitors in the first feedback branch and the one of the third and fourth capacitors in the second feedback branch to the first and second output nodes of the amplifier (e.g., 500) based on a second reset signal having a first value,

[0104] wherein the first reset signal is configured to have a first value during a first time interval (e.g., P0, P1) and to switch from the first value to a second value (e.g., t2) after the first time interval,

[0105] In response to the first reset signal switching from the first value to the second value, the second reset signal is reset at another time interval (eg, P2, T DELAY ), and the first reset signal has the first value during the first time interval.

[0106] As illustrated herein, the circuit includes a power supply for an amplifier, which is configured to be powered off based on a power-off (e.g., PD) signal having a first value, a first time interval (in which the first reset signal is configured to have a first value) includes a first sub-interval (e.g., P0) and a second sub-interval (e.g., P1), the power-off signal has the first value during the first sub-interval and the second value during the second sub-interval, resulting in the power supply for the amplifier being powered off during the first sub-interval.

[0107] As illustrated here, the amplifier has a signal amplification bandwidth, and wherein the further time interval (eg, P2, T DELAY ) has a duration that is a function of the signal amplification bandwidth of the amplifier, during which time interval the first reset signal has the first value.

[0108] As illustrated here, the amplifier is a fully differential (eg, multi-stage or single-stage) operational transconductance amplifier OTA.

[0109] As illustrated here, the second feedback branch is a copy of the first feedback branch.

[0110] For example:

[0111] The first feedback branch comprises a parallel connection of a first capacitor and a second capacitor, which is in turn arranged to be connected to a resistor (eg R F )in parallel,

[0112] The second set of switches includes:

[0113] The first switch (eg, S F1A ), is inserted into the first input node of the amplifier and a first capacitor (e.g., C F1 )between,

[0114] The second switch (eg, S F2A ), is inserted into the first input node of the amplifier and a second capacitor (e.g., C F2 )between,

[0115] The third set of switches includes:

[0116] The corresponding first switch (eg, S F1B ), is inserted into the first output node of the amplifier and the first capacitor,

[0117] The corresponding second switch (eg, S F2B ), is inserted into the first output node of the amplifier circuit and a second capacitor (e.g., C F2 )between.

[0118] A sensor device (e.g., 50) as illustrated herein comprises:

[0119] At least one detection capacitor (e.g., C S ), configured to convert a change in a physical quantity into a capacitance change signal (eg, ΔC),

[0120] Reference capacitance element (e.g., C R ), coupled to the at least one capacitor, the reference capacitive element having a capacitance value substantially equal to a static capacitance value (e.g., C0) of the at least one capacitor,

[0121] The circuit according to the present disclosure has an input node (eg, V ) coupled at an end of the at least one detection capacitor and at an end of the reference capacitor element. INp 、V INn ),

[0122] a control circuit arrangement coupled to the circuit and configured to provide a first reset signal (e.g., RST) and a second reset signal (e.g., RSTD) to the circuit,

[0123] wherein the first reset signal is configured to have a first value during a first time interval and to switch from the first value to a second value after the first time interval,

[0124] In response to the first reset signal (RST) switching from the first value to the second value, the second reset signal is switched to the second value for a further time interval (eg, T) exceeding the first time interval (eg, P0, P1). DELAY ), and the first reset signal has the first value during the first time interval.

[0125] As illustrated here, the sensor includes an additional set of switches (e.g., S IN1 、S IN2 ), configured to: reset the input node (eg, V IN1 ) and the input node of the reference capacitor element (e.g., VIN2 ) is coupled to the bias voltage node.

[0126] In one or more embodiments, executing the reset phase of the OTA stage 500 in the circuit 50 includes:

[0127] In the first reset phase, based on the first reset signal RST, the virtual ground and the shortcut of the two output nodes are coupled, and

[0128] In the second reset phase, further actions as described below are performed based on the second reset signal RSTD. The second reset phase is delayed relative to the first reset phase by a time interval determined based on the bandwidth of the OTA 500 .

[0129] For example, the second reset signal RSTD controls the feedback capacitance and input node of the OTA circuit 500 , as discussed below.

[0130] like Figure 6 Examples in:

[0131] At an initial time t0, during an initial phase P0, the circuit 50 is turned off and remains off until the power-down signal PD is at a first signal level (eg, “1”),

[0132] At time point t1 when phase P0 ends and phase P1 begins, when the first and second reset signals RST and RSTD are at a first signal level (eg, “1”), the power-down signal switches to a second signal level (eg, “0”). Figure 7A is an example of circuit 50 during phase P1. Figure 7A As shown in the example, the first set of switches S IN1 、S IN2 、S INp 、S INn 、S OUT The switches in the second set of switches S F1A 、S F1B 、S F2A 、S F2B 、S F1C 、S F1D 、S F2C 、S F2D The switches in the first (eg, “closed”) state couple the corresponding nodes to the common-mode bias voltage level VCM, thereby causing all capacitors C in the feedback branch of the OTA 500 to be F1 、C F2 The result is (see, for example, Figure 6 ) outputs a differential voltage level V during phase P1 OUT is ground level.

[0133] like Figure 6As illustrated in FIG, at time point t2 when phase P1 ends and phase P2 begins, the first reset signal RST switches to the second signal level (eg, “0”), while the second reset switch RSTD remains at the first signal level (eg, “1”). Figure 7B is an example of circuit 50 during phase P2. Figure 7B As shown in the example, the first set of switches S IN1 、S IN2 、S INp 、S INn The fifth S in OUT is released and enters the second state (eg, “off”), while the second set of switches S F1A 、S F1B 、S F2A 、S F2B 、S F1C 、S F1D 、S F2C 、S F2D The switches in the circuit remain in a first (eg, "closed") state and couple the corresponding nodes to a common-mode bias voltage level V CM .

[0134] like Figure 6 and Figure 7B As illustrated in FIG, during phase P2, the offset voltage V OFS is transmitted to the output node V OUTp , V OUTn , and by the amplification factor (1+C VG / C F ) is amplified, where the charge V OFS *C VG is stored in C VG and C F1 In the middle, the capacitor C F2 is shorted to the common bias voltage V CM .

[0135] like Figure 7B As shown in the example, in order to avoid signal cancellation, the input node V of the circuit 15 IN1 During phase P2, the coupling to the common-mode level V CM .

[0136] like Figure 6 As illustrated in FIG, at time t3 at which the phase P2 ends and the phase P3 begins, the second reset switch RSTD switches to the second signal level (eg, “0”). Figure 7C is an example of circuit 50 during phase P3. Figure 7C As shown in the example, based on the second reset signal RSTD, the second set of switches S F1A 、S F1B 、SF2A 、S F2B 、S F1C 、S F1D 、S F2C 、S F2D The switch in the first feedback capacitor C F1 Decouple from OTA 500 and discharge to the common-mode voltage level V CM The second feedback capacitor C F2 Start from the discharge state. Figure 6 and Figure 7C As shown in FIG. 5 , the output node V OUTn 、V OUTp The output differential voltage VOUT reaches the steady-state voltage value V during phase P3. OFS For example, the time interval T between the second time interval t2 and the third time interval t3 DELAY is equal to the time constant for reaching this steady-state condition.

[0137] like Figure 6 As shown in the example, the time interval T DELAY has a duration determined by the bandwidth of the amplifier and is an order of magnitude slower than the “slow” time constant τ of the feedback network F =R F C F high.

[0138] A method of operating a circuit or sensor device according to the present disclosure, comprising:

[0139] Provide a bias voltage node configured to provide a bias voltage level (e.g., V CM ),

[0140] Based on a first reset signal (eg, RST), the first set of switches (eg, S INp 、S INn 、S OUT ) to couple the input node of the amplifier circuit to the bias voltage node (V CM ), and coupling it between the first output node and the second output node of the amplifier circuit,

[0141] Based on a second reset signal (eg, RSTD) having a first value, the second set of switches (eg, S F1A 、S F1C 、S F2A 、S F2C ) in order to selectively connect the first feedback branch (e.g., C F1 、C F2 、R F ) in the first (e.g. C F1) and the second (e.g. C F2 ) capacitor and the second feedback branch (e.g. R F 、C F1 、C F2 ) in the third (e.g. C F1 ) and the fourth (e.g. C F2 ) capacitor is coupled to the first (e.g. V INp ) and the second (eg V INn ) input node (e.g. V INn , V INp ),and

[0142] Based on the second reset signal (eg, RSTD) having the first value, the third set of switches (eg, S F1B 、S F1D 、S F2B 、S F2D ) in order to couple the one of the first capacitor and the second capacitor in the first feedback branch and the one of the third capacitor and the fourth capacitor in the second feedback branch to the first (eg, V OUTp ) and a second (e.g., V OUTn ) output node (V OUTn 、V OUTp ),

[0143] After a first time interval, switching the first reset signal from the first value (e.g., t2) to a second value;

[0144] In response to the first reset signal switching from the first value to the second value, the first reset signal is switched to the second value at a further time interval (eg, T DELAY ), maintaining the second reset signal at a first value within the first time interval, and the first reset signal has the first value during the first time interval.

[0145] like Figure 7C As shown in the example, after full discharge, the input node V IN1 、V IN2 Can be coupled to input square waveform V0, V0'.

[0146] It should also be understood that the various individual implementation options illustrated in the drawings accompanying this specification are not necessarily intended to be employed in the same combinations illustrated in the drawings. Thus, one or more embodiments may employ these (otherwise non-mandatory) options individually and / or in different combinations relative to the combinations illustrated in the drawings.

[0147] Without prejudice to the basic principle, the details and embodiments may vary, even significantly, with respect to what is described purely by way of example, without departing from the scope of protection.

[0148] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which such claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A circuit comprising: an amplifier having a first input node and a second input node, wherein the first input node and the second input node are configured to be coupled to opposite ends of at least one capacitor to detect a capacitance change signal indicating a change in capacitance value of the at least one capacitor, and wherein the amplifier has a first output node and a second output node. a bias voltage node configured to provide a bias voltage level, a first set of switches configured to couple the first input node and the second input node of the amplifier to the bias voltage node and to couple between the first output node and the second output node of the amplifier based on a first reset signal having a first value; a first feedback branch coupled between the first output node and the first input node of the amplifier, wherein the first feedback branch comprises a first RC network, and the first RC network comprises a first capacitor and a second capacitor; a second feedback branch coupled between the second output node and the second input node of the amplifier, wherein the second feedback branch comprises a second RC network, and the second RC network comprises a third capacitor and a fourth capacitor; The first feedback branch and the second feedback branch further include: a second set of switches between the first input node and the second input node of the amplifier and the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor; and A third set of switches is provided between the first input node and the second output node of the amplifier and the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor. in, The switches in the second set of switches are configured to selectively couple one of the first capacitor and the second capacitor in the first feedback branch and one of the third capacitor and the fourth capacitor in the second feedback branch to the first input node and the second input node of the amplifier based on a second reset signal having a first value, and The switches in the third group of switches are configured to selectively couple the one of the first capacitor and the second capacitor in the first feedback branch and the one of the third capacitor and the fourth capacitor in the second feedback branch to the first output node and the second output node of the amplifier based on a second reset signal having a first value, wherein the first reset signal is configured to have a first value during a first time interval and to switch from the first value to a second value after the first time interval, and wherein in response to the first reset signal switching from the first value to the second value, the second reset signal maintains the first value for an additional time interval exceeding the first time interval, during which the first reset signal has the first value.

2. The circuit according to claim 1, wherein: The circuit includes a power supply for the amplifier, the power supply being configured to be powered down based on a power down signal having a first value, The first time interval includes a first sub-interval and a second sub-interval, the first reset signal is configured to have a first value during the first time interval, and The power down signal has the first value during the first sub-interval and the second value during the second sub-interval, with the result that the power supply to the amplifier is powered down during the first sub-interval.

3. The circuit of claim 1 , wherein: The amplifier has a signal amplification bandwidth, and The further time interval exceeding the time interval during which the first reset signal has the first value has a duration that is a function of the signal amplification bandwidth of the amplifier. The circuit of claim 1 , wherein the amplifier is a fully differential operational transconductance amplifier (OTA). The circuit of claim 1 , wherein the second feedback branch is a copy of the first feedback branch.

6. The circuit of claim 1 , wherein: The first feedback branch comprises a parallel connection of the first capacitor and the second capacitor, the parallel connection being arranged in parallel with a resistor, The second set of switches includes: a first switch, inserted between the first input node of the amplifier and the first capacitor, a second switch inserted between the first input node of the amplifier and the second capacitor, and The third set of switches includes: a corresponding first switch, inserted between the first output node of the amplifier and the first capacitor, and A corresponding second switch is inserted between the first output node of the amplifier circuit and the second capacitor.

7. The circuit of claim 1 , wherein: The second feedback branch comprises a parallel connection of the third capacitor and the fourth capacitor, the parallel connection being arranged in parallel with a resistor, The second set of switches includes: a third switch, inserted between the second input node of the amplifier and the third capacitor, a fourth switch inserted between the second input node of the amplifier and the fourth capacitor, and The third set of switches includes: a corresponding third switch inserted between the second output node of the output node of the amplifier and the first capacitor in the second feedback branch, and A corresponding fourth switch is inserted between the second output node of the amplifier circuit and the second capacitor.

8. A sensor device comprising: at least one capacitor configured to convert a change in a physical quantity into a capacitance change signal, a reference capacitor coupled to the at least one capacitor, the reference capacitor having a capacitance value substantially equal to a capacitance value of the at least one capacitor when the capacitor is at rest, A circuit having an input node coupled at an end of the at least one capacitor and at an end of the reference capacitor, the circuit comprising: an amplifier having a first input node and a second input node, the first input node and the second input node being coupled to ends of at least one capacitor to detect a capacitance change signal indicating a change in capacitance value of the at least one capacitor, the amplifier having a first output node and a second output node, a bias voltage node configured to provide a bias voltage level, a first set of switches configured to couple the first input node and the second input node of the amplifier to the bias voltage node and to couple between the first output node and the second output node of the amplifier based on a first reset signal having a first value; a first feedback branch coupled between the first output node and the first input node of the amplifier, wherein the first feedback branch comprises a first RC network, and the first RC network comprises a first capacitor and a second capacitor; a second feedback branch coupled between the second output node and the second input node of the amplifier, wherein the second feedback branch comprises a second RC network, and the second RC network comprises a third capacitor and a fourth capacitor; The first feedback branch and the second feedback branch further include: a second set of switches between the first input node and the second input node of the amplifier and the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor; and A third set of switches is provided between the first output node and the second output node of the amplifier and the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor. in, The switches in the second set of switches are configured to selectively couple one of the first capacitor and the second capacitor in the first feedback branch and one of the third capacitor and the fourth capacitor in the second feedback branch to the first input node and the second input node of the amplifier based on a second reset signal having a first value, and The switches in the third group of switches are configured to selectively couple the one of the first capacitor and the second capacitor in the first feedback branch and the one of the third capacitor and the fourth capacitor in the second feedback branch to the first output node and the second output node of the amplifier based on a second reset signal having a first value; and a control circuit arrangement coupled to the circuit and configured to provide a first reset signal and a second reset signal to the circuit, wherein the first reset signal is configured to have a first value within a first time interval and to switch from the first value to a second value after the first time interval, and Wherein, in response to the first reset signal switching from the first value to the second value, the second reset signal maintains the first value for a further time interval exceeding the first time interval during which the first reset signal has the first value.

9. The sensor device according to claim 8, comprising a further set of switches, wherein the further set of switches is configured to: couple the input node of the at least one capacitor and the input node of the reference capacitor to the bias voltage node based on the second reset signal having a first value.

10. The sensor device according to claim 8, wherein: The circuit includes a power supply for the amplifier, the power supply being configured to be powered down based on a power down signal having a first value, The first time interval includes a first sub-interval and a second sub-interval, the first reset signal is configured to have the first value during the first time interval, and The power down signal has a first value during the first sub-interval and a second value during the second sub-interval, with the result that the power supply to the amplifier is powered down during the first sub-interval.

11. The sensor device according to claim 8, wherein: The amplifier has a signal amplification bandwidth, and The further time interval exceeding the time interval during which the first reset signal has the first value has a duration that is a function of the signal amplification bandwidth of the amplifier. 12 . The sensor device according to claim 8 , wherein the amplifier is a fully differential operational transconductance amplifier (OTA). 13 . The sensor device of claim 8 , wherein the second feedback branch is a copy of the first feedback branch.

14. The sensor device according to claim 8, wherein: The first feedback branch comprises a parallel connection of the first capacitor and the second capacitor, the parallel connection being arranged in parallel with a resistor, The second set of switches includes: a first switch, inserted between the first input node of the amplifier and the first capacitor, a second switch inserted between the first input node of the amplifier and the second capacitor, and The third set of switches includes: a corresponding first switch, inserted between the first output node of the amplifier and the first capacitor, and A corresponding second switch is inserted between the first output node of the amplifier circuit and the second capacitor.

15. The sensor device according to claim 8, wherein: The second feedback branch comprises a parallel connection of the third capacitor and the fourth capacitor, the parallel connection being arranged in parallel with a resistor, The second set of switches includes: a third switch, inserted between the second input node of the amplifier and the third capacitor, a fourth switch inserted between the second input node of the amplifier and the fourth capacitor, and The third set of switches includes: a corresponding third switch inserted between the second output node of the output node of the amplifier and the first capacitor in the second feedback branch, and A corresponding fourth switch is inserted between the second output node of the amplifier circuit and the second capacitor.

16. A method of operating the circuit of claim 1, the method comprising: providing a bias voltage node configured to provide a bias voltage level; driving the first set of switches based on a first reset signal to couple the input node of the amplifier circuit to the bias voltage node and between the first output node and the second output node of the amplifier circuit; driving switches in the second set of switches to selectively couple one of a first capacitor and a second capacitor in the first feedback branch and one of a third capacitor and a fourth capacitor in the second feedback branch to the first input node and the second input node of the amplifier based on a second reset signal having a first value; driving switches in the third set of switches to selectively couple the one of the first capacitor and the second capacitor in the first feedback branch and the one of the third capacitor and the fourth capacitor in the second feedback branch to the first output node and the second output node of the amplifier based on a second reset signal having a first value; After a first time interval, switching the first reset signal from the first value to a second value; and In response to the first reset signal switching from the first value to the second value, the second reset signal is maintained at the first value for an additional time interval exceeding the first time interval during which the first reset signal has the first value.

17. The method according to claim 16, further comprising: providing a power-off signal having the first value during a first subinterval of the first time interval; providing a power-off signal having the second value during a second subinterval of the first time interval; and The power supply of the amplifier is powered down during the first sub-interval based on the power-down signal.

18. The method of claim 16, wherein the further time interval has a duration that is a function of the signal amplification bandwidth of the amplifier. The method of claim 16 , wherein the amplifier is a fully differential operational transconductance amplifier (OTA).

20. The method of claim 16, wherein the second feedback branch is a copy of the first feedback branch.

Images