Digital-to-analog conversion apparatus and method with signal calibration mechanism

Abstract

The present disclosure relates to a digital-to-analog conversion device and method with signal calibration mechanism. A digital-to-analog conversion device with signal calibration mechanism. A first conversion circuit generates a first analog signal to an echo path according to an input digital signal. A second conversion circuit generates a second analog signal to the echo path according to the input digital signal and a pseudo noise digital signal. An echo transmission circuit processes the signals of the echo path to generate an echo signal. First and second calibration circuits generate first and second calibration signals. A calibration parameter operation circuit operates according to a difference between the echo signal and the first and second calibration signals and related path information to generate first and second offset values. The first and second calibration circuits make the first and second response coefficients converge according to the echo signal, and update first and second code word offset tables according to the first and second offset values.

Description

Technical Field

[0001] This invention relates to digital-to-analog conversion technology, and more particularly to a digital-to-analog conversion device and method with a signal calibration mechanism. Background Technology

[0002] A digital-to-analog converter (DTC) is a crucial component that converts signals from digital to analog form. DTCs can generate analog signals of varying magnitudes by multiplying different digital codes by corresponding conversion gain values.

[0003] However, when a digital-to-analog converter circuit contains multiple circuits for calibration and echo cancellation that need to be trained, the interaction between different circuits often makes the training process difficult. Summary of the Invention

[0004] In view of the problems of the prior art, one of the objectives of the present invention is to provide a digital-to-analog conversion device and method with a signal calibration mechanism to improve the prior art.

[0005] This invention includes a digital-to-analog converter with a signal calibration mechanism, comprising: a first conversion circuit, a second conversion circuit, an echo transmission circuit, a first calibration circuit, a second calibration circuit, and a calibration parameter calculation circuit. When activated, the first conversion circuit receives an input digital signal with an input codeword from a signal source, performs digital-to-analog conversion to generate a first analog signal for the echo path. When activated, the second conversion circuit receives the input digital signal from the signal source and a pseudo-noise digital signal from a pseudo-noise source, performs digital-to-analog conversion to generate a second analog signal for the echo path. The echo transmission circuit processes the echo path signal to generate an echo signal. The first calibration circuit maps the input digital signal according to a first codeword deviation table and processes it according to a set of first response coefficients, generating a first calibration signal corresponding to the first conversion circuit. The second calibration circuit maps the input digital signal and the pseudo-noise digital signal according to a second codeword deviation table and processes them according to a set of second response coefficients, generating a second calibration signal corresponding to the second conversion circuit. The calibration parameter calculation circuit generates a first offset and a second offset based on the difference between the echo signal and the first and second calibration signals, as well as the path information related to the first and second calibration circuits. The first and second calibration circuits first converge the first and second set of response coefficients based on the echo signal, and then update the first codeword deviation table and the second codeword deviation table based on the first and second offsets, respectively.

[0006] This invention further includes a digital-to-analog conversion method with a signal calibration mechanism, applied in a digital-to-analog conversion device, comprising: enabling a first conversion circuit to receive an input digital signal with an input codeword from a signal source when activated, performing digital-to-analog conversion to generate a first analog signal onto the echo path; enabling a second conversion circuit to receive an input digital signal from a signal source and a pseudo-noise digital signal from a pseudo-noise source when activated, performing digital-to-analog conversion to generate a second analog signal onto the echo path; enabling an echo transmission circuit to perform signal processing on the echo path to generate an echo signal; enabling a first calibration circuit to map the input digital signal according to a first codeword deviation table and process it according to a set of first response coefficients, corresponding to the first conversion... The circuit generates a first calibration signal; the second calibration circuit maps the input digital signal and the pseudo-noise digital signal according to the second codeword deviation table and processes them according to a set of second response coefficients, corresponding to the second conversion circuit generating a second calibration signal; the calibration parameter calculation circuit generates a first offset and a second offset according to the difference between the echo signal and the first and second calibration signals, and the path information related to the first and second calibration circuits; and the first and second calibration circuits first converge the set of first response coefficients and the set of second response coefficients according to the echo signal, and then update the first codeword deviation table and the second codeword deviation table according to the first offset and the second offset, respectively.

[0007] Regarding the features, implementation, and effects of this case, the preferred embodiments are described in detail below with reference to the drawings. Attached Figure Description

[0008] Figure 1 A block diagram showing a digital-to-analog converter with a signal calibration mechanism in one embodiment of the present invention is shown.

[0009] Figure 2 A block diagram showing a digital-to-analog converter with a signal calibration mechanism is shown in another embodiment of the present invention.

[0010] Figure 3 A flowchart of a digital-to-analog conversion method with a signal calibration mechanism is shown in one embodiment of the present invention.

[0011] Figure 4 In one embodiment of the present invention, the application Figure 1 A schematic diagram of the training process performed by the digital-to-analog converter; and

[0012] Figure 5 In one embodiment of the present invention, the application Figure 2 A schematic diagram of the training process performed by the digital-to-analog converter. Detailed Implementation

[0013] One of the objectives of this invention is to provide a digital-to-analog converter with a signal calibration mechanism, which trains the calibration circuit in stages according to the input of different signal contents, thereby avoiding the impact of interaction between different calibration circuits on the training.

[0014] Please refer to Figure 1 . Figure 1 This diagram shows a block diagram of a digital-to-analog converter 100 with a signal calibration mechanism according to one embodiment of the present invention. The digital-to-analog converter 100 includes: a first conversion circuit 110A, a second conversion circuit 110B, an echo transmission circuit 120, a first calibration circuit 130, a second calibration circuit 140, a first error calculation circuit 150A, a second error calculation circuit 150B, an inversion error calculation circuit 160, and a calibration parameter calculation circuit 170.

[0015] When enabled, the first conversion circuit 110A receives an input digital signal IS with an input codeword from a signal source SS, such as a transmitter (TX) in a communication system, and performs a digital-to-analog conversion to generate a first analog signal OAS1. In one embodiment, the first conversion circuit 110A is an output digital-to-analog conversion circuit, and the generated first analog signal OAS1 is an output analog signal for output to an external circuit, and is also output to the echo path EP.

[0016] When the second conversion circuit 110B is enabled, it receives the input digital signal IS from the signal source SS and the pseudo-noise digital signal IN from the pseudo-noise source NS, performs digital-to-analog conversion to generate the second analog signal OAS2, and outputs it to the echo path EP.

[0017] In one embodiment, the pseudo-noise digital signal IN generated by the pseudo-noise source NS is used to simulate random 0 and 1 signals of noise. In one embodiment, the second conversion circuit 110B is an echo-cancelling digital-to-analog conversion circuit, and the generated second analog signal OAS2 is an echo-cancelling analog signal that performs echo cancellation on the first analog signal OAS1 on the echo path EP.

[0018] In one embodiment, the second conversion circuit 110B includes a non-noise conversion circuit 115A and a noise conversion circuit 115B, which respectively receive the input digital signal IS and the pseudo-noise digital signal IN and perform digital-to-analog conversion to generate a second analog signal OAS2.

[0019] In one embodiment, the non-noise conversion circuit 115A and the noise conversion circuit 115B in the first conversion circuit 110A and the second conversion circuit 110B may each include multiple current sources (not shown in the figure). The input codeword of the input digital signal IS and the pseudo-noise digital signal IN can respectively control the operation of the corresponding current sources to generate the first and second analog signals OAS1 and OAS2.

[0020] The echo transmission circuit 120 performs signal processing on the echo path EP, such as echo response processing and analog-to-digital conversion, as well as selective low-pass filtering or other digital signal processing, to generate the echo signal ES.

[0021] In one embodiment, the first calibration circuit 130 includes a first mapping circuit 135A and a first response circuit 135B.

[0022] The first mapping circuit 135A maps the input codeword of the input digital signal IS to the first codeword offset table TB1 to generate the first mapping signal DS1. The first codeword offset table TB1 contains a one-to-one correspondence between multiple codewords and multiple codeword offset values, and the input codeword is one of these codewords. In one embodiment, in the initial state, the offset values ​​corresponding to all codewords are preset to 0.

[0023] The first response circuit 135B processes the first mapping signal DS1 according to the first response coefficient CC1 to generate the first calibration signal ECS1.

[0024] In one embodiment, the second calibration circuit 140 includes a second mapping circuit 145A and a second response circuit 145B.

[0025] The second mapping circuit 145A generates a second mapping signal DS2 by mapping the input codeword of the input digital signal IS to the second codeword offset table TB2. The second codeword offset table TB2 contains a one-to-one correspondence between multiple codewords and multiple codeword offset values, and the input codeword is one of these codewords. In one embodiment, in the initial state, the offset values ​​corresponding to all codewords are preset to 0.

[0026] In one embodiment, the digital-to-analog converter 100 further includes a pseudo-noise feed circuit 155 that receives a second mapped signal DS2 and a pseudo-noise digital signal IN to generate a superimposed digital signal SD. A second response circuit 145B processes the superimposed digital signal SD according to a second response coefficient CC2 to generate a second calibration signal ECS2.

[0027] The calibration parameter calculation circuit 170 generates a first offset DA1 and a second offset DA2 based on the difference between the echo signal ES and the first calibration signal ECS1 and the second calibration signal ECS2, and the path information related to the first calibration circuit 130 and the second calibration circuit 140.

[0028] In one embodiment, the first and second error calculation circuits 150A and 150B perform error calculations based on the first and second calibration signals ECS1 and ECS2, respectively, and the echo signal ES. The first error calculation circuit 150A ultimately generates the error signal DIS. More specifically, the second error calculation circuit 150B and the first error calculation circuit 150A sequentially calculate the difference between the echo signal ES and the first and second calibration signals ECS1 and ECS2 to generate the error signal DIS.

[0029] In one embodiment, the digital-to-analog converter 100 further includes an inversion error calculation circuit 160. The inversion error calculation circuit 160 receives a first response coefficient CC1, performs a one-dimensional inversion, multiplies it by the value of the error signal DIS, and then accumulates the results to generate a first inversion error value FD1. Furthermore, the inversion error calculation circuit 160 receives a second response coefficient CC2, performs a one-dimensional inversion, multiplies it by the value of the error signal DIS, and then accumulates the results to generate a second inversion error value FD2.

[0030] The calibration parameter calculation circuit 170 uses the path delay DL1 between the first response circuit 135A and the inversion error calculation circuit 160 to make the first inversion error value FD1 the first offset DA1 corresponding to the input codeword. Furthermore, the calibration parameter calculation circuit 170 uses the path delay DL2 between the second response circuit 135B and the inversion error calculation circuit 160 to make the second inversion error value FD2 the second offset DA2 corresponding to the input codeword.

[0031] It should be noted that the above-described method of generating offsets is merely an example. In other embodiments, the calibration parameter calculation circuit 170 may also generate the first offset DA1 and the second offset DA2 in other ways.

[0032] The digital-to-analog converter 100 needs to train the first codeword deviation table TB1, the first response coefficient CC1, the second codeword deviation table TB2, and the second response coefficient CC2 in the first calibration circuit 130 and the second calibration circuit 140 to achieve the purpose of calibrating the digital-to-analog circuit and echo cancellation. More specifically, the first calibration circuit 130 and the second calibration circuit 140 will first converge the first response coefficient CC1 and the second response coefficient CC2 according to the error signal DIS generated by the echo signal ES, and then update the first codeword deviation table TB1 and the second codeword deviation table TB2 according to the first offset DA1 and the second offset DA2, respectively.

[0033] To avoid interference between the training targets, the digital-to-analog converter 100 is trained in different stages.

[0034] During the first training phase, the first conversion circuit 110A is disabled and the second conversion circuit 110B is enabled. At this time, the echo transmission circuit 120 will only receive the second analog signal OAS2 on the echo path EP and generate the echo signal ES accordingly.

[0035] The second mapping circuit 145A maps the input digital signal IS according to the preset second codeword deviation table TB2 to generate the second mapping signal DS2. The second response circuit 145B processes the superimposed digital signal SD generated by superimposing the second mapping signal DS2 and the pseudo-noise digital signal IN according to the second response coefficient CC2 to generate the second calibration signal ECS2.

[0036] During the second training phase, the first conversion circuit 110A remains disabled while the second conversion circuit 110B remains enabled. The second mapping circuit 145A updates the second codeword offset table TB2 according to the second offset DA2.

[0037] In one embodiment, the second conversion circuit 110B includes a thermometer-controlled current source. The deviation value of each current source will generate multiple permutations and combinations corresponding to different input codewords in response to the control of the input digital signal IS, thereby creating a mapping relationship between the deviation value of the current source and the offset of the input codeword.

[0038] The calibration parameter calculation circuit 170 can perform statistical calculations on the second offset DA2 corresponding to different input codewords, grouping them according to the operating state of each current source, and generating average values ​​for each group. Specifically, each pair of adjacent groups represents the operating state of one of the thermometer-controlled current sources as a first current output state and a second current output state, respectively. By calculating the difference between the average values ​​of each group, the calibration parameter calculation circuit 170 can obtain the deviation values ​​between each current source, and then map these deviation values ​​back to the offset of the input codeword to update the second codeword deviation table TB2.

[0039] In one embodiment, the calibration parameter calculation circuit 170 may not set an anchor point when performing the above-mentioned statistical calculation to distinguish groups.

[0040] In the third training phase, both the first conversion circuit 110A and the second conversion circuit 110B are activated. At this time, the echo transmission circuit 120 will receive the signal generated by the second analog signal OAS2 after echo cancellation of the first analog signal OAS1 on the echo path EP, so as to generate the echo signal ES.

[0041] The first mapping circuit 135A maps the input digital signal IS according to the preset first codeword deviation table TB1 to generate the first mapping signal DS1. The first response circuit 135B processes the first mapping signal DS1 according to the first response coefficient CC1 to generate the first calibration signal ECS1.

[0042] Furthermore, the first response circuit 135B causes the first response coefficient CC1 to converge based on the difference between the echo signal ES and the first calibration signal ECS1 and the second calibration signal ECS2, i.e. the error signal DIS.

[0043] During the fourth training phase, both the first conversion circuit 110A and the second conversion circuit 110B remain operational. The first mapping circuit 135A updates the first codeword deviation table TB1 according to the first offset DA1.

[0044] The method by which the first mapping circuit 135A updates the first codeword offset table TB1 is similar to the method by which the second mapping circuit 145A updates the second codeword offset table TB2, and will not be repeated here. However, when the calibration parameter calculation circuit 170 performs statistical calculations to distinguish groups of the second offset DA2, it can set the average value of two groups to 0 as an anchor point before calculation to avoid system interaction.

[0045] In accordance with the above method, the digital-to-analog converter 100 can complete the training of the first calibration circuit 130 and the second calibration circuit 140 without inter-circuit interaction.

[0046] Please refer to Figure 2 . Figure 2 A block diagram showing another embodiment of the present invention is provided, illustrating a digital-to-analog converter 200 with a signal calibration mechanism.

[0047] Digital-to-analog converter 200 and Figure 1 The digital-to-analog converter 100 in the present invention contains similar components, therefore, the same components will not be described in detail here.

[0048] In this embodiment, the digital-to-analog converter 200 also includes a pseudo-noise feed circuit 155. However, in this embodiment, the pseudo-noise feed circuit 155 receives a second mapping signal DS2 from the second mapping circuit 145A and a pseudo-noise digital signal IN from the pseudo-noise source NS to generate a superimposed digital signal SD, which is directly fed into the second mapping circuit 145A of the second conversion circuit 110B and the second calibration circuit 140, respectively.

[0049] Therefore, the second conversion circuit 110B only needs to include the following: Figure 1The noise-free conversion circuit 115A shown (not illustrated) directly receives the superimposed digital signal SD to generate the second analog signal OAS2, without needing to include the noise conversion circuit 115B.

[0050] Furthermore, the second mapping circuit 145A maps the superimposed digital signal SD from the second codeword deviation table TB2 to generate the second mapping signal DS2, and the second response circuit 145B processes the second mapping signal DS2 according to the second response coefficient CC2 to generate the second calibration signal ECS2.

[0051] Under this architecture, the digital-to-analog converter 200 can be trained in only two stages.

[0052] During the first training phase, both the first conversion circuit 110A and the second conversion circuit 110B are activated. At this time, the echo transmission circuit 120 will receive the signal generated by the second analog signal OAS2 after echo cancellation of the first analog signal OAS1 on the echo path EP, so as to generate the echo signal ES.

[0053] The second mapping circuit 145A maps the superimposed digital signal SD according to the preset second codeword deviation table TB2 to generate a second mapping signal DS2. The second response circuit 145B processes the second mapping signal DS2 according to the second response coefficient CC2 to generate a second calibration signal ECS2. The second response circuit 145B causes the second response coefficient CC2 to converge according to the error signal DIS.

[0054] Simultaneously, the first mapping circuit 135A maps the input digital signal IS according to the preset first codeword deviation table TB1 to generate a first mapping signal DS1. The first response circuit 135B processes the first mapping signal DS1 according to the first response coefficient CC1 to generate a first calibration signal ECS1. The first response circuit 135B causes the first response coefficient CC1 to converge according to the error signal DIS.

[0055] During the second training phase, both the first conversion circuit 110A and the second conversion circuit 110B remain operational. At this time, the echo transmission circuit 120 receives the signal generated by the second analog signal OAS2 after echo cancellation of the first analog signal OAS1 on the echo path EP, thereby generating the echo signal ES.

[0056] The second mapping circuit 145A updates the second codeword offset table TB2 according to the second offset DA2, and the first mapping circuit 135A updates the first codeword offset table TB1 according to the first offset DA1.

[0057] In this embodiment, when the calibration parameter calculation circuit 170 performs statistical calculations to distinguish groups for the second offset DA2 and the first offset DA1, it can set the average value of two of the groups to 0 as an anchor point before calculation, thus avoiding system interaction.

[0058] In accordance with the above method, the digital-to-analog converter 200 can complete the training of the first calibration circuit 130 and the second calibration circuit 140 without inter-circuit interaction.

[0059] It should be noted that the training of the first calibration circuit 130 and the second calibration circuit 140 by the aforementioned digital-to-analog converters 100 and 200 can be performed during actual circuit operation.

[0060] In one embodiment, both the digital-to-analog converter 100 and the digital-to-analog converter 200 may further include a first auxiliary conversion circuit (not shown in the figure), configured to generate a corresponding calibration signal based on the first codeword deviation table TB1 obtained from the training results after the training status has stabilized, to calibrate the first analog signal OAS1 generated by the first conversion circuit 110A, to offset the error of the current source, and then use it as the actual signal output to the external circuit.

[0061] Furthermore, both the digital-to-analog converter 100 and the digital-to-analog converter 200 may further include a second auxiliary conversion circuit (not shown in the figure), configured to generate a corresponding calibration signal based on the second codeword deviation table TB2 obtained from the training results after the training status has stabilized, to calibrate the second analog signal OAS2 generated by the second conversion circuit 110B, to offset the error of the current source, and then use it as the actual signal for echo cancellation.

[0062] Therefore, the digital-to-analog converter 100 can train the first calibration circuit 130 and the second calibration circuit 140 in stages by feeding the first conversion circuit 110A and the first calibration circuit 130 with the input digital signal IS, and feeding the second conversion circuit 110B and the second calibration circuit 140 with the input digital signal IS and the pseudo-noise digital signal IN, thereby avoiding interaction between the calibration circuits.

[0063] Please refer to Figure 3 . Figure 3 This invention illustrates a flowchart of a digital-to-analog conversion method 300 with a signal calibration mechanism, according to one embodiment of the present invention.

[0064] In addition to the aforementioned apparatus, the present invention also discloses a digital-to-analog conversion method 300, applicable to, for example, but not limited to, [various applications]. Figure 1 Digital-to-analog converter 100 or Figure 2In the digital-to-analog conversion device 200. One embodiment of the digital-to-analog conversion method 300 is, for example... Figure 3 As shown, it includes the following steps.

[0065] In step S310: When the first conversion circuit 110A is enabled, it receives an input digital signal IS with an input codeword from the signal source SS, performs digital-to-analog conversion to generate a first analog signal OAS1 and sends it to the echo path EP.

[0066] In step S320: When the second conversion circuit 110B is enabled, it receives the input digital signal IS from the signal source SS and the pseudo noise digital signal IN from the pseudo noise source NS, performs digital-to-analog conversion to generate the second analog signal OAS2 and sends it to the echo path EP.

[0067] In step S330: the echo transmission circuit 120 performs signal processing on the echo path EP to generate an echo signal ES.

[0068] In step S340: the first calibration circuit 130 maps the input digital signal IS according to the first codeword deviation table TB1 and processes it according to a set of first response coefficients CC1, and the first conversion circuit 110A generates the first calibration signal ECS1.

[0069] In step S350: the second calibration circuit 140 maps the input digital signal IS and the pseudo-noise digital signal IN according to the second codeword deviation table TB2 and processes them according to a set of second response coefficients CC2, and the second conversion circuit 110B generates the second calibration signal ECS2.

[0070] In step S360: the calibration parameter calculation circuit 170 generates a first offset DA1 and a second offset DA2 based on the difference between the echo signal ES and the first calibration signal ECS1 and the second calibration signal ECS2, and the path information related to the first calibration circuit 130 and the second calibration circuit 140.

[0071] In step S370: the first calibration circuit 130 and the second calibration circuit 140 first converge the first response coefficient CC1 and the second response coefficient CC2 according to the echo signal ES, and then update the first codeword deviation table TB1 and the second codeword deviation table TB2 according to the first offset DA1 and the second offset DA2, respectively.

[0072] Please refer to Figure 4 . Figure 4 In one embodiment of the present invention, the application Figure 1 A schematic diagram of the training process 400 performed by the digital-to-analog converter 100.

[0073] In step S410, during the first training phase, the first conversion circuit 110A is disabled and the second conversion circuit 110B is enabled. The second mapping circuit 145A maps the input digital signal IS according to the preset second codeword deviation table TB2 to generate the second mapping signal DS2. The second response circuit 145B processes the superimposed digital signal SD according to the second response coefficient CC2 to generate the second calibration signal ECS2. The second response circuit 145B also causes the second response coefficient CC2 to converge according to the difference between the echo signal ES and the second calibration signal ECS2.

[0074] In step S420, during the second training phase, the first conversion circuit 110A is disabled and the second conversion circuit 110B is enabled, and the second mapping circuit 145A updates the second codeword deviation table TB2 according to the second offset DA2.

[0075] In step S430, during the third training phase, both the first conversion circuit 110A and the second conversion circuit 110B are enabled. The first mapping circuit 135A maps the input digital signal IS according to the preset first codeword deviation table TB1 to generate a first mapping signal DS1. The first response circuit 135B processes the first mapping signal DS1 according to the first response coefficient CC1 to generate a first calibration signal ECS1. The first response circuit 135B also causes the first response coefficient CC1 to converge according to the difference between the echo signal ES and the first calibration signal ECS1 and the second calibration signal ECS2.

[0076] In step S440, during the fourth training phase, both the first conversion circuit 110A and the second conversion circuit 110B are activated, and the first mapping circuit 135A updates the first codeword deviation table TB1 according to the first offset DA1.

[0077] Please refer to Figure 5 . Figure 5 In one embodiment of the present invention, the application Figure 2 A schematic diagram of the training process 500 performed by the digital-to-analog converter 200.

[0078] In step S510, during the first training phase, both the first conversion circuit 110A and the second conversion circuit 110B are enabled. The second mapping circuit 145A maps the superimposed digital signal SD according to the preset second codeword deviation table TB2 to generate a second mapping signal DS2. The second response circuit 145B processes the second mapping signal DS2 according to the second response coefficient CC2 to generate a second calibration signal ECS2. The second response circuit 145B also causes the second response coefficient CC2 to converge according to the difference between the echo signal ES and the second calibration signal ECS2.

[0079] In step S520, during the first training phase, the first mapping circuit 135A maps the input digital signal IS according to the preset first codeword deviation table TB1 to generate a first mapping signal DS1. The first response circuit 135B processes the first mapping signal DS1 according to the first response coefficient CC1 to generate a first calibration signal ECS1. The first response circuit 135B also causes the first response coefficient CC1 to converge according to the difference between the echo signal ES and the first calibration signal ECS1 and the second calibration signal ECS2.

[0080] In step S530, during the second training phase, both the first conversion circuit 110A and the second conversion circuit 110B are enabled. The second mapping circuit 145A updates the second codeword deviation table TB2 according to the second offset DA2, and the first mapping circuit 135A updates the first codeword deviation table according to the first offset DA1.

[0081] It should be noted that the above-described embodiments are merely examples. In other embodiments, those skilled in the art can make modifications without departing from the spirit of the invention. For example, the first conversion circuit and the second conversion circuit described above are respectively illustrated as an output conversion circuit and an echo cancellation conversion circuit. In one embodiment, the first conversion circuit may also be an echo cancellation conversion circuit, and the second conversion circuit may be an output conversion circuit.

[0082] In summary, the digital-to-analog converter and method with signal calibration mechanism of the present invention can train the calibration circuit in stages according to the input of different signal contents, so as to avoid the interaction between calibration circuits from affecting the training.

[0083] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make changes to the technical features of this case based on the express or implied content of this case. All such changes may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection of this case shall be determined by the scope of the patent application in this specification.

[0084] Symbol Explanation

[0085] 100: Digital-to-analog converter

[0086] 110A: First conversion circuit

[0087] 110B: Second conversion circuit

[0088] 115A: Noise-free conversion circuit

[0089] 115B: Noise Conversion Circuit

[0090] 120: Echo transmission circuit

[0091] 130: First calibration circuit

[0092] 135A: First mapping circuit

[0093] 135B: First Response Circuit

[0094] 140: Second calibration circuit

[0095] 145A: Second mapping circuit

[0096] 145B: Second Response Circuit

[0097] 150A: First Error Calculation Circuit

[0098] 150B: Second Error Calculation Circuit

[0099] 155: Pseudo-noise feed circuit

[0100] 160: Reversal Error Calculation Circuit

[0101] 170: Calibration parameter calculation circuit

[0102] 300: Digital-to-Analog Conversion Method

[0103] S310~S370: Steps

[0104] 400, 500: Training Process

[0105] S410~S440, S510~S530: Steps

[0106] CC1: First Response Coefficient

[0107] CC2: Second Response Coefficient

[0108] DA1: First offset

[0109] DA2: Second offset

[0110] DL1, DL2: Path Delay

[0111] DIS: Error Signal

[0112] DS1: First mapped signal

[0113] DS2: Second Mapped Signal

[0114] ECS1: First calibration signal

[0115] ECS2: Second calibration signal

[0116] EP: Echo Path

[0117] ES: Echo Signal

[0118] FD1: First Reversal Error Value

[0119] FD2: Second reversal error value

[0120] IN: Pseudo-noise digital signal

[0121] IS: Input digital signal

[0122] NS: Pseudo-noise source

[0123] OAS1: First analog signal

[0124] OAS2: Second analog signal

[0125] SD: Superimposed digital signal

[0126] TB1: First Codeword Deviation Table

[0127] TB2: Second Codeword Deviation Table

Claims

1. A digital-to-analog converter with a signal calibration mechanism, comprising: When enabled, the first conversion circuit receives an input digital signal with an input codeword from a signal source, performs digital-to-analog conversion to generate a first analog signal and sends it to the echo path. When enabled, the second conversion circuit receives the input digital signal from the signal source and the pseudo-noise digital signal from the pseudo-noise source, performs digital-to-analog conversion to generate a second analog signal to the echo path. The echo transmission circuit processes the echo path to generate an echo signal. The first calibration circuit maps the input digital signal according to a first codeword deviation table and processes it according to a set of first response coefficients to generate a first calibration signal corresponding to the first conversion circuit. The second calibration circuit maps the input digital signal and the pseudo-noise digital signal according to the second codeword deviation table and processes them according to a set of second response coefficients to generate a second calibration signal corresponding to the second conversion circuit. as well as The calibration parameter calculation circuit generates a first offset and a second offset based on the difference between the echo signal and the first calibration signal and the second calibration signal, as well as the path information related to the first calibration circuit and the second calibration circuit. The first calibration circuit and the second calibration circuit first converge the first set of response coefficients and the second set of response coefficients according to the echo signal, and then update the first codeword deviation table and the second codeword deviation table according to the first offset and the second offset, respectively.

2. The digital-to-analog conversion device as claimed in claim 1, wherein the first conversion circuit is an output conversion circuit, the first analog signal is an output analog signal, and the second conversion circuit is an echo cancellation conversion circuit, the second analog signal is an echo cancellation analog signal, and the echo cancellation analog signal is used to cancel the echo of the input digital signal on the echo path.

3. The digital-to-analog conversion apparatus of claim 1, wherein the first calibration circuit includes a first mapping circuit configured to generate a first mapping signal by mapping according to the first codeword deviation table and a first response circuit configured to generate the first calibration signal by processing according to the set of first response coefficients, and the second calibration circuit includes a second mapping circuit configured to generate a second mapping signal by mapping according to the second codeword deviation table and a second response circuit configured to generate the second calibration signal by processing according to the set of second response coefficients.

4. The digital-to-analog conversion apparatus of claim 3 further includes a pseudo-noise feed circuit configured to receive the second mapping signal from the second mapping circuit and the pseudo-noise digital signal from the pseudo-noise source to generate a superimposed digital signal, thereby causing the second response circuit to receive the superimposed digital signal, the second conversion circuit further including a non-noise conversion circuit and a noise conversion circuit, the non-noise conversion circuit receiving the input digital signal to perform digital-to-analog conversion and the noise conversion circuit receiving the pseudo-noise digital signal to perform digital-to-analog conversion; In the first training phase, the first conversion circuit is disabled and the second conversion circuit is enabled. The second mapping circuit maps the input digital signal according to the preset second codeword deviation table to generate the second mapping signal. The second response circuit processes the superimposed digital signal according to the set of second response coefficients to generate the second calibration signal. The second response circuit also causes the set of second response coefficients to converge according to the difference between the echo signal and the second calibration signal. During the second training phase, the first conversion circuit is disabled and the second conversion circuit is enabled, and the second mapping circuit updates the second codeword offset table according to the second offset. In the third training phase, both the first conversion circuit and the second conversion circuit are activated. The first mapping circuit maps the input digital signal according to the preset first codeword deviation table to generate the first mapping signal. The first response circuit processes the first mapping signal according to the set of first response coefficients to generate the first calibration signal. The first response circuit also causes the set of first response coefficients to converge according to the difference between the echo signal and the first and second calibration signals. In the fourth training phase, both the first conversion circuit and the second conversion circuit are enabled, and the first mapping circuit updates the first codeword deviation table according to the first offset.

5. The digital-to-analog conversion apparatus of claim 3 further includes a pseudo-noise feed circuit configured to receive the input digital signal from the signal source and the pseudo-noise digital signal from the pseudo-noise source to generate a superimposed digital signal, thereby enabling the second conversion circuit to receive the superimposed digital signal for digital-to-analog conversion. In the first training phase, both the first conversion circuit and the second conversion circuit are activated. The second mapping circuit maps the superimposed digital signal according to the preset second codeword deviation table to generate the second mapping signal. The second response circuit processes the second mapping signal according to the set of second response coefficients to generate the second calibration signal. The second response circuit also causes the set of second response coefficients to converge according to the difference between the echo signal and the second calibration signal. In the first training phase, the first mapping circuit maps the input digital signal according to the preset first codeword deviation table to generate the first mapping signal, the first response circuit processes the first mapping signal according to the first set of first response coefficients to generate the first calibration signal, and the first response circuit makes the first set of first response coefficients converge according to the difference between the echo signal and the first and second calibration signals. In the second training phase, both the first conversion circuit and the second conversion circuit are enabled. The second mapping circuit updates the second codeword deviation table according to the second offset, and the first mapping circuit updates the first codeword deviation table according to the first offset.

6. A digital-to-analog conversion method with a signal calibration mechanism, applied in a digital-to-analog conversion device, comprising: When the first conversion circuit is enabled, it receives an input digital signal with an input codeword from the signal source, performs digital-to-analog conversion to generate a first analog signal and sends it to the echo path. When the second conversion circuit is enabled, it receives the input digital signal from the signal source and the pseudo-noise digital signal from the pseudo-noise source, performs digital-to-analog conversion, and generates a second analog signal to the echo path. The echo transmission circuit processes the echo path to generate an echo signal. The first calibration circuit maps the input digital signal according to the first codeword deviation table and processes it according to a set of first response coefficients, thereby generating a first calibration signal corresponding to the first conversion circuit. The second calibration circuit maps the input digital signal and the pseudo-noise digital signal according to the second codeword deviation table and processes them according to a set of second response coefficients, thereby generating a second calibration signal for the second conversion circuit. The calibration parameter calculation circuit generates a first offset and a second offset based on the difference between the echo signal and the first calibration signal and the second calibration signal, as well as the path information related to the first calibration circuit and the second calibration circuit. as well as The first calibration circuit and the second calibration circuit first converge the first set of response coefficients and the second set of response coefficients according to the echo signal, and then update the first codeword deviation table and the second codeword deviation table according to the first offset and the second offset, respectively.

7. The digital-to-analog conversion method as described in claim 6, wherein the first conversion circuit is an output conversion circuit, the first analog signal is an output analog signal, and the second conversion circuit is an echo cancellation conversion circuit, the second analog signal is an echo cancellation analog signal, and the echo cancellation analog signal is used to cancel the echo of the input digital signal on the echo path.

8. The digital-to-analog conversion method of claim 6, wherein the first calibration circuit includes a first mapping circuit configured to generate a first mapping signal by mapping according to the first codeword deviation table and a first response circuit to generate the first calibration signal by processing according to the set of first response coefficients, and the second calibration circuit includes a second mapping circuit configured to generate a second mapping signal by mapping according to the second codeword deviation table and a second response circuit to generate the second calibration signal by processing according to the set of second response coefficients.

9. The digital-to-analog conversion method of claim 8, wherein the second response circuit directly receives the pseudo-noise digital signal from the pseudo-noise source, the second conversion circuit further includes a non-noise conversion circuit and a noise conversion circuit, the non-noise conversion circuit receiving the input digital signal to perform digital-to-analog conversion and the noise conversion circuit receiving the pseudo-noise digital signal to perform digital-to-analog conversion, the digital-to-analog conversion method further comprising: In the first training phase, the first conversion circuit is disabled and the second conversion circuit is enabled. The second mapping circuit maps the input digital signal according to the preset second codeword deviation table to generate the second mapping signal. The second response circuit processes the second mapping signal and the pseudo-noise digital signal according to the set of second response coefficients to generate the second calibration signal. The second response circuit also causes the set of second response coefficients to converge according to the difference between the echo signal and the second calibration signal. In the second training phase, the first conversion circuit is disabled and the second conversion circuit is enabled, and the second mapping circuit updates the second codeword offset table according to the second offset. In the third training phase, both the first conversion circuit and the second conversion circuit are enabled. The first mapping circuit maps the input digital signal according to the preset first codeword deviation table to generate the first mapping signal. The first response circuit processes the first mapping signal according to the set of first response coefficients to generate the first calibration signal. The first response circuit also makes the set of first response coefficients converge according to the difference between the echo signal and the first and second calibration signals. as well as In the fourth training phase, both the first conversion circuit and the second conversion circuit are enabled, and the first mapping circuit updates the first codeword deviation table according to the first offset.

10. The digital-to-analog conversion method of claim 8, further comprising a pseudo-noise feeding circuit configured to receive the input digital signal from the signal source and the pseudo-noise digital signal from the pseudo-noise source to generate a superimposed digital signal, thereby enabling the second conversion circuit to receive the superimposed digital signal for digital-to-analog conversion, the digital-to-analog conversion method further comprising: In the first training phase, both the first conversion circuit and the second conversion circuit are enabled. The second mapping circuit maps the superimposed digital signal according to the preset second codeword deviation table to generate the second mapping signal. The second response circuit processes the second mapping signal according to the set of second response coefficients to generate the second calibration signal. The second response circuit also makes the set of second response coefficients converge according to the difference between the echo signal and the second calibration signal. In the first training phase, the first mapping circuit maps the input digital signal according to the preset first codeword deviation table to generate the first mapping signal, the first response circuit processes the first mapping signal according to the first set of first response coefficients to generate the first calibration signal, and the first response circuit makes the first set of first response coefficients converge according to the difference between the echo signal and the first and second calibration signals. as well as In the second training phase, both the first conversion circuit and the second conversion circuit are enabled, the second mapping circuit updates the second codeword offset table according to the second offset, and the first mapping circuit updates the first codeword offset table according to the first offset.

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