Turbo decoding circuit and decoding method

Abstract

The present invention discloses a Turbo decoding circuit and decoding method. The input of a first decoder includes a detection value s(k), a detection value p(k) and a priori information #imgabs0# of an information bit sequence, and the output a posteriori information #imgabs1# and the posteriori information #imgabs2# are input to a second decoder after passing through a first interleaver; the detection value s(k) is input to a second decoder after passing through a second interleaver; the second interleaver receives the detection value p'(k) of a second check sequence, performs decoding calculation, and outputs a posteriori information #imgabs3# of each bit of the information sequence. The posteriori information #imgabs4# is input to the second decoder after passing through a deinterleaver as the next iterative process; the priori information #imgabs5# of the first decoder is converted into a logarithmic form by the present invention, and the multiplication operation is converted into an addition operation, thereby avoiding complex exponential operations, greatly simplifying the operation process, reducing decoding delay, and can be widely used in the field of integrated circuits.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a Turbo decoding circuit and a decoding method. Background Art

[0002] In NB-IoT digital baseband processing, turbo codes, a near-Shannon limit error correction scheme commonly used for wireless data transmission, have attracted considerable attention. NB-IoT applications place extremely stringent power consumption requirements. The component decoder is crucial in the design process. Turbo codes have different structures in different standards, and two algorithms are generally used to implement turbo codes: the soft-output Viterbi decoding algorithm (SOVA), a modified Viterbi decoding algorithm; and the maximum a posteriori probability decoding algorithm (MAP) and its improved versions.

[0003] The SOVA algorithm has the advantages of low decoding complexity and easy implementation, but its decoding performance is the worst and lacks stability. The MAP algorithm has better decoding performance than the SOVA algorithm, but its disadvantages are high computational complexity and large storage space requirements, making it difficult to implement in practice. Summary of the Invention

[0004] In order to at least solve one of the technical problems existing in the prior art to a certain extent, an object of the present invention is to provide a Turbo decoding circuit and decoding method.

[0005] The technical solution adopted in the present invention is:

[0006] A turbo decoding circuit includes a first decoder, a second decoder, a first interleaver, a second interleaver, and a deinterleaver;

[0007] The decoding process of the turbo decoding circuit is an iterative process, the input is the prior information of the system information bit, and after decoding, the output is the a posteriori information of the system information bit;

[0008] One of the iterations is as follows:

[0009] The input information of the first decoder includes the detection value s(k) of the information sequence, the detection value p(k) of the first check sequence, and the prior information of the information bit sequence The first decoder outputs the posterior information of each bit of the information sequence Posterior information After passing through the first interleaver, the information sequence is input to the second decoder; the detection value s(k) of the information sequence is input to the second decoder after passing through the second interleaver;

[0010] The second interleaver receives the detection value p'(k) of the second check sequence, performs decoding calculation, and outputs the posterior information of each bit of the information sequence Posterior information After the deinterleaver, it is used as the prior information of the first decoder in the next iteration.

[0011] The input and output calculation process of the decoder is converted into logarithmic form, and the multiplication operation is converted into addition operation to avoid complex exponential operations.

[0012] Furthermore, the first decoder and the second decoder have the same structure, both being soft input and output decoders;

[0013] Information is continuously exchanged and iterated between the two decoders to achieve the required Turbo code decoding performance.

[0014] Furthermore, the forward recursion, backward recursion and branch metrics are logarithmized and then calculated.

[0015] Furthermore, the decoder includes a branch metric calculation module, a forward recursion module, a backward recursion module, a likelihood information calculation module and an external information calculation module;

[0016] The input information of the branch metric calculation module is the detection value s(k), the detection value p(k), the prior information Output four different values of branch metric M k (e), respectively M k (0,0),M k (0,1),M k (1,0),M k (1,1);

[0017] The forward recursion module and the backward recursion module are based on the four branch metrics M k (e) performing calculations to obtain the recursive value at the current moment;

[0018] The likelihood information calculation module performs calculations based on the recursive value to obtain a likelihood ratio result;

[0019] The extrinsic information calculation module is used to calculate the extrinsic information generated by the current decoder according to the result of the likelihood ratio.

[0020] Furthermore, the branch metric calculation module is composed of an adder and an inverter.

[0021] Furthermore, the forward recursive module and the backward recursive module are both composed of adders and comparators.

[0022] Furthermore, the Turbo decoding circuit performs decoding in a parallel decoding manner.

[0023] Another technical solution adopted in the present invention is:

[0024] A decoding method, applied to the Turbo decoding circuit as described above, comprises the following steps:

[0025] The detection value s(k) of the information sequence, the detection value p(k) of the first check sequence and the prior information of the information bit sequence are Input the first decoder and output the posterior information

[0026] Posterior information After one interleaving, the data is input into the second decoder;

[0027] The detection value s(k) is interleaved once and then input into the second decoder;

[0028] After the second interleaver receives the detection value p'(k) of the second check sequence, it performs decoding calculation and outputs the posterior information of each bit of the information sequence

[0029] Posterior information After one deinterleaving, it is used as the prior information of the first decoder in the next iteration.

[0030] Information is continuously exchanged and iterated between the two decoders until the Turbo code decoding performance requirements are met.

[0031] The beneficial effects of the present invention are as follows: the present invention converts the input and output calculation process of the decoder into a logarithmic form, converts the multiplication operation into an addition operation, avoids complex exponential operations, greatly simplifies the operation process, reduces the decoding delay, and can achieve low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following introduction is made to the drawings of the embodiments of the present invention or the related technical solutions in the prior art. It should be understood that the drawings introduced below are only for the convenience of clearly describing some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative work.

[0033] Figure 1 is a structural diagram of a Turbo decoder circuit according to an embodiment of the present invention;

[0034] Figure 21 is an overall circuit diagram of a low-power Turbo code decoding circuit according to an embodiment of the present invention;

[0035] Figure 3 is a schematic diagram of the concept of a grid graph edge in an embodiment of the present invention;

[0036] Figure 4 is a circuit diagram of a branch metric calculation module in an embodiment of the present invention;

[0037] Figure 5 1 is a circuit diagram of a forward state metric and a backward state metric calculation module in an embodiment of the present invention;

[0038] Figure 6 This is a circuit diagram of a likelihood ratio calculation module and an external information calculation module in an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention and are not to be construed as limiting the present invention. The step numbers in the following embodiments are provided for ease of explanation only and do not limit the order of the steps. The order of execution of the steps in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0040] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.

[0041] In the description of the present invention, "several" means one or more, "many" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" in the description is solely for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, implicitly specifying the number of the indicated technical features, or implicitly specifying the order of the indicated technical features.

[0042] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0043] Since the MAP algorithm was proposed earlier, after decades of revisions and improvements, its decoding performance has approached the Shannon limit while significantly reducing the decoding computational complexity. This improved MAP algorithm has been widely adopted in practical applications. The Max-Log-MAP algorithm involved in the present invention is a further simplification of the MAP algorithm. Compared with the Log-MAP algorithm, it uses the max() function to simulate the max*() function, eliminating the data table lookup process, further simplifying the computational process, reducing decoding delay, complexity, and required storage space. This simplification results in a loss of approximately 0.3dB in decoding performance. However, for applications with a large overall system gain margin, this performance loss is significantly offset by the hardware cost and real-time performance. The following describes the Turbo code decoding circuit of the present invention in detail.

[0044] like Figure 1 As shown, Figure 1 The following is a block diagram of a turbo decoder circuit. Turbo code decoding is an iterative process. The turbo code decoding circuit includes two decoders (decoder 1 and decoder 2) with identical structures. In this embodiment, both decoders are soft input and output decoders (SISO). The decoder input is the a priori information of the system information bits, and after decoding, the output is the a posteriori information of the system information bits.

[0045] Figure 1 The parameters in are defined as follows:

[0046] p(k)—check information, check the detection value of the sequence.

[0047] s(k)—system information, detection value of information sequence.

[0048] La(u k )—prior information, which comes from the initial prior information or the result of the previous iteration.

[0049] Le(u k )—A posteriori information, the output result of the information bits calculated by the decoding algorithm.

[0050] L(u k )—likelihood information, input code element information u k The log-likelihood ratio.

[0051] In one iteration, the input of decoder 1 is the detection value s(k) of the received information sequence, the detection value p(k) of the check sequence generated by the first sub-encoder, and the prior information of the information bit sequence. After decoding operation, the posterior information of each bit of the information sequence is output After the a posteriori information is interleaved once, it is input to decoder 2 and used as its a priori information. At the same time, the received information sequence s(k) is also interleaved once and input to decoder 2, and the check sequence p'(k) corresponding to the second sub-encoder is received. After decoding calculation, decoder 2 outputs the a posteriori information of each bit of the (interleaved) information sequence. After a single deinterleaving, the a posteriori information sequence is fed into decoder 2 and used as the a priori information for decoder 1 in the next iteration. This continuous exchange and iteration of soft information between the two sub-decoders ensures the required Turbo code decoding performance.

[0052] Before analyzing the decision function, we first define the concept of edges in the grid, also called branches (corresponding to branch metrics), such as Figure 3 As shown in the figure. The starting state and ending state of the edge are and The input information symbol is u k (e), the code word is c k (e), the time index is k. It can be seen that at time k, the input information bits and the starting state uniquely determine the output codeword, the ending state, and the edges in the grid graph. Here

[0053] Figure 3 The definitions of the characters in are as follows:

[0054] u k —The information bits input at time k.

[0055] c k —The encoding output codeword at time k.

[0056] X k —The symbol sent at time k.

[0057] Y k —The received symbol at time k.

[0058] —Send the coded sequence from the signal X at time i i Signal X at time j j The corresponding sequence.

[0059] —Receive the coded sequence from the signal Y at time i i Signal Y at time j j The corresponding sequence.

[0060] For the decoder of MAP algorithm, the output code element information u k The posterior probability log-likelihood ratio is as shown in Formula 1:

[0061]

[0062] The received information bit u has two codeword states u = 0 or 1, then the posterior probability of the decoded output information bit probability at time k is shown in formula 2:

[0063]

[0064] After deriving the forward recursion and backward recursion, the remaining γ k (s) is the branch transfer probability, also known as the branch metric, which can be derived as Formula 3 using the Bayesian formula:

[0065]

[0066] In summary, after deriving the forward recursion, backward recursion, and branch metric, the MAP algorithm uses the log-likelihood ratio (LLR) as the decision function, as shown in Formula 4:

[0067]

[0068] As can be seen from the above, the MAP decoding algorithm contains a large number of exponential operations and multiplication operations, resulting in high decoding complexity and difficulty in hardware implementation. Therefore, in this embodiment, by converting the input and output calculation process of the decoder into logarithmic form, multiplication operations are converted into addition operations to avoid complex exponential operations. The key forward recursion, backward recursion, and branch metrics are logarithmized and the Jacobian equation is introduced based on the calculations in the map algorithm, as shown in Formula 5:

[0069] ln(e x +e y )=max(x,y)+ln(1+e -|x-y| )=max*(x,y) (5)

[0070] The Max-Log-MAP algorithm is a further simplification of the MAP algorithm. Compared with the Log-MAP algorithm, the max() function is used to simulate the max*() function. The result of simplifying the decision function of the Log-MAP algorithm is shown in Formula 6. Finally, the decoding result calculated by the Max-Log-MAP algorithm is According to L M-log (u k ) is determined by the value of , as shown in Formula 7.

[0071]

[0072]

[0073] like Figure 2As shown in FIG2, FIG2 is the overall circuit diagram of the Turbo code decoding. Figure 2 As can be seen, the decoder includes branch metric calculation M k , forward recursion module, backward recursion module, likelihood information calculation LLR and external information calculation L e Four parts.

[0074] See also Figure 4 , Figure 4 This is the circuit diagram of the branch metric calculation module. The transmission channel model of this system is a channel ratio of E s / N o Additive White Gaussian Noise (AWGN) channel, the coded information is modulated by BPSK in the channel, and the check information symbol sent is is the result of bipolar transformation of code element, that is According to the state transition diagram of the Turbo code introduced above, there are only two edges from any state at a certain moment to a certain state at the next moment. Therefore, there are only four edges in the grid diagram that can perform state transitions at adjacent moments. When the check bit is ±1, the external information Le and Different combinations of branch metrics M k (e) Take four different values, namely M k (0,0),M k (0,1),M k (1,0),M k (1,1).

[0075] See also Figure 5 , Figure 5 This is the circuit diagram of the forward state metric and backward state metric calculation modules, and the circuit diagram of the multiplexer in the Turbo code encoding circuit. The state metric module calculation adopts a feedback iterative structure, feeding back the new state metric value obtained from the operation to the input terminal for participation in the next recursive operation. Figure 5 This is a diagram of the hardware implementation of a four-state forward recursion, and the same applies to backward recursion. The forward and backward recursion values are two important intermediate variables in the Turbo decoding iteration process. As can be seen from the circuit structure in the figure, the recursion value is calculated by adding and comparing the corresponding branch metric value and the recursion value at the previous moment to calculate the current recursion value.

[0076] See also Figure 6 The figure is the circuit diagram of the likelihood ratio calculation module and the external information calculation module. In the likelihood ratio calculation module, it can be divided into four parts. The first and second parts calculate the input data u kTaking the path when it is 0 or 1, the third and fourth parts compare the corresponding branch metrics and state metrics, and finally obtain the likelihood ratio result. The extrinsic information calculation module circuit module calculates the extrinsic information generated by the current sub-decoder, and this information will be fed back to the other sub-decoder for use as prior information.

[0077] from Figure 4-Figure 6 It can be clearly seen that all operations in the decoder are simple addition or comparison operations, which greatly simplifies the operation process, reduces decoding delay, and reduces complexity and required storage space. Figure 2 In addition, the Turbo code decoding circuit adopts a parallel decoding method to calculate the forward recursive value and the backward recursive value at the same time, improves the decoding structure, and can effectively reduce power consumption.

[0078] In summary, compared with the prior art, this embodiment has the following advantages and beneficial effects: the Turbo code decoding circuit of this embodiment is not only simple in operation but also has low power consumption. It is implemented in the Verilog hardware description language and simulated and synthesized with the Altera Cyclone IV EP4CE75F23C8 as the target device. The simulation shows that the power consumption of the encoding circuit is less than 30mW at a frequency of 125MHz, which can meet the low power consumption requirements in NB-IoT application scenarios.

[0079] In the above description of this specification, reference to the terms "one embodiment / example," "another embodiment / example," or "certain embodiments / examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0080] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

[0081] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A Turbo decoding circuit, characterized in that: comprising a first decoder, a second decoder, a first interleaver, a second interleaver and a deinterleaver; The decoding process of the turbo decoding circuit is an iterative process, the input is the prior information of the system information bit, and after decoding, the output is the a posteriori information of the system information bit; One of the iterations is as follows: The input information of the first decoder includes the detection value s(k) of the information sequence, the detection value p(k) of the first check sequence, and the prior information of the information bit sequence The first decoder outputs the posterior information of each bit of the information sequence Posterior information After passing through the first interleaver, the information sequence is input to the second decoder; the detection value s(k) of the information sequence is input to the second decoder after passing through the second interleaver; The second decoder receives the detection value p'(k) of the second check sequence, performs decoding calculation, and outputs the posterior information of each bit of the information sequence Posterior information After the deinterleaver, it is used as the prior information of the first decoder in the next iteration. Convert the decoder's input and output calculation process into logarithmic form and convert multiplication operations into addition operations to avoid complex exponential operations; In the decoder, the forward recursion, backward recursion and branch metrics are logarithmized and then calculated; The decoder includes a branch metric calculation module, a forward recursion module, a backward recursion module, a likelihood information calculation module and an external information calculation module; The input information of the branch metric calculation module is the detection value s(k), the detection value p(k), the prior information Output four different values of branch metric M k (e), respectively M k (0,0),M k (0,1),M k (1,0),M k (1,1); The forward recursion module and the backward recursion module are based on the four branch metrics M k (e) performing calculations to obtain the recursive value at the current moment; The likelihood information calculation module performs calculations based on the recursive value to obtain a likelihood ratio result; The external information calculation module is used to calculate the external information generated by the current decoder according to the result of the likelihood ratio; The branch metric calculation module is composed of an adder and an inverter; The detection value s(k) and the detection value p(k) are respectively input into the two input terminals of the first adder; the detection value s(k) is input into the first input terminal of the second adder, and the detection value p(k) is input into the second input terminal of the second adder through an inverter; The first input end of the third adder is connected to the output end of the first adder, and the second input end is connected to the prior information. Output branch metric M k (0,0); The first input terminal of the fourth adder is connected to the output terminal of the first adder through an inverter. The output terminal of the fourth adder outputs the branch metric M. k (0,1); The first input terminal of the fifth adder is connected to the output terminal of the second adder, and the second input terminal inputs the prior information Output branch metric M k (1,0); The first input terminal of the sixth adder is connected to the output terminal of the second adder through an inverter. The second input terminal of the sixth adder is input through an inverter, and the output terminal outputs the branch metric M. k (1,1).

2. A Turbo decoding circuit according to claim 1, characterized in that: The first decoder and the second decoder have the same structure, both being soft input and output decoders; Information is continuously exchanged and iterated between the two decoders to achieve the required Turbo code decoding performance.

3. The Turbo decoding circuit according to claim 1, wherein: The forward recursive module and the backward recursive module are both composed of adders and comparators.

4. The Turbo decoding circuit according to claim 1, wherein: The Turbo decoding circuit performs decoding in a parallel decoding manner.

5. A decoding method, applied to a Turbo decoding circuit according to any one of claims 1 to 4, characterized in that: The following steps are involved: The detection value s(k) of the information sequence, the detection value p(k) of the first check sequence and the prior information of the information bit sequence are Input the first decoder and output the posterior information Posterior information After one interleaving, the data is input into the second decoder; The detection value s(k) is interleaved once and then input into the second decoder; After the second decoder receives the detection value p'(k) of the second check sequence, it performs decoding calculation and outputs the posterior information of each bit of the information sequence Posterior information After one deinterleaving, it is used as the prior information of the first decoder in the next iteration. Information is continuously exchanged and iterated between the two decoders until the Turbo code decoding performance requirements are met.

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