Comparators, ADCs, and Image Sensors
By designing a new comparator in the CMOS image sensor, using the amplification module, potential pull-up module and sampling module, avoiding continuous quiescent current, the problem of high overall power consumption of the CMOS image sensor is solved, and significant power consumption reduction is achieved .
Patent Information
- Application Number
- CN202211157120.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-09-22
- Publication Date
- 2024-12-27
- Estimated Expiration
- 2042-09-22
AI Technical Summary
The overall power consumption of existing CMOS image sensors is large, mainly due to the high static power consumption of column ADCs. Traditional comparators require continuous quiescent current to work, resulting in large power consumption.
A comparator is designed, including an amplification module, a potential pulling module, a sampling module and a reset module. The amplification module receives pixel signals and ramp signals, and only turns on when the ramp signal potential is higher than a specific difference to avoid continuous quiescent current. , the potential pulling module pulls up the potential when the potential is lower than a specific difference value, and the sampling module charges the power supply and lowers the potential when it is turned on, reducing power consumption.
It effectively reduces the overall power consumption of CMOS image sensor, which is only 3% of that of traditional comparators, and has a simple structure and occupies a smaller design space.
Smart Images
Figure CN115514910B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a comparator, an analog-to-digital converter and an image sensor. Background Art
[0002] CMOS Image Sensor (CIS) has been widely used in imaging fields such as video, surveillance, industrial manufacturing, automobiles, and home appliances. With the continuous improvement of various application requirements, CIS resolution and frame rate are also increasing, and CIS power consumption is also increasing. The increase in temperature will bring many problems, including the increase in CIS pixel dark current noise, packaging heat dissipation problems, etc., which will directly affect the final imaging quality. While ensuring performance, reducing CIS power consumption as much as possible has become a technical difficulty. The current mainstream CIS readout circuit is an architecture based on column-parallel ADC. To reduce the overall power consumption of CIS, the most important thing is to reduce the power consumption of the column ADC. The static power consumption of the column ADC comes from the comparator. Traditional comparators need to be under continuous static current to ensure normal operation, and their power consumption is relatively large.
[0003] For example, a Chinese patent with publication number CN104617930B discloses a comparator and an analog-to-digital converter using the comparator, wherein a bias voltage is set at each amplifier stage so that the corresponding transistor acts as a current source in the corresponding amplifier stage. The comparator needs to be operated normally under a continuous static current, and its power consumption is relatively large.
[0004] Therefore, the present invention provides a comparator, an analog-to-digital converter, and an image sensor to reduce the overall power consumption of the image sensor. Summary of the invention
[0005] The present invention provides a comparator, an analog-to-digital converter and an image sensor to solve the problem of high overall power consumption of a CIS in the prior art.
[0006] In a first aspect, the present invention provides a comparator, which is applied to a CMOS image sensor and connected to a counter, and includes: an amplification module, a potential pull-up module, a sampling module, a first reset module, and a second reset module; the amplification module receives a pixel signal and a ramp signal, and is used to amplify the comparison result of the pixel signal and the ramp signal, and when the potential of the ramp signal is higher than the potential of a first difference, there is no current on the amplification module, and the first difference is the difference between the potential of the pixel signal and the threshold voltage of the amplification module; the amplification module is connected to the first output end of the comparator, and the first output end of the comparator is used to output the amplified comparison result; the first reset module is also connected to the first output end of the comparator, and is used to reset the potential of the first output end of the comparator; the second reset module is connected to the second output end of the comparator, and the The second reset module is used to reset the potential of the second output end of the comparator. After the first output end of the comparator and the second output end of the comparator are reset, the comparator enters the comparison state and the counter starts counting; the potential pull-up module is connected to the second output end of the comparator and the power supply respectively. The potential pull-up module is used to pull up the potential of the second output end of the comparator when the potential of the first output end of the comparator is lower than the second difference. The second difference is the difference between the power supply voltage and the threshold voltage of the potential pull-up module; the amplification module and the first output end of the comparator are both connected to the sampling module. The sampling module is charged by the power supply and is used to pull down the potential of the first output end of the comparator when the amplification module is turned on; when the potential of the second output end of the comparator is pulled up, the counter stops counting.
[0007] The beneficial effect is that the comparator provided by the present invention does not need a bias voltage to provide a static current. When the potential of the ramp signal is higher than the potential of the first difference, there is no current on the amplification module, and the amplifier module will not be powered on all the time during the operation of the comparator. The duration of the ramp signal being higher than the first difference accounts for a large proportion of the working stage of the comparator, so the present invention can reduce the overall power consumption of the CIS to solve the problem of high power consumption in the prior art.
[0008] Optionally, the amplification module includes a first N-type transistor, the gate of the first N-type transistor receives the pixel signal, the source of the first N-type transistor receives the ramp signal, the drain of the first N-type transistor, the first end of the first reset module, the first end of the sampling capacitor and the third end of the potential pull-up module are all connected to the first output end of the comparator, and the first N-type transistor is used to amplify the comparison result of the pixel signal and the ramp signal. The beneficial effect is that the amplification module provided by the present invention has a simple structure and can occupy a smaller design space.
[0009] Optionally, the potential-raising module includes a second P-type transistor, the drain of the first N-type transistor, the first end of the first reset module, the first end of the sampling capacitor, and the gate of the second P-type transistor are all connected to the first output end of the comparator, and the source of the second P-type transistor is connected to the power supply; the drain of the second P-type transistor and the first end of the second reset module are all connected to the second output end of the comparator, and the second P-type transistor is used to raise the potential of the second output end of the comparator when the potential of the first output end of the comparator is lower than the second difference. Its beneficial effect is that the potential-raising module provided by the present invention has a simple structure and can occupy a smaller design space.
[0010] Optionally, the first reset module includes a first P-type transistor, the drain of the first N-type transistor, the drain of the first P-type transistor, the first end of the sampling module, and the gate of the second P-type transistor are all connected to the first output end of the comparator, the gate of the first P-type transistor receives a first reset control signal, the source of the first P-type transistor is connected to a power supply, and the first P-type transistor is used to reset the potential of the first output end of the comparator. The beneficial effect is that the first reset module provided by the present invention has a simple structure and can occupy a smaller design space.
[0011] Optionally, the second reset module includes a second N-type transistor, the drain of the first N-type transistor, the drain of the first P-type transistor, the first end of the sampling module and the gate of the second P-type transistor are all connected to the first output end of the comparator, the source of the second N-type transistor is grounded, the drain of the second P-type transistor and the drain of the second N-type transistor are all connected to the second output end of the comparator, and the second N-type transistor is used to reset the potential of the second output end of the comparator. Its beneficial effect is that the second reset module provided by the present invention has a simple structure and can occupy a smaller design space.
[0012] Optionally, the sampling module includes a sampling capacitor, the drain of the first N-type transistor, the drain of the first P-type transistor, the first end of the sampling capacitor and the gate of the second P-type transistor are all connected to the first output end of the comparator, the second end of the sampling capacitor is grounded, the sampling capacitor samples the comparison result, and is used to pull down the potential of the first output end of the comparator when the first N-type transistor is turned on. The beneficial effect is that the sampling capacitor is used to pull down the potential of the first output end of the comparator when the first N-type transistor is turned on.
[0013] In a second aspect, the present invention provides an analog-to-digital converter, comprising: a counter and a comparator as described in any one of the first aspects; the first output end of the comparator and the second output end of the comparator are both connected to the counter, and the counter is used to count according to the output results of the first output end of the comparator and the second output end of the comparator.
[0014] In a third aspect, the present invention provides an image sensor, comprising: a pixel array, an analog-to-digital converter, and a ramp generator; the pixel array is used to output pixel signals; the ramp generator is used to output ramp signals; the analog-to-digital converter comprises a counter and a comparator as described in any one of the first aspects; the first output end of the comparator and the second output end of the comparator are both connected to the counter, and the counter is used to count according to the output results of the first output end of the comparator and the second output end of the comparator.
[0015] For the beneficial effects of the second to third aspects, reference may be made to the description of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 is a schematic diagram of the structure of a comparator in a traditional CIS in the prior art;
[0017] Figure 2 A schematic diagram of a comparator embodiment provided by the present invention;
[0018] Figure 3 A schematic diagram of a comparator circuit structure embodiment provided by the present invention;
[0019] Figure 4 A schematic diagram of a CIS readout operation timing provided by the present invention. DETAILED DESCRIPTION
[0020] The technical solutions in the embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application. Among them, in the description of the embodiments of the present application, the terms used in the following embodiments are only for the purpose of describing specific embodiments, and are not intended to be used as limitations on the present application. As used in the specification and the appended claims of the present application, the singular expressions "a", "the", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear indication to the contrary in the context. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" refer to one or more (including two). The term "and / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist; for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in a "or" relationship.
[0021] References to "one embodiment" or "some embodiments" etc. described in this specification mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Thus, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways. The term "connection" includes direct connection and indirect connection, unless otherwise specified. "First" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.
[0022] In the embodiments of the present application, the words "exemplarily" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present related concepts in a specific way.
[0023] Figure 1A comparator circuit in a traditional CIS is shown. Among them, the first capacitor C1 and the second capacitor C2 function to pass AC and block DC. The first transistor N1, the second transistor N2, the third transistor N3, the fourth transistor P1, and the fifth transistor P2 form a first-stage amplifier circuit of the comparator. The third transistor N3 is a current source tube, which provides a fixed bias current Ib for the first-stage amplifier circuit. The first transistor N1 and the second transistor N2 are input pairs, and the fourth transistor P1 and the fifth transistor P2 are active load tubes. The sixth transistor P3 and the seventh transistor N4 form a second-stage amplifier circuit of the comparator, and the sources of the sixth transistor P3 and the seventh transistor N4 are both grounded GND1. The seventh transistor N4 is a current source tube. The sources of the fourth transistor P1, the fifth transistor P2, and the sixth transistor P3 are all connected to the power supply VDD1. When the ramp signal RAMP is higher than the pixel signal PIX_OUT, the potential of the output terminal CM1 is high and the output terminal CM2 is low; otherwise, the potential of the output terminal CM1 is low and the output terminal CM2 is high. When the reset control signal RS_CM is at a low level, the first switch tube NS1, the second switch tube NS2, and the third switch tube NS3 are turned on, and the comparator is reset. The bias voltage VBN_CM is used to make the comparator generate a static current Ia. The comparator in the traditional CIS needs to work under the bias of a continuous static current to achieve a smaller flip delay and a larger gain effect.
[0024] In order to solve the problem of high overall power consumption of CIS in the prior art, the present invention provides a comparator, which is applied to a CMOS image sensor and connected to a counter, such as Figure 1As shown, the comparator includes: an amplification module 101, a potential pull-up module 102, a sampling module 103, a first reset module 104 and a second reset module 105. The amplification module 101 receives a pixel signal PIX_OUT and a ramp signal RAMP, and is used to amplify the comparison result between the pixel signal RAMP and the ramp signal PIX_OUT, and when the potential of the ramp signal RAMP is higher than the potential of the first difference, there is no current on the amplification module 101, and the first difference is the difference between the potential of the pixel signal PIX_OUT and the threshold voltage of the amplification module 101; the amplification module 101 is connected to the first output terminal CMO1 of the comparator, and the first output terminal CMO1 of the comparator is used to output the amplified comparison result; the first reset module 104 is also connected to the first output terminal CMO1 of the comparator, and is used to reset the potential of the first output terminal CMO1 of the comparator; the second reset module 105 is connected to the second output terminal CMO2 of the comparator, and the second reset module 105 is used to reset the potential of the second output terminal CMO2 of the comparator. After the first output terminal CMO1 of the comparator and the second output terminal CMO2 of the comparator are reset, the comparator enters the comparison state and the counter starts counting; the potential-pulling module 102 is connected to the second output terminal CMO2 of the comparator and the power supply VDD respectively, and the potential-pulling module 102 is used to pull up the potential of the second output terminal CMO2 of the comparator when the potential of the first output terminal CMO1 of the comparator is lower than the second difference, and the second difference is the difference between the power supply voltage and the threshold voltage of the potential-pulling module 102; the amplification module 101 and the first output terminal CMO1 of the comparator are both connected to the sampling module 103, and the sampling module 103 is charged by the power supply VDD and is used to pull down the potential of the first output terminal CMO1 of the comparator when the amplification module 101 is turned on; when the potential of the second output terminal CMO2 of the comparator is pulled up, the counter stops counting.
[0025] In some embodiments, the amplification module includes a first N-type transistor, the gate of the first N-type transistor receives the pixel signal, the source of the first N-type transistor receives the ramp signal, the drain of the first N-type transistor, the first end of the first reset module, the first end of the sampling capacitor and the third end of the potential pull-up module are all connected to the first output end of the comparator, and the first N-type transistor is used to amplify the comparison result of the pixel signal and the ramp signal.
[0026] In some embodiments, the potential pull-up module includes a second P-type transistor, the drain of the first N-type transistor, the first end of the first reset module, the first end of the sampling capacitor and the gate of the second P-type transistor are all connected to the first output end of the comparator, and the source of the second P-type transistor is connected to the power supply; the drain of the second P-type transistor and the first end of the second reset module are all connected to the second output end of the comparator, and the second P-type transistor is used to pull up the potential of the second output end of the comparator when the potential of the first output end of the comparator is lower than the second difference.
[0027] In some embodiments, the first reset module includes a first P-type transistor, the drain of the first N-type transistor, the drain of the first P-type transistor, the first end of the sampling module, and the gate of the second P-type transistor are all connected to the first output end of the comparator, the gate of the first P-type transistor receives a first reset control signal, the source of the first P-type transistor is connected to a power supply, and the first P-type transistor is used to reset the potential of the first output end of the comparator.
[0028] In some embodiments, the second reset module includes a second N-type transistor, the drain of the first N-type transistor, the drain of the first P-type transistor, the first end of the sampling module and the gate of the second P-type transistor are all connected to the first output end of the comparator, the source of the second N-type transistor is grounded, the drain of the second P-type transistor and the drain of the second N-type transistor are all connected to the second output end of the comparator, and the second N-type transistor is used to reset the potential of the second output end of the comparator.
[0029] In some embodiments, the sampling module includes a sampling capacitor, the drain of the first N-type transistor, the drain of the first P-type transistor, the first end of the sampling capacitor and the gate of the second P-type transistor are all connected to the first output end of the comparator, the second end of the sampling capacitor is grounded, the sampling capacitor samples the comparison result, and is used to lower the potential of the first output end of the comparator when the first N-type transistor is turned on.
[0030] In order to better illustrate the comparator provided in this application, an example is given here:
[0031] like Figure 3 As shown, the comparator includes: a first N-type transistor M1, a drain of the first P-type transistor M2, the second P-type transistor M3, a second N-type transistor M4 and a sampling capacitor C3.
[0032] The gate of the first N-type transistor M1 receives the pixel signal PIX_OUT, the source of the first N-type transistor M1 receives the ramp signal RAMP, the drain of the first N-type transistor M1, the drain of the first P-type transistor M2, the first end of the sampling capacitor C3 and the gate of the second P-type transistor M3 are all connected to the first output end CMO1 of the comparator, and the first output end CMO1 of the comparator is used to output a first signal; the gate of the first P-type transistor M2 receives the first reset control signal RST1_CM, and the source of the first P-type transistor M2 is connected to the power supply VDD2; the source of the second P-type transistor M3 is connected to the power supply VDD2, the drain of the second P-type transistor M3 and the drain of the second N-type transistor M4 are all connected to the second output end CMO2 of the comparator, and the second output end CMO2 of the comparator is used to output a second signal; the gate of the second N-type transistor M4 receives the second reset control signal RST2_CM, and the source of the second N-type transistor M4 is grounded GND2; the second end of the sampling capacitor C3 is grounded GND2. The sampling capacitor C3 is a charging capacitor, and the power supply VDD2 charges the upper plate of the sampling capacitor C3. The first output terminal CMO1 of the comparator and the second output terminal CMO2 of the comparator are connected to a counter.
[0033] Specifically, combined Figure 4 The timing sequence shown is described as follows: first, the second reset control signal RST2_CM is at a high level, and the second N-type transistor M4 resets the potential of the second output terminal CMO2 of the comparator to the potential of the ground GND2. The first reset control signal RST1_CM is at a low level, and the first P-type transistor M2 resets the potential of the first output terminal CMO1 to the potential of the power supply VDD2, that is, the potential of the upper plate of the sampling capacitor C3 is the potential of the power supply VDD2. After that, the second reset control signal RST2_CM is at a low level, and the first reset control signal RST1_CM is at a high level, and the comparator enters the comparison state. The potential of the first output terminal CMO1 of the comparator is at a high level, so at this time the second P-type transistor M3 is turned off, and the second P-type transistor M3 and the second N-type transistor M4 do not form a path and no current flows. The ramp signal RAMP first becomes a high level, and is higher than the potential of the pixel signal PIX_OUT, so at this time the potential of the drain of the first N-type transistor M1 is higher than the potential of its gate, and the first N-type transistor M1 is also turned off. No current flows through the first N-type transistor M1 and the first P-type transistor M2 either.
[0034] exist Figure 4In the VR stage, the ramp signal RAMP will gradually decrease. When the potential of the ramp signal RAMP is as low as the difference VRST-Vthn between the reset signal VRST in the pixel signal PIX_OUT and the threshold voltage Vthn of the first N-type transistor M1, the gate-source voltage VGS8 of the first N-type transistor M1 is greater than the threshold voltage Vthn of the first N-type transistor M1. The first N-type transistor M1 is turned on, and the charge on the sampling capacitor C3 will be discharged through the first N-type transistor M1 to the end of the first N-type transistor M1 to obtain the ramp signal RAMP, so that the potential of the first output terminal CMO1 of the comparator is reduced. When the potential of the first output terminal CMO1 of the comparator is as low as the difference between the power supply voltage VDD and the threshold voltage Vthp of the second P-type transistor M3, the second P-type transistor M3 is turned on and the potential of the second output terminal CMO2 of the comparator is pulled up. The potential of the second output terminal CMO2 of the comparator changes from a low level to a high level, which will stop the counter from counting.
[0035] exist Figure 4 In the first flipping stage of the comparator, the VR stage, the first counting time t1' corresponds to the first counting value CN1', after which the ramp signal RAMP jumps to a potential greater than the reset signal VRST in the pixel signal PIX_OUT, which turns off the first N-type transistor M1 and the second P-type transistor M3, and the comparator stops working; similarly, in the second flipping stage of the comparator, the VS stage, when the potential of the ramp signal RAMP is lower than the difference VSIG-Vthn between the integral signal VSIG and the threshold voltage Vthn of the first N-type transistor M1, the comparator flips. In the VS stage, the second counting time t2' corresponds to the second counting value CN2', after which the ramp signal RAMP jumps to a potential greater than the integral signal VSIG, which turns off the first N-type transistor M1 and the second P-type transistor M3, and the comparator stops working. Finally, the counter CNT outputs a count difference value of ΔCN', which is the difference between the second count value CN2' and the first count value CN1', that is, ΔCN'=CN2'-CN1'. Since the comparison delay of the comparator in the VR stage and the VS stage is the same, the final output data obtained by the comparator provided in the present application is the same as the counting result obtained by the traditional comparator. However, the comparator provided in the present application is only turned on when the potential of the ramp signal RAMP in the VR stage and the VS stage is lower than the difference VRST-Vthn between the reset signal VRST and the threshold voltage Vthn of the first N-type transistor M1, and the difference VSIG-Vthn between the integral signal VSIG and the threshold voltage Vthn of the first N-type transistor M1.
[0036] Since the comparator provided in the present application does not operate under a continuous static current, the current it generates comes from discharging the charge collected by the sampling capacitor C3, so the power generated in the two stages is the product of the capacitance of the sampling capacitor C3 and the voltage of the power supply VDD2. Assume that the capacitance of the sampling capacitor C3 is 100fF and the voltage of the power supply VDD2 is 3V. The conduction time of the comparator in the two flipping stages is about 5μs in total. Then in this example, the total power consumption of the comparator provided in the present application in the two stages is (2×100fF×9V2) / 5μs=0.36μW. With a traditional comparator, the static bias current is generally 4~10μA, and the minimum power consumption is 4μA×3V=12μW. It can be seen that the power consumption of the comparator provided in the present application is only 0.36 / 12=3% of the traditional comparator, and the power consumption is significantly reduced.
[0037] Based on the comparator provided in any one of the above embodiments, the present invention also provides an analog-to-digital converter, comprising: a counter and the comparator as described in any one of the above embodiments; the first output end of the comparator and the second output end of the comparator are both connected to the counter, and the counter is used to count according to the output results of the first output end of the comparator and the second output end of the comparator.
[0038] Based on the comparator provided by any of the above embodiments, the present invention also provides an image sensor, comprising: a pixel array, an analog-to-digital converter, and a ramp generator; the pixel array is used to output pixel signals; the ramp generator is used to output ramp signals; the analog-to-digital converter includes a counter and a comparator as described in any of the above embodiments; the first output end of the comparator and the second output end of the comparator are both connected to the counter, and the counter is used to count according to the output results of the first output end of the comparator and the second output end of the comparator.
[0039] The above is only a specific implementation of the embodiment of the present application, but the protection scope of the embodiment of the present application is not limited thereto, and any changes or replacements within the technical scope disclosed in the embodiment of the present application should be included in the protection scope of the embodiment of the present application. Therefore, the protection scope of the embodiment of the present application should be based on the protection scope of the claims.
Claims
1. A comparator, characterized in that: It is applied to CMOS image sensor and connected with the counter, and includes: an amplification module, a potential pull-up module, a sampling module, a first reset module and a second reset module; The amplification module receives a pixel signal and a ramp signal, and is used to amplify a comparison result between the pixel signal and the ramp signal, and when the potential of the ramp signal is higher than the potential of a first difference, there is no current on the amplification module, and the first difference is the difference between the potential of the pixel signal and a threshold voltage of the amplification module; The amplification module is connected to the first output terminal of the comparator, and the first output terminal of the comparator is used to output the amplified comparison result; The first reset module is also connected to the first output end of the comparator, and is used to reset the potential of the first output end of the comparator; the second reset module is connected to the second output end of the comparator, and the second reset module is used to reset the potential of the second output end of the comparator. After the first output end of the comparator and the second output end of the comparator are reset, the comparator enters the comparison state, and the counter starts counting; The potential-raising module is connected to the second output terminal of the comparator and the power supply respectively, and is used to raise the potential of the second output terminal of the comparator when the potential of the first output terminal of the comparator is lower than the second difference, and the second difference is the difference between the power supply voltage and the threshold voltage of the potential-raising module; The amplification module and the first output end of the comparator are both connected to the sampling module, the sampling module is charged by the power supply, and is used to pull down the potential of the first output end of the comparator when the amplification module is turned on; When the potential of the second output terminal of the comparator is pulled high, the counter stops counting.
2. The comparator according to claim 1, characterized in that: The amplification module includes a first N-type transistor, a gate of the first N-type transistor receives the pixel signal, a source of the first N-type transistor receives the ramp signal, a drain of the first N-type transistor, a first end of the first reset module, a first end of the sampling capacitor, and a third end of the potential pull-up module are all connected to the first output end of the comparator, and the first N-type transistor is used to amplify the comparison result of the pixel signal and the ramp signal.
3. The comparator according to claim 2, characterized in that: The potential-raising module includes a second P-type transistor, the drain of the first N-type transistor, the first end of the first reset module, the first end of the sampling capacitor, and the gate of the second P-type transistor are all connected to the first output end of the comparator, and the source of the second P-type transistor is connected to the power supply; the drain of the second P-type transistor and the first end of the second reset module are all connected to the second output end of the comparator, and the second P-type transistor is used to raise the potential of the second output end of the comparator when the potential of the first output end of the comparator is lower than the second difference.
4. The comparator according to claim 3, characterized in that: The first reset module includes a first P-type transistor, the drain of the first N-type transistor, the drain of the first P-type transistor, the first end of the sampling module and the gate of the second P-type transistor are all connected to the first output end of the comparator, the gate of the first P-type transistor receives a first reset control signal, the source of the first P-type transistor is connected to a power supply, and the first P-type transistor is used to reset the potential of the first output end of the comparator.
5. The comparator according to claim 4, characterized in that: The second reset module includes a second N-type transistor, the drain of the first N-type transistor, the drain of the first P-type transistor, the first end of the sampling module and the gate of the second P-type transistor are all connected to the first output end of the comparator, the source of the second N-type transistor is grounded, the drain of the second P-type transistor and the drain of the second N-type transistor are all connected to the second output end of the comparator, and the second N-type transistor is used to reset the potential of the second output end of the comparator.
6. The comparator according to claim 5, characterized in that: The sampling module includes a sampling capacitor, the drain of the first N-type transistor, the drain of the first P-type transistor, the first end of the sampling capacitor and the gate of the second P-type transistor are all connected to the first output end of the comparator, the second end of the sampling capacitor is grounded, the sampling capacitor samples the comparison result, and is used to pull down the potential of the first output end of the comparator when the first N-type transistor is turned on.
7. An analog-to-digital converter, characterized in that: include: A counter and a comparator as claimed in any one of claims 1 to 6; The first output end of the comparator and the second output end of the comparator are both connected to the counter, and the counter is used to count according to the output results of the first output end of the comparator and the second output end of the comparator.
8. An image sensor, characterized in that: include: Pixel array, analog-to-digital converter, ramp generator; The pixel array is used to output pixel signals; The ramp generator is used to output a ramp signal; The analog-to-digital converter includes a counter and a comparator as described in any one of claims 1-6; the first output end of the comparator and the second output end of the comparator are both connected to the counter, and the counter is used to count according to the output results of the first output end of the comparator and the second output end of the comparator.