Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device includes a semiconductor substrate provided with a drift region, and a buffer region disposed between the drift region and a lower surface and having a higher concentration than the drift region, a doping concentration distribution of which has a deepest slope, a doping concentration of the deepest slope monotonically decreasing toward a position where the drift region is connected in a direction from the lower surface toward an upper surface of the semiconductor substrate, and a hydrogen chemical concentration distribution in the buffer region having, in a first depth range where the deepest slope is provided, a first decreasing portion in which a hydrogen chemical concentration decreases toward the upper surface side, a second decreasing portion located at a position closer to the upper surface side than the first decreasing portion and in which the hydrogen chemical concentration decreases, and an intermediate portion disposed between the first decreasing portion and the second decreasing portion, the intermediate portion having a flat portion in which the hydrogen chemical concentration distribution is uniform, an inner peak of a slope of the hydrogen chemical concentration, or a turning portion of the hydrogen chemical concentration.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] Previously, it was known that a buffer layer (field cutoff layer) was provided in semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) (for example, see Patent Document 1).

[0003] Patent Document 1: WO2016 / 203545 Summary of the Invention

[0004] Technical issues

[0005] In semiconductor devices such as IGBTs, it is preferable to suppress the vibration of voltage or current waveforms during turn-off.

[0006] Technical solution

[0007] To address the aforementioned issues, in a first aspect of the present invention, a semiconductor device is provided, comprising a semiconductor substrate having an upper surface and a lower surface, and having a drift region of a first conductivity type. The semiconductor device may include a buffer zone of the first conductivity type disposed between the drift region and the lower surface, having a concentration higher than that of the drift region. The doping concentration distribution in the buffer zone may have a deepest slope, the doping concentration of which monotonically decreases from the lower surface of the semiconductor substrate toward the upper surface to a position adjacent to the drift region. The hydrogen chemical concentration distribution in the buffer zone may have a first decreasing portion within a first depth range where the deepest slope is provided, where the hydrogen chemical concentration decreases toward the upper surface. The hydrogen chemical concentration distribution may have a second decreasing portion located further above the upper surface than the first decreasing portion, and where the hydrogen chemical concentration decreases. The hydrogen chemical concentration distribution may have an intermediate portion disposed between the first and second decreasing portions. The intermediate portion may have a flat portion with uniform hydrogen chemical concentration distribution, an inner peak of the hydrogen chemical concentration slope, or a turning point in the hydrogen chemical concentration distribution.

[0008] The length of the deepest slope in the depth direction can be less than 5 μm.

[0009] The hydrogen chemical concentration distribution in the buffer zone can have an in-slope peak within the first depth range.

[0010] The hydrogen chemical concentration distribution in the buffer zone can have a flat portion within a first depth range. At the same depth as the flat portion of the hydrogen chemical concentration distribution, the slope of the hydrogen chemical concentration distribution can be gentler than the slope of the doping concentration distribution.

[0011] The length of the deepest slope in the depth direction of the semiconductor substrate can be 0.4 μm or more.

[0012] The hydrogen chemical concentration in the flat parts or peaks of the hydrogen chemical concentration distribution can be less than half of the hydrogen chemical concentration at the apex of the deepest slope.

[0013] The hydrogen chemical concentration distribution in the buffer zone may include a lower peak outside the first depth range, the lower peak being positioned closest to the lower end of the first depth range. The full width at half maximum (FWHM) of the inner peak may overlap with the FWHM of the lower peak.

[0014] The apex of one of the inner peaks and the lower peaks can be positioned outside the full width of the other peak.

[0015] The distance between the half-peak full width of the inner peak and the half-peak full width of the lower peak can be less than the full width of either half-peak.

[0016] The distance between the apex of the inner peak and the apex of the lower peak on the slope can be greater than 0.1 μm and less than 3 μm.

[0017] The distance between the inner peak and the lower peak of the slope and the lower surface of the semiconductor substrate can be less than 10 μm.

[0018] In a second aspect of the present invention, a method for manufacturing a semiconductor device is provided. The manufacturing method may include a buffer formation step, in which hydrogen ions are implanted from the lower surface of a semiconductor substrate having an upper surface and a lower surface and a drift region of a first conductivity type, thereby forming a buffer zone between the drift region and the lower surface with a concentration of the first conductivity type higher than that of the drift region. The buffer formation step may include an implantation step, in which hydrogen ions are implanted to the lower end of a first depth range adjacent to the drift region and to predetermined positions within the first depth range. The buffer formation step may include a heat treatment step, in which the semiconductor substrate is heat-treated to form a deepest slope, the doping concentration of which monotonically decreases from the lower end of the first depth range to the position adjacent to the drift region.

[0019] It should be noted that the above description of the invention does not list all the essential features of the invention. Furthermore, sub-combinations of these feature groups can also constitute separate inventions. Attached Figure Description

[0020] Figure 1 This is a top view showing an example of a semiconductor device 100.

[0021] Figure 2 yes Figure 1 An enlarged view of region D in the image.

[0022] Figure 3 It is shown Figure 2 A diagram of an example of the ee section.

[0023] Figure 4 It is shown Figure 3 A diagram showing an example of the doping concentration distribution along the depth direction at the location of the FF line.

[0024] Figure 5 This is a diagram showing an example of the distribution of doping concentration and hydrogen chemical concentration in buffer 20.

[0025] Figure 6 The distribution of doping concentration in buffer 20 of the comparative example is shown.

[0026] Figure 7 The distribution of doping concentration in buffer 20 of the comparative example is shown.

[0027] Figure 8 This is a diagram illustrating an example of the hydrogen chemical concentration distribution in buffer 20.

[0028] Figure 9 This is another example of the hydrogen chemical concentration distribution in buffer 20.

[0029] Figure 10 This is another example of the hydrogen chemical concentration distribution in buffer 20.

[0030] Figure 11 This is a diagram showing an example of the full width at half maximum (FWHM) of the lower peak 103 and the second bend 113.

[0031] Figure 12 This is another example of the full width at half maximum (FWHM) of the lower peak 103 and the second bend 113.

[0032] Figure 13 This is a diagram showing a portion of the manufacturing process of the semiconductor device 100.

[0033] Symbol Explanation

[0034] 10. Semiconductor substrate, 11. Well region, 12. Emitter region, 14. Base region, 15. Contact region, 16. Accumulation region, 18. Drift region, 20. Buffer zone, 21. Upper surface, 22. Collector region, 23. Lower surface, 24. Collector, 25. Concentration peak, 26. Upper surface side slope, 27. Lower surface side slope, 28. First depth range, 29. Straight portion, 30. Dummy trench, 31. Front end, 32. Dummy insulating film, 34. Dummy conductive portion, 38. Interlayer insulating film, 39. Straight portion, 40. Gate trench, 41. Front end, 42. Gate insulating film, 44. Gate conductive portion 52···Emitter, 54···Contact Hole, 60, 61···Mesa Section, 70···Transistor Section, 80···Diode Section, 81···Extension Region, 82···Cathode Region, 90···Edge Termination Structure Section, 100···Semiconductor Device, 101, 102···Distribution, 103···Lower Peak, 108, 109···Upper Surface Side Slope, 110···Middle Section, 112···First Bending Section, 113···Second Bending Section, 114···Flat Section, 115···Turn Section, 121···First Reduction Section, 122···Second Reduction Section, 130···Outer Peripheral Gate Wiring, 131···Active Side Gate Wiring, 160···Active Section, 162···End Edge, 164···Gate Pad Detailed Implementation

[0035] The present invention will now be described through embodiments thereof, but these embodiments do not limit the scope of the invention as defined in the claims. Furthermore, not all combinations of the features described in the embodiments are necessarily required for the technical solution of the invention.

[0036] In this specification, one side parallel to the depth direction of the semiconductor substrate is referred to as "upper," and the other side as "lower." Of the two main surfaces of a substrate, layer, or other component, one is referred to as the upper surface, and the other as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the actual orientation of the semiconductor device during mounting.

[0037] In this specification, rectangular coordinate axes, namely the X-axis, Y-axis, and Z-axis, are sometimes used to illustrate technical matters. Rectangular coordinate axes merely determine the relative positions of constituent elements and do not limit specific directions. For example, the Z-axis does not necessarily represent the direction of height relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite to each other. When the Z-axis direction is not specified as positive or negative, it refers to a direction parallel to both the +Z-axis and -Z-axis.

[0038] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are designated as the X-axis and Y-axis. An axis perpendicular to the upper and lower surfaces of the semiconductor substrate is designated as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Additionally, in this specification, the direction including the X-axis and Y-axis and parallel to the upper and lower surfaces of the semiconductor substrate is sometimes referred to as the horizontal direction.

[0039] Additionally, the region extending from the center of the semiconductor substrate in the depth direction to the upper surface of the semiconductor substrate is sometimes referred to as the upper surface side. Similarly, the region extending from the center of the semiconductor substrate in the depth direction to the lower surface of the semiconductor substrate is sometimes referred to as the lower surface side. In this specification, the center position in the depth direction of the semiconductor substrate is sometimes referred to as Zc.

[0040] In this specification, the terms "same" or "equal" may also include cases with errors caused by manufacturing deviations, etc. Such errors are, for example, within 10%.

[0041] In this specification, the conductivity type of the doped region containing impurities is described as P-type or N-type. In this specification, impurity sometimes specifically refers to either an N-type donor or a P-type acceptor, and is sometimes referred to as a dopant. In this specification, doping refers to introducing a donor or acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity type or a P-type conductivity type.

[0042] In this specification, doping concentration refers to the concentration of donors or acceptors at thermal equilibrium. In this specification, net doping concentration refers to the actual concentration obtained by adding the polarities of charges, with the donor concentration set to the concentration of positive ions and the acceptor concentration set to the concentration of negative ions. For example, if the donor concentration is set to N... D And set the acceptor concentration to N A Then the actual net doping concentration at any position becomes N. D -N A In this specification, the net doping concentration is sometimes described as the doping concentration only.

[0043] Donors have the function of supplying electrons to semiconductors. Acceptors have the function of taking electrons from semiconductors. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, formed by the combination of vacancies (V), oxygen (O), and hydrogen (H) present in a semiconductor, act as electron-supplying donors. In this specification, VOH defects are sometimes referred to as hydrogen donors.

[0044] In this specification, "P+" or "N+" indicates a higher doping concentration than "P" or "N" type, while "P-" or "N-" indicates a lower doping concentration than "P" or "N" type. Similarly, "P++" or "N++" indicates a higher doping concentration than "P+" or "N+" type. Unless otherwise stated, the units used in this specification are SI units. Although length is sometimes expressed in cm, all calculations should be converted to meters (m).

[0045] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electroactivated state. Chemical concentration (atomic density) can be measured using, for example, secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured using voltage-capacitance measurement (CV method). Alternatively, the carrier concentration measured using extended resistance measurement (SR method) can be used as the net doping concentration. The carrier concentration measured by CV or SR methods can be taken as the value under thermal equilibrium conditions. Furthermore, in the N-type region, the donor concentration is much greater than the acceptor concentration; therefore, the carrier concentration in this region can also be defined as the donor concentration. Similarly, in the P-type region, the carrier concentration in this region can also be defined as the acceptor concentration. In this specification, the doping concentration in the N-type region is sometimes referred to as the donor concentration, and the doping concentration in the P-type region is sometimes referred to as the acceptor concentration.

[0046] Furthermore, when the concentration distribution of donor, acceptor, or net dopant has a peak, the peak value can be taken as the concentration of donor, acceptor, or net dopant in that region. When the concentration of donor, acceptor, or net dopant is almost uniform, the average concentration of donor, acceptor, or net dopant in that region can also be taken as the concentration of donor, acceptor, or net dopant. In this specification, concentration per unit volume is expressed in atoms / cm³. 3 or / cm 3 This unit is used to indicate the concentration of donors or acceptors, or the chemical concentration, within a semiconductor substrate. The "atoms" designation can also be omitted.

[0047] The carrier concentration measured by the SR method can be lower than the donor or acceptor concentration. During the measurement of extended resistance, within the current flow range, there are cases where the carrier mobility of the semiconductor substrate is lower than the carrier mobility value in the crystalline state. This decrease in carrier mobility is due to the disorder (disorder) of the crystal structure caused by lattice defects, which disperses the carriers.

[0048] The donor or acceptor concentration calculated from the carrier concentration measured by the CV or SR method can be lower than the chemical concentration of the element representing the donor or acceptor. For example, in silicon semiconductors, the donor concentration of phosphorus or arsenic (which acts as a donor), or the acceptor concentration of boron (which acts as an acceptor), is approximately 99% of their chemical concentration. On the other hand, in silicon semiconductors, the donor concentration of hydrogen (which acts as a donor) is approximately 0.1% to 10% of the chemical concentration of hydrogen. The concentrations in this specification can be values ​​at room temperature. For example, values ​​at room temperature can be values ​​at 300 K (Kelvin) (approximately 26.9°C).

[0049] Figure 1 This is a top view showing an example of a semiconductor device 100. Figure 1 The diagram shows the positions of the components projected onto the upper surface of the semiconductor substrate 10. Figure 1 In this paper, only a portion of the components of the semiconductor device 100 are shown, and some components are omitted.

[0050] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate, but the material of the semiconductor substrate 10 is not limited to silicon.

[0051] The semiconductor substrate 10 has end edges 162 when viewed from above. In this specification, "viewed from above" refers to the view from the top surface of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two sets of end edges 162 that are opposite each other when viewed from above. Figure 1 In this configuration, the X and Y axes are parallel to either end edge 162. Additionally, the Z axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0052] An active portion 160 is provided on the semiconductor substrate 10. The active portion 160 is the region where, when the semiconductor device 100 is operated, the main current flows along the depth direction between the upper and lower surfaces of the semiconductor substrate 10. An emitter is provided above the active portion 160, but... Figure 1 Omitted in .

[0053] The active section 160 is provided with at least one of a transistor section 70 including transistor elements such as IGBTs and a diode section 80 including diode elements such as freewheeling diodes (FWDs). Figure 1 In this example, the transistor section 70 and the diode section 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10. In other examples, only one of the transistor section 70 and the diode section 80 may be provided in the active section 160.

[0054] exist Figure 1In this specification, the area where the transistor section 70 is arranged is marked with the symbol "I", and the area where the diode section 80 is arranged is marked with the symbol "F". In this specification, the direction perpendicular to the arrangement direction when viewed from above is sometimes referred to as the extension direction (in...). Figure 1 (The middle direction is the Y-axis direction). The transistor section 70 and the diode section 80 may each have a long side in the extending direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extending directions of the transistor section 70 and the diode section 80 may be the same as the long side direction of each trench section described later.

[0055] The diode section 80 has an N+ type cathode region in the area that is in contact with the lower surface of the semiconductor substrate 10. In this specification, the area where the cathode region is provided is referred to as the diode section 80. That is, the diode section 80 is the area that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in the area other than the cathode region. In this specification, the diode section 80 may sometimes also include an extension region 81 that extends the diode section 80 along the Y-axis direction to the gate wiring described later. A collector region is provided on the lower surface of the extension region 81.

[0056] The transistor section 70 has a P+ type collector region in the region that is in contact with the lower surface of the semiconductor substrate 10. In addition, the transistor section 70 has an N-type emitter region, a P-type base region, and a gate structure having a gate conductive portion and a gate insulating film periodically arranged on the upper surface side of the semiconductor substrate 10.

[0057] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 164. The semiconductor device 100 may also have anode pads, cathode pads, and current sensing pads, etc. Each pad is located near the edge 162. "Near the edge 162" refers to the area between the edge 162 and the emitter when viewed from above. When the semiconductor device 100 is actually mounted, each pad can be connected to an external circuit via wiring such as leads.

[0058] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes gate wiring connecting the gate pad 164 to the gate trench portion. Figure 1 In the diagram, a shading line is marked on the gate wiring.

[0059] The gate wiring in this example includes a peripheral gate wiring 130 and an active-side gate wiring 131. The peripheral gate wiring 130 is disposed between the active portion 160 and the edge 162 of the semiconductor substrate 10 in plan view. In this example, the peripheral gate wiring 130 surrounds the active portion 160 in plan view. Alternatively, the area surrounded by the peripheral gate wiring 130 in plan view can also be considered as the active portion 160. Furthermore, the peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 can be a metal wiring including aluminum, etc.

[0060] An active-side gate wiring 131 is provided in the active portion 160. Since the active-side gate wiring 131 is provided in the active portion 160, the deviation of the wiring length from the gate pad 164 can be reduced for each region of the semiconductor substrate 10.

[0061] The active-side gate wiring 131 is connected to the gate trench portion of the active portion 160. The active-side gate wiring 131 is disposed above the semiconductor substrate 10. The active-side gate wiring 131 can be a wiring formed from a semiconductor such as polysilicon doped with impurities.

[0062] The active-side gate wiring 131 can be connected to the outer peripheral gate wiring 130. In this example, the active-side gate wiring 131 extends along the X-axis direction from the outer peripheral gate wiring 130 on one side to the outer peripheral gate wiring 101 on the other side, approximately at the center in the Y-axis direction, traversing the active portion 160. When the active portion 160 is divided using the active-side gate wiring 131, the transistor portion 70 and the diode portion 80 can be alternately arranged along the X-axis direction in each divided region.

[0063] Additionally, the semiconductor device 100 may include: a temperature sensing unit (not shown) which is a PN junction diode formed of polysilicon or the like; and a current sensing unit (not shown) which simulates the operation of the transistor unit disposed in the active unit 160.

[0064] Viewed from above, the semiconductor device 100 of this example has an edge termination structure 90 between the active portion 160 and the edge 162. In this example, the edge termination structure 90 is disposed between the peripheral gate wiring 130 and the edge 162. The edge termination structure 90 alleviates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a protective ring surrounding the active portion 160 in an annular shape, a field plate, and a surface electric field reduction section.

[0065] Figure 2 yes Figure 1An enlarged view of region D is shown. Region D includes the transistor section 70, the diode section 80, and the active-side gate wiring 131. The semiconductor device 100 of this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 disposed inside the upper surface side of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are examples of trench sections. Furthermore, the semiconductor device 100 of this example includes an emitter 52 and an active-side gate wiring 131 disposed above the upper surface of the semiconductor substrate 10. The emitter 52 and the active-side gate wiring 131 are disposed separately from each other.

[0066] An interlayer insulating film is provided between the emitter 52 and the upper surface of the semiconductor substrate 10, and between the active-side gate wiring 131 and the upper surface of the semiconductor substrate 10, but in Figure 2 The details are omitted. In this example, the interlayer insulating film has contact holes 54 provided in a manner that penetrates the interlayer insulating film. Figure 2 In the middle, the shading of the diagonal lines marks each contact hole 54.

[0067] An emitter 52 is disposed above the gate trench 40, the dummy trench 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. Furthermore, the emitter 52 is connected to a dummy conductive portion within the dummy trench 30 through a contact hole disposed in the interlayer insulating film. The front end of the emitter 52 in the dummy trench 30 along the Y-axis direction can be connected to a dummy conductive portion of the dummy trench 30.

[0068] The active-side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active-side gate wiring 131 can be connected to the gate conductive portion of the gate trench portion 40 at its front end 41 in the Y-axis direction. The active-side gate wiring 131 is not connected to the dummy conductive portion within the dummy trench portion 30.

[0069] The emitter 52 is formed of a material containing metal. Figure 2 The area where the emitter 52 is disposed is shown. For example, at least a portion of the emitter 52 is formed of aluminum or an aluminum-silicon alloy, such as AlSi, AlSiCu, or other metal alloys. The emitter 52 may have a barrier metal formed of titanium or titanium compounds in the lower layer of the area formed of aluminum or the like. Furthermore, a plug formed by embedding tungsten or the like in contact with the barrier metal and the aluminum or the like may be provided within the contact hole.

[0070] The well region 11 is disposed overlapping with the active-side gate wiring 131. The well region 11 also extends with a predetermined width in a region that does not overlap with the active-side gate wiring 131. In this example, the well region 11 is separated from the active-side gate wiring 131 by its end in the Y-axis direction relative to the contact hole 54. The well region 11 is a region of a second conductivity type with a higher doping concentration than the base region 14. In this example, the base region 14 is P-type, and the well region 11 is P+ type.

[0071] Both the transistor section 70 and the diode section 80 have multiple trench sections arranged along the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately arranged along the arrangement direction. In the diode section 80 of this example, multiple dummy trench sections 30 are arranged along the arrangement direction. In the diode section 80 of this example, no gate trench section 40 is provided.

[0072] In this example, the gate trench portion 40 may have two straight portions 39 (the trench portion that is straight in the extension direction) extending in an extension direction perpendicular to the arrangement direction, and a front end portion 41 connecting the two straight portions 39. Figure 2 The direction of extension in the middle is the Y-axis direction.

[0073] Preferably, at least a portion of the front end portion 41 is curved when viewed from above. By connecting the ends of the two straight portions 39 in the Y-axis direction to each other through the front end portion 41, the electric field concentration at the ends of the straight portions 39 can be alleviated.

[0074] In the transistor section 70, dummy trench sections 30 are provided between each straight portion 39 of the gate trench section 40. One dummy trench section 30 may be provided between each straight portion 39, or multiple dummy trench sections 30 may be provided. The dummy trench section 30 may have a straight shape extending in the extending direction, or it may have the same straight portion 29 and front end portion 31 as the gate trench section 40. Figure 2 The semiconductor device 100 shown includes both a dummy trench portion 30 with a straight shape and no front end portion 31, and a dummy trench portion 30 with a front end portion 31.

[0075] The diffusion depth of the well region 11 can be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 when viewed from above. That is, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. This helps to alleviate electric field concentration at the bottom of each trench portion.

[0076] Mesa-shaped portions are provided between the trench portions in the arrangement direction. A mesa-shaped portion refers to the area within the semiconductor substrate 10 that is held between the trench portions. For example, the upper end of the mesa-shaped portion is the upper surface of the semiconductor substrate 10. The lower end of the mesa-shaped portion has the same depth as the lower end of the trench portion. In this example, the mesa-shaped portion is provided on the upper surface of the semiconductor substrate 10, extending along the trench in the extension direction (Y-axis direction). In this example, a mesa-shaped portion 60 is provided in the transistor portion 70, and a mesa-shaped portion 61 is provided in the diode portion 80. In this specification, when referred to simply as a mesa-shaped portion, the terms mesa-shaped portion 60 and mesa-shaped portion 61 are used interchangeably.

[0077] A base region 14 is provided on each mesa. The region of the base region 14 exposed on the upper surface of the semiconductor substrate 10 within the mesa, positioned closest to the active-side gate wiring 131, is designated as base region 14-e. Figure 2 Although a base region 14-e is shown disposed at one end of each stage in the extending direction, a base region 14-e is also disposed at the other end of each stage. In each stage, the area sandwiched by the base region 14-e in top view may be provided with at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be disposed between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0078] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is grounded to the gate trench portion 40. A contact region 15 exposed on the upper surface of the semiconductor substrate 10 may be provided on the mesa portion 60 that is in contact with the gate trench portion 40.

[0079] Each contact area 15 and each emission area 12 in the platform surface 60 extends from a groove on one side to a groove on the other side in the X-axis direction. As an example, the contact areas 15 and emission areas 12 of the platform surface 60 are alternately arranged along the extension direction of the groove (Y-axis direction).

[0080] In other examples, the contact area 15 and the emission area 12 of the platform 60 can be arranged in a strip shape along the extension direction (Y-axis direction) of the groove. For example, the emission area 12 is provided in the area that is in contact with the groove, and the contact area 15 is provided in the area that is held by the emission area 12.

[0081] The emitter region 12 is not provided on the mesa 61 of the diode section 80. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa 61. On the upper surface of the mesa 61, a contact region 15 may be provided in the area sandwiched between the base regions 14-e and grounded to each base region 14-e. A base region 14 may be provided on the upper surface of the mesa 61 in the area sandwiched by the contact region 15. The base region 14 may be configured throughout the entire area sandwiched by the contact region 15.

[0082] A contact hole 54 is provided above each stage surface. The contact hole 54 is located in the area held by the base region 14-e. In this example, the contact hole 54 is located above the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 is not located in the region corresponding to the base region 14-e and the sink region 11. The contact hole 54 can be located at the center of the stage surface 60 in the arrangement direction (X-axis direction).

[0083] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. On the lower surface of the semiconductor substrate 10, in a region where the cathode region 82 is not provided, a P+ type collector region 22 may be provided. The cathode region 82 and the collector region 22 are disposed between the lower surface 23 of the semiconductor substrate 10 and the buffer zone 20. Figure 2 In the diagram, a dashed line is used to represent the boundary between the cathode region 82 and the collector region 22.

[0084] The cathode region 82 is disposed separately from the well region 11 in the Y-axis direction. This ensures a sufficient distance between the cathode region 82 and the P-type region (well region 11), which has a high doping concentration and is formed deep within the well, thereby improving the breakdown voltage. In this example, the end of the cathode region 82 in the Y-axis direction is disposed further away from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In other examples, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact hole 54.

[0085] Figure 3 It is shown Figure 2 A diagram showing an example of the ee cross section. The ee cross section is the XZ plane passing through the emitter region 12 and the cathode region 82. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter 52, and a collector 24 in this cross section.

[0086] An interlayer insulating film 38 is disposed on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film comprising at least one layer of an insulating film such as silicate glass with added impurities like boron or phosphorus, a thermally oxidized film, and other insulating films. The interlayer insulating film 38 has a layer of... Figure 2 Contact hole 54 as described in the text.

[0087] The emitter 52 is disposed above the interlayer insulating film 38. The emitter 52 contacts the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The collector 24 is disposed on the lower surface 23 of the semiconductor substrate 10. The emitter 52 and the collector 24 are formed of a metallic material such as aluminum. In this specification, the direction (Z-axis direction) connecting the emitter 52 and the collector 24 is referred to as the depth direction.

[0088] The semiconductor substrate 10 has N-type or N-type drift regions 18. The drift regions 18 are respectively provided in the transistor section 70 and the diode section 80.

[0089] On the mesa 60 of the transistor section 70, an N+ type emitter region 12 and a P- type base region 14 are sequentially disposed from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is disposed below the base region 14. An N+ type accumulation region 16 may be disposed on the mesa 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0090] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is grounded to the gate trench portion 40. The emitter region 12 can be connected to the trench portions on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18.

[0091] The base region 14 is located below the transmitter region 12. In this example, the base region 14 is grounded to the transmitter region 12. The base region 14 can be connected to the grooves on both sides of the stage surface 60.

[0092] Accumulation region 16 is disposed below base region 14. Accumulation region 16 is an N+ type region with a higher doping concentration than drift region 18. Accumulation region 16 may have concentration peaks of donors such as phosphorus or hydrogen donors. By providing a high-concentration accumulation region 16 between drift region 18 and base region 14, the carrier injection promotion effect (IE effect) can be improved, and the turn-on voltage can be reduced. Accumulation region 16 may be disposed in such a way that it covers the entire lower surface of base region 14 in each mesa 60.

[0093] A P-type base region 14 is provided on the mesa 61 of the diode section 80, in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An accumulation region 16 may be provided on the mesa 61, below the base region 14.

[0094] In each transistor section 70 and each diode section 80, an N+ type buffer 20 may be provided below the drift region 18. The doping concentration of the buffer 20 is higher than that of the drift region 18. The buffer 20 may have a concentration peak with a higher doping concentration than that of the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Alternatively, the doping concentration of the drift region 18 can be the average doping concentration in a region with a roughly flat doping concentration distribution.

[0095] Buffer 20 can be formed by ion implantation of N-type dopants such as hydrogen (protons) or phosphorus. In this example, buffer 20 is formed by ion implantation of hydrogen. Buffer 20 can function as a field cutoff layer to prevent the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0096] In the transistor section 70, a P+ type collector region 22 is provided below the buffer 20. The acceptor concentration in the collector region 22 is higher than that in the base region 14. The collector region 22 may contain the same acceptors as the base region 14, or it may contain acceptors different from the base region 14. The acceptors in the collector region 22 are, for example, boron.

[0097] In the diode section 80, an N+ type cathode region 82 is provided below the buffer zone 20. The donor concentration in the cathode region 82 is higher than that in the drift region 18. The donors in the cathode region 82 are, for example, hydrogen or phosphorus. It should be noted that the elements that become donors and acceptors in each region are not limited to the examples described above. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 can contact the entire lower surface 23 of the semiconductor substrate 10. The emitter 52 and the collector electrode 24 can be formed of a metallic material such as aluminum.

[0098] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the upper surface 21 side of the semiconductor substrate 10. Each trench portion extends from the upper surface 21 of the semiconductor substrate 10, penetrates the base region 14, and reaches the drift region 18. In regions where at least one of the emitter region 12, contact region 15, and accumulation region 16 is provided, each trench portion also penetrates these doped regions and reaches the drift region 18. The trench portion penetrating the doped region is not limited to being manufactured in the order of forming the trench portion after forming the doped region. The case where doped regions are formed between the trench portions after the trench portions are formed is also included in the case where the trench portion penetrates the doped region.

[0099] As described above, the transistor section 70 is provided with a gate trench section 40 and a dummy trench section 30. The diode section 80 is provided with a dummy trench section 30, but not with a gate trench section 40. In this example, the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.

[0100] The gate trench portion 40 includes a gate trench disposed on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is disposed covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is disposed inside the gate trench, at a position further inward than the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0101] The gate conductive portion 44 may be longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. If a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface in the base region 14 that is in contact with the gate trench portion 40.

[0102] The dummy trench portion 30 can have the same structure as the gate trench portion 40 in this cross-section. The dummy trench portion 30 has a dummy trench disposed on the upper surface 21 of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy conductive portion 34 is electrically connected to the emitter 52. The dummy insulating film 32 is disposed covering the inner wall of the dummy trench. The dummy conductive portion 34 is disposed inside the dummy trench and is located further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 can be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 can be formed of a conductive material such as polysilicon. The dummy conductive portion 34 can have the same length in the depth direction as the gate conductive portion 44.

[0103] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. It should be noted that the bottom of the dummy trench portion 30 and the gate trench portion 40 can be a downwardly convex curved surface (curved in cross-section).

[0104] Figure 4 It is shown Figure 3 A diagram showing an example of the doping concentration distribution along the depth direction at the location of the FF line. Figure 4 The vertical axis is the logarithmic axis. Figure 4 In this process, the central position in the depth direction of the semiconductor substrate 10 is set as Zc.

[0105] Emitter region 12 has a concentration peak of N-type dopant. N-type dopant is, for example, phosphorus, but is not limited thereto. Base region 14 has a concentration peak of P-type dopant. P-type dopant is, for example, boron, but is not limited thereto. Accumulation region 16 has a concentration peak of N-type dopant. N-type dopant is, for example, hydrogen or phosphorus, but is not limited thereto.

[0106] The drift region 18 can have a flat region with a substantially constant doping concentration. The flat region is a continuous portion in the depth direction between a predetermined maximum doping concentration (max) and a predetermined minimum doping concentration (min). The maximum doping concentration (max) can be the highest value of the doping concentration in this region. The minimum doping concentration (min) can be 50%, 70%, or 90% of the maximum doping concentration (max).

[0107] Alternatively, for a flat region, the value of the doping concentration distribution relative to the average concentration of the doping concentration distribution within a predetermined range in the depth direction can be within ±50% of the average concentration of the doping concentration distribution, or within ±30% of the average concentration of the doping concentration distribution, or within ±10% of the average concentration of the doping concentration distribution.

[0108] In this example, the doping concentration distribution in buffer 20 has a single concentration peak 25. Buffer 20 can have multiple concentration peaks 25 located at different positions along the depth direction. When buffer 20 has multiple concentration peaks 25, in... Figure 4 The concentration peak 25, which will be described later, is the concentration peak 25 closest to the drift region 18.

[0109] In this example, concentration peak 25 is formed by injecting hydrogen ions from the lower surface 23 of the semiconductor substrate 10. That is, concentration peak 25 is the concentration peak of hydrogen donors. Hydrogen ions are injected near the apex of concentration peak 25. When hydrogen ions are injected from the lower surface 23, hydrogen is also distributed in the region from the apex of concentration peak 25 to the lower surface 23. On the other hand, almost no hydrogen is distributed in the region closer to the upper surface 21 than the apex of concentration peak 25. Therefore, the slope of the lower surface slope 27 from the apex of concentration peak 25 toward the lower surface 23 becomes gentle, and the slope of the upper surface slope 26 from the apex of concentration peak 25 toward the upper surface 21 is steeper than the lower surface slope 27.

[0110] In this example, the upper surface slope 26 is the deepest slope where the doping concentration monotonically decreases in the direction from the lower surface 23 of the semiconductor substrate 10 toward the upper surface 21, down to the position where it connects with the drift region 18. Monotonically decreasing means that the doping concentration does not increase in the direction from the lower surface 23 toward the upper surface 21. That is, at each position of the upper surface slope 26, the doping concentration is either decreased or the same compared to the adjacent position on the lower surface 23 side.

[0111] In this example, the upper surface slope 26 extends from the apex of the concentration peak 25 to the lower end of the drift region 18. The boundary between the drift region 18 and the upper surface slope 26 can be the lower end of the flat region of the drift region 18. This boundary can be a position between the upper surface slope 26 and the drift region 18 where the doping concentration is the same as the average doping concentration of the flat region of the drift region 18, or it can be a position 1.5 times that average value.

[0112] If charged particles such as hydrogen ions are irradiated onto the semiconductor substrate 10, lattice defects dominated by vacancies, such as single-atom vacancies (V) and multi-atom vacancies (VV), are formed in the regions through which the charged particles pass. In this example, lattice defects are formed in the region from the lower surface 23 of the semiconductor substrate 10 to near the peak of the concentration peak 25. Atoms adjacent to vacancies have dangling bonds. Lattice defects also include interlattice atoms, dislocations, etc., and can also broadly include donors and / or acceptors. However, in this specification, lattice defects dominated by vacancies are sometimes referred to as vacancy-type lattice defects, or simply lattice defects. In addition, by injecting charged particles into the semiconductor substrate 10, a large number of lattice defects are formed, which sometimes severely disrupts the crystallinity of the semiconductor substrate 10. In this specification, this disruption of crystallinity is sometimes referred to as disorder.

[0113] Furthermore, oxygen is present throughout the semiconductor substrate 10. This oxygen is intentionally or unintentionally introduced during the manufacture of the semiconductor ingot. Hydrogen injected into the buffer 20 diffuses due to heat treatment, etc., thereby combining hydrogen (H), vacancies (V), and oxygen (O) inside the semiconductor substrate 10 to form VOH defects.

[0114] VOH defects function as donors that supply electrons. In this specification, VOH defects are sometimes simply referred to as hydrogen donors. By forming hydrogen donors on the semiconductor substrate 10, it is possible to form a buffer zone 20 with a higher concentration than that in the drift region 18.

[0115] Figure 5 This is a graph showing an example of the distribution of doping concentration and hydrogen chemical concentration in buffer 20. Figure 5 In the diagram, the horizontal axis represents the distance (depth position) from the lower end of buffer zone 20.

[0116] Doping concentration distribution and Figure 4 The examples described are the same. Figure 5 In this context, the depth range where the upper surface side slope 26 (deepest slope) is set is defined as the first depth range 28. The lower end position of the first depth range 28 is defined as position ZD, and the upper end position is defined as position ZU. Position ZD is the position of the apex of the concentration peak 25. Position ZU is the boundary between the drift region 18 and the upper surface side slope 26.

[0117] The hydrogen chemical concentration distribution has more than one peak outside the first depth range 28. The peak closest to the lower end position ZD is designated as the lower peak 103. The apex of the lower peak 103 is located at depth position Z1. Depth position Z1 can be located between the lower end position ZD and the lower surface 23. Depth position Z1 can also be the same position as the lower end position ZD.

[0118] The hydrogen chemical concentration distribution has a first decreasing portion 121 inside the first depth range 28, where the hydrogen chemical concentration decreases toward the upper surface 21. The hydrogen chemical concentration distribution also has a second decreasing portion 122 inside the first depth range 28. The second decreasing portion 122 is located further up the upper surface 21 than the first decreasing portion 121 and is a region where the hydrogen chemical concentration monotonically decreases toward the upper surface 21. The hydrogen chemical concentration distribution has an intermediate portion 110 between the first decreasing portion 121 and the second decreasing portion 122. That is, the hydrogen chemical concentration distribution has an intermediate portion 110 at a position overlapping with the slope 26 on the upper surface side. The intermediate portion 110 is a region where the hydrogen chemical concentration distribution has an inner peak, a flat portion 114, or a turning portion 115, as described later. The hydrogen chemical concentration H2 in the intermediate portion 110 is less than the hydrogen chemical concentration H1 of the lower peak 103. The hydrogen chemical concentration H2 in the intermediate portion 110 can be the maximum value of the hydrogen chemical concentration in the intermediate portion 110. The hydrogen chemical concentration H2 can be less than half of the hydrogen chemical concentration H1, less than 40%, less than 30%, or less than 20%. The hydrogen chemical concentration H2 can be more than 5% of the hydrogen chemical concentration H1, more than 10%, or more than 20%.

[0119] Additionally, the hydrogen chemical concentration at position ZD is set as H3. The hydrogen chemical concentration H3 is greater than the hydrogen chemical concentration H2. The hydrogen chemical concentration H2 can be less than half of the hydrogen chemical concentration H3, less than 40%, less than 30%, or less than 20%. The hydrogen chemical concentration H2 can be more than 5%, more than 10%, or more than 20% of the hydrogen chemical concentration H3.

[0120] In this example, at multiple depth locations in buffer 20 (at Figure 5 Hydrogen ions are injected into locations Z1 and Z2. Buffer zone 20 has a hydrogen chemical concentration distribution obtained by summing the chemical concentration distributions of the hydrogen injected into each location. Figure 5 In this configuration, the chemical concentration distribution of hydrogen injected into position Z1 is designated as distribution 101. Additionally, the chemical concentration distribution of hydrogen injected into position Z2 is designated as distribution 102. The buffer zone 20 has a hydrogen chemical concentration distribution obtained by adding distribution 101 and distribution 102.

[0121] Without injecting hydrogen ions into position Z2, the slope of the upper surface side slope 26 of concentration peak 25 is the same as the slope of the upper surface side slope of distribution 101. In this case, the slope of the upper surface side slope 26 becomes steep. When the semiconductor device 100 is turned off, the depletion layer extends from the lower end of the base region 14 toward the buffer zone 20. At this time, if the slope of the upper surface side slope 26, which is the deepest slope, is steep, the voltage or current waveform becomes prone to oscillation when the depletion layer reaches the upper surface side slope 26.

[0122] In this example, hydrogen ions are also injected at position Z2, which is located on the upper surface 21 side, compared to position Z1. This makes the slope of the upper surface slope of the hydrogen chemical concentration distribution gentler, and also makes the slope of the upper surface slope 26 of the concentration peak 25 gentler.

[0123] It should be noted that if position Z2 is too far from position Z1, distributions 101 and 102 exist independently, thus failing to smooth the inclination of the upper surface side slope 26. Furthermore, whether the dose of hydrogen ions injected into position Z2 is too high or too low, the inclination of the upper surface side slope 26 cannot be smoothed. By bringing the distance between positions Z1 and Z2 close to the point where the hydrogen chemical concentration distribution has a middle portion 110 within the first depth range 28, and by adjusting the dose at position Z2, the inclination of the upper surface side slope 26 can be smoothed, thereby suppressing oscillations in the current waveform.

[0124] The depth length of the upper surface side slope 26 is less than 5 μm. This length can be less than 3 μm or less than 2 μm. Alternatively, it can be greater than 0.4 μm, greater than 1.0 μm, or greater than 1.5 μm. The doping concentration at the lower end of the upper surface side slope 26 can be greater than 10 times, greater than 50 times, or greater than 100 times the doping concentration of the drift region 18.

[0125] Figure 6 The distribution of doping concentration in buffer 20 of the comparative example is shown. Figure 6 The diagram shows the doping concentration distribution when a buffer zone 20 is formed by injecting phosphorus ions, and the doping concentration distribution when a buffer zone 20 is formed by injecting hydrogen ions into a single depth location.

[0126] When phosphorus is injected from the lower surface 23 and diffused, the slope of the upper surface slope 108 of the concentration peak can be made gentle. On the other hand, since no hydrogen donor is formed in the area through which phosphorus passes, it is difficult to form a high concentration region over a wide range.

[0127] When hydrogen ions are injected from the lower surface 23 to a single depth location and diffused, hydrogen donors are formed in the region through which the hydrogen ions pass, thus creating a high-concentration region from the lower surface 23 to the injection site. On the other hand, sometimes lattice defects are less abundant in regions deeper than the injection site, resulting in a lower concentration of hydrogen donors even with hydrogen diffusion. Therefore, the slope of the upper surface side slope 109 becomes steep. With a steep slope of the upper surface side slope 109, the voltage or current waveform becomes prone to oscillation when the depletion layer reaches the upper surface side slope 109. In contrast, according to... Figure 5 In the example shown, by injecting hydrogen ions into position Z1 and the nearby position Z2, the slope of the upper surface side slope 26 can be made gentler.

[0128] Figure 7 The distribution of doping concentration in buffer 20 of the comparative example is shown. In this example, buffer 20 is formed by injecting hydrogen ions into two depth positions Z1 and Z2. In this example, the distance between depth positions Z1 and Z2 is relatively large. Therefore, the doping concentration distribution of buffer 20 has concentration peaks 25 (25-1, 25-2) at depth positions Z1 and Z2, respectively. In this case, it is not possible to make the slope of the upper surface ramp 26 closest to the drift region 18 gentle.

[0129] In contrast, according to Figure 5 For example, by injecting hydrogen ions into position Z1 and the nearby position Z2, the slope of the upper surface side slope 26 can be made gentler. The distance between position Z1 and position Z2 can be more than 0.1 μm and less than 3 μm. The distance between position Z1 and position Z2 can be less than 2 μm or less than 1.5 μm. The distance between position Z1 and position Z2 can be more than 0.3 μm or more than 0.5 μm. Position Z1 can be the position of the apex of the lower peak 103. Position Z2 can be the position of the apex of the second bend 113.

[0130] Figure 8 This is a diagram illustrating an example of the hydrogen chemical concentration distribution in buffer zone 20. Figure 8 The diagram shows the hydrogen chemical concentration distribution near positions Z1 and Z2. In this example, the middle portion 110 has a first bend 112 and a second bend 113. In the hydrogen chemical concentration distribution, the first bend 112 is a downwardly convex portion, and the second bend 113 is an upwardly convex portion. The first bend 112 is disposed between position Z1 and the drift region 18. The first bend 112 is a bend different from the lower peak 103. The second bend 113 is disposed between the first bend 112 and the drift region 18. The second bend 113 is a bend different from the bend at the boundary between the drift region 18 and the buffer zone 20.

[0131] In this example, the first bend 112 is a valley where the hydrogen chemical concentration shows a minimum value of H4. The second bend 113 is a peak where the hydrogen chemical concentration shows a maximum value of H2. In this specification, the second bend 113 is sometimes referred to as an inner peak of the slope. The region from the first bend 112 to the second bend 113 can be designated as the intermediate portion 110.

[0132] Figure 9 This is another example of the hydrogen chemical concentration distribution in buffer zone 20. Figure 9 The diagram shows the hydrogen chemical concentration distribution near positions Z1 and Z2. The middle section 110 in this example... Figure 8 The example also has a first bend 112 and a second bend 113. However, the first bend 112 does not exhibit a minimum value, and the second bend 113 does not exhibit a maximum value.

[0133] In this example, the region between the first curved portion 112 and the second curved portion 113 is referred to as the flat portion 114. The flat portion 114 is a region with a uniform hydrogen chemical concentration distribution. A uniform hydrogen chemical concentration distribution means, for example, a region where the variation in hydrogen chemical concentration is less than ±10%. In the flat portion 114, the hydrogen chemical concentration distribution does not increase from the lower surface 23 toward the upper surface 21. Furthermore, when differentiating the hydrogen chemical concentration distribution from the lower surface 23 toward the upper surface 21 with depth position, the region where the differential function between the first curved portion 112 and the second curved portion 113 substantially shows 0 can also be considered as the flat portion 114. The slope of the flat portion 114 is gentler than either the hydrogen chemical concentration distribution between the flat portion 114 and position Z1, or the hydrogen chemical concentration distribution between the flat portion 114 and the drift region 18. In this example, the hydrogen chemical concentration exhibits a constant value in the flat portion 114. In addition, the slope of the flat portion 114 can be gentler than the slope of the doping concentration distribution at the same depth position as the flat portion 114.

[0134] Figure 10 This is another example of the hydrogen chemical concentration distribution in buffer zone 20. Figure 10 The diagram shows the hydrogen chemical concentration distribution near positions Z1 and Z2. The middle section 110 in this example... Figure 9 The example also has a first bend 112 and a second bend 113. In this example, the region between the first bend 112 and the second bend 113 is referred to as the transition 115. In this example, the hydrogen chemical concentration distribution of the transition 115 monotonically decreases from the lower surface 23 toward the upper surface 21. Other characteristics of the transition 115 are similar to... Figure 9 The flat portion 114 is the same. The turning portion 115 is the region where the slope of the hydrogen chemical concentration distribution is not greater than 0 and the second derivative is 0.

[0135] Figure 11This is a diagram showing an example of the full width at half maximum (FWHM) of the lower peak 103 and the second bend 113. In this example, the second bend 113 is an inner peak of the slope. Additionally, the first bend 112 is a valley.

[0136] In this example, the separation distance L1 between the full width at half maximum (FWHM1) of the lower peak 103 and the full width at half maximum (FWHM2) of the second bend 113. Distance L1 can be less than either the full width at half maximum (FWHM1) or the full width at half maximum (FWHM2).

[0137] It should be noted that when the minimum hydrogen chemical concentration H3 at the first bend 112 is greater than half the doping concentration H2 at the apex of the second bend 113, the lower end position of the full width at half maximum (FWHM2) of the second bend 113 cannot be determined. In this case, the FWHM2 of the upper side (drift region 18 side) of the second bend 113 can be measured. The size of the FWHM2 of the lower side (lower peak 103 side) of the second bend 113 can be made the same as the measured size of the FWHM2. That is, the width of the full width at half maximum (FWHM2) can be set to twice the size of the FWHM2.

[0138] The distance L1 between the full width at half maximum (FWHM1) and FWHM2 can be controlled by the positions Z1 and Z2 of the injected hydrogen ions. In this example, since the distance L1 is relatively small, Figure 5 The sum of distributions 101 and 102 shown can make the slope of the upper surface slope 26 of the concentration peak 25 gentler.

[0139] Figure 12 This is a diagram showing another example of the full width at half maximum (FWHM) of the lower peak 103 and the second bend 113. In this example, the second bend 113 is an inner peak of the slope. Additionally, the first bend 112 is a valley.

[0140] In this example, the full width at half maximum (FWHM1) of the lower peak 103 and the full width at half maximum (FWHM2) of the second curved portion 113 can be joined at their ends or partially overlap. Thus, Figure 5 The sum of distributions 101 and 102 shown can make the slope of the upper surface slope 26 of the concentration peak 25 gentler.

[0141] It should be noted that, for the lower peak 103 and the second bend 113, the apex of one peak can be positioned outside the full width at half maximum of the other peak. This prevents distribution 102 from being... Figure 5 The distribution 101 shown is buried. Therefore, the slope of the upper surface slope 26 of the concentration peak 25 can be made gentle.

[0142] exist Figures 1 to 12In either example, the distance between the lower peak 103 and the second curved portion 113 and the lower surface 23 can be 10 μm or less. This distance can be 8 μm or less, or 6 μm or less.

[0143] Figure 13 This diagram illustrates a portion of the manufacturing process of the semiconductor device 100. The manufacturing method in this example includes a top surface side structure formation step S1301 and a buffer formation step S1302. The buffer formation step S1302 includes an implantation step S1303 and a heat treatment step S1304.

[0144] In the upper surface side structure formation step S1301, a structure is formed on the upper surface 21 side of the semiconductor substrate 10. The semiconductor substrate 10 may be an N-type substrate. In this case, the area remaining without other regions is called the drift region 18. The structure on the upper surface 21 side may refer to a structure that is located on the upper surface 21 side further than the center of the depth position of the semiconductor substrate 10. The structure on the upper surface 21 side includes, for example, an emitter region 12, a base region 14, an accumulation region 16, a trench, etc. The structure on the upper surface 21 side may include various insulating films such as an interlayer insulating film 38 disposed above the upper surface 21 of the semiconductor substrate 10, and various conductive components such as an emitter 52.

[0145] In implantation step S1303, hydrogen ions are implanted from the lower surface 23 of the semiconductor substrate 10 to at least two depth positions within the region where the buffer zone 20 is to be formed. In this example, hydrogen ions are implanted to position Z1 at the lower end of a first depth range 28 that is adjacent to the drift region 18 and to a predetermined depth position Z2 within the first depth range 28.

[0146] The second dose of hydrogen ions injected into position Z2 (ions / cm) 2 The first dose (ions / cm) of hydrogen ions injected into position Z1 is less than the initial dose. 2 The second dose can be less than half, less than 40%, less than 30%, or less than 20% of the first dose. The second dose can be more than 5%, more than 10%, or more than 20% of the first dose.

[0147] Next, in heat treatment step S1304, the semiconductor substrate 10 is heat-treated. This forms hydrogen donors in the buffer zone 20, which has the ability to... Figures 4 to 12 The doping concentration distribution is described in the text.

[0148] Before the heat treatment step S1304, the lower surface 23 of the semiconductor substrate 10 can be ground to adjust the thickness of the semiconductor substrate 10. Before or after the heat treatment step S1304, the collector region 22 and the cathode region 82 can be formed. After the heat treatment step S1304, the collector electrode 24 can be formed. Through these processes, a semiconductor device 100 can be manufactured.

[0149] While the present invention has been described above using embodiments, its technical scope is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or alterations can be made to the above embodiments. As can be seen from the claims, such modifications or alterations can also be included within the technical scope of the present invention.

[0150] It should be noted that the execution order of actions, processes, steps, and stages in the apparatus, system, program, and method shown in the claims, specification, and drawings can be implemented in any order unless specifically stated as "earlier than" or "before," and unless the results of previous processes are used in subsequent processes. Even if the flow of actions in the claims, specification, and drawings is described using terms such as "firstly" or "next" for convenience, this does not mean that they must be implemented in this order.

Claims

1. A semiconductor device, characterized in that, have: A semiconductor substrate having an upper surface and a lower surface, and having a drift region of a first conductivity type; and A buffer zone of the first conductivity type is disposed between the drift region and the lower surface, and has a higher concentration than that in the drift region. The doping concentration distribution in the buffer has a deepest slope, where the doping concentration monotonically decreases from the lower surface of the semiconductor substrate toward the upper surface until it reaches the position where it connects with the drift region. The hydrogen chemical concentration distribution in the buffer zone, within the first depth range where the deepest slope is located, is as follows: The first decreasing portion has a hydrogen chemical concentration that decreases toward the upper surface side; The second reduction portion is located further along the upper surface than the first reduction portion, and the hydrogen chemical concentration is reduced; and The middle portion is positioned between the first reduced portion and the second reduced portion. The intermediate portion has: The flat portion, wherein the hydrogen chemical concentration is uniformly distributed; or The inner peak of the slope of the hydrogen chemical concentration; or The inflection point of the hydrogen chemical concentration, The first depth range includes a doping concentration reduction portion at each position in the depth direction of the semiconductor substrate, wherein the doping concentration of the doping concentration reduction portion is smaller than the doping concentration at the adjacent position on the lower surface side of the semiconductor substrate. The flat portion, the inner peak of the slope, or the turning portion is disposed in the doping concentration reduction portion.

2. The semiconductor device as claimed in claim 1, characterized in that, The length of the deepest slope in the depth direction is less than 5 μm.

3. The semiconductor device as claimed in claim 1, characterized in that, The hydrogen chemical concentration distribution in the buffer zone has the slope peak within the first depth range.

4. The semiconductor device as claimed in claim 2, characterized in that, The hydrogen chemical concentration distribution in the buffer zone has the slope peak within the first depth range.

5. The semiconductor device as claimed in claim 1, characterized in that, The hydrogen chemical concentration distribution in the buffer zone has a flat portion within the first depth range. At the same depth as the flat portion of the hydrogen chemical concentration distribution, the slope of the hydrogen chemical concentration distribution is gentler than the slope of the doping concentration distribution.

6. The semiconductor device as claimed in claim 2, characterized in that, The hydrogen chemical concentration distribution in the buffer zone has a flat portion within the first depth range. At the same depth as the flat portion of the hydrogen chemical concentration distribution, the slope of the hydrogen chemical concentration distribution is gentler than the slope of the doping concentration distribution.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, The length of the deepest slope in the depth direction of the semiconductor substrate is 0.4 μm or more.

8. The semiconductor device according to any one of claims 1 to 6, characterized in that, The hydrogen chemical concentration in the middle part of the hydrogen chemical concentration distribution is less than half of the hydrogen chemical concentration at the apex of the deepest slope.

9. The semiconductor device as claimed in claim 7, characterized in that, The hydrogen chemical concentration in the middle part of the hydrogen chemical concentration distribution is less than half of the hydrogen chemical concentration at the apex of the deepest slope.

10. The semiconductor device as claimed in claim 3, characterized in that, The hydrogen chemical concentration distribution in the buffer zone includes a lower peak outside the first depth range, and the lower peak is located at the position closest to the lower end of the first depth range. The full width of half the peak of the inner slope overlaps with the full width of half the peak of the lower end.

11. The semiconductor device as claimed in claim 4, characterized in that, The hydrogen chemical concentration distribution in the buffer zone includes a lower peak outside the first depth range, and the lower peak is located at the position closest to the lower end of the first depth range. The full width of half the peak of the inner slope overlaps with the full width of half the peak of the lower end.

12. The semiconductor device as claimed in claim 10, characterized in that, The apex of one of the inner peaks of the slope and the lower peak is positioned outside the full width of the half-peak of the other peak.

13. The semiconductor device as claimed in claim 11, characterized in that, The apex of one of the inner peaks of the slope and the lower peak is positioned outside the full width of the half-peak of the other peak.

14. The semiconductor device as claimed in claim 3, characterized in that, The hydrogen chemical concentration distribution in the buffer zone includes a lower peak outside the first depth range, and the lower peak is located at the position closest to the lower end of the first depth range. The distance between the half-peak full width of the inner peak of the slope and the half-peak full width of the lower peak is smaller than the half-peak full width of either of the two peaks.

15. The semiconductor device as claimed in claim 4, characterized in that, The hydrogen chemical concentration distribution in the buffer zone includes a lower peak outside the first depth range, and the lower peak is located at the position closest to the lower end of the first depth range. The distance between the half-peak full width of the inner peak of the slope and the half-peak full width of the lower peak is smaller than the half-peak full width of either of the two peaks.

16. The semiconductor device according to any one of claims 10 to 14, characterized in that, The distance between the apex of the inner peak of the slope and the apex of the lower peak is greater than 0.1 μm and less than 3 μm.

17. The semiconductor device according to any one of claims 10 to 15, characterized in that, The distance between the inner peak of the slope and the lower peak and the lower surface of the semiconductor substrate is less than 10 μm.

18. The semiconductor device as claimed in claim 16, characterized in that, The distance between the inner peak of the slope and the lower peak and the lower surface of the semiconductor substrate is less than 10 μm.

19. The semiconductor device according to any one of claims 1 to 6, characterized in that, The hydrogen chemical concentration distribution in the buffer zone includes a lower peak located between the lower end of the deepest slope and the lower surface of the semiconductor substrate.

20. The semiconductor device according to any one of claims 1 to 6, characterized in that, The deepest slope does not have a flat section with the same doping concentration.

21. The semiconductor device according to any one of claims 1 to 6, characterized in that, The deepest slope of the doping concentration distribution in the buffer gradually decreases in absolute value in the direction from the lower surface of the semiconductor substrate toward the upper surface.

22. The semiconductor device according to any one of claims 1 to 6, characterized in that, The hydrogen chemical concentration in the middle part of the hydrogen chemical concentration distribution is more than 10% of the hydrogen chemical concentration at the apex of the deepest slope.

23. A method for manufacturing a semiconductor device, characterized in that, The device includes a buffer formation step in which hydrogen ions are implanted from the lower surface of a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type, thereby forming a buffer zone with a concentration of the first conductivity type higher than that of the drift region between the drift region and the lower surface. The buffer formation step includes: The injection step involves injecting hydrogen ions into the lower end of a first depth range connected to the drift region and into a predetermined position within the first depth range. The heat treatment step involves heat-treating the semiconductor substrate to form the deepest slope, wherein the doping concentration of the deepest slope monotonically decreases from the lower end of a first depth range until it reaches the position where it connects with the drift region. After the heat treatment step, The first depth range includes a doping concentration reduction portion at each position in the depth direction of the semiconductor substrate, wherein the doping concentration of the doping concentration reduction portion is smaller than the doping concentration at the adjacent position on the lower surface side of the semiconductor substrate. The flat sections, sloping inner peaks, or inflection points with the same hydrogen chemical concentration distribution are arranged in the section where the doping concentration decreases.

24. The method of manufacturing a semiconductor device as claimed in claim 23, characterized in that, The length of the deepest slope formed in the heat treatment step is less than 5 μm in the depth direction.

25. The method of manufacturing a semiconductor device as claimed in claim 23, characterized in that, After the heat treatment step, the hydrogen chemical concentration distribution in the buffer zone has an in-slope peak within the first depth range.

26. The method of manufacturing a semiconductor device as claimed in claim 24, characterized in that, After the heat treatment step, the hydrogen chemical concentration distribution in the buffer zone has an in-slope peak within the first depth range.

27. The method of manufacturing a semiconductor device as claimed in claim 23, characterized in that, After the heat treatment step, The hydrogen chemical concentration distribution in the buffer zone has a flat portion with the same hydrogen chemical concentration distribution within the first depth range. At the same depth as the flat portion of the hydrogen chemical concentration distribution, the slope of the hydrogen chemical concentration distribution is gentler than that of the doping concentration distribution.

28. The method of manufacturing a semiconductor device as claimed in claim 24, characterized in that, After the heat treatment step, The hydrogen chemical concentration distribution in the buffer zone has a flat portion with the same hydrogen chemical concentration distribution within the first depth range. At the same depth as the flat portion of the hydrogen chemical concentration distribution, the slope of the hydrogen chemical concentration distribution is gentler than that of the doping concentration distribution.

29. The method of manufacturing a semiconductor device according to any one of claims 23 to 28, characterized in that, Following the heat treatment step, the hydrogen chemical concentration distribution in the buffer includes a lower peak positioned between the lower end of the deepest slope and the lower surface of the semiconductor substrate.

30. The method of manufacturing a semiconductor device according to any one of claims 23 to 28, characterized in that, In the implantation step, hydrogen ions are implanted between the lower end of the first depth range adjacent to the drift region and the lower surface of the semiconductor substrate, and at predetermined positions within the first depth range.

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