Methods for fabricating memory devices and memory devices fabricated via the methods
By employing a replacement gate architecture in a 3D vertical memory array, and utilizing the replacement of alternating dielectric material layers and sacrificial layers, the problem of selective etching was solved, enabling high-density data storage and low-cost production.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MICRON TECHNOLOGY INC
- Filing Date
- 2020-03-18
- Publication Date
- 2026-06-05
AI Technical Summary
In the manufacturing of 3D vertical memory arrays, selective etching is difficult to perform, especially when there are many vertically stacked layers of conductive and dielectric materials, which leads to increased production costs and limited memory device performance.
A replacement gate architecture is used to form a cross-point type 3D vertical memory array by forming alternating layers of two different dielectric materials on the substrate and using a sacrificial layer during the etching process, which is then replaced with a conductive material.
This technology enables high-density data storage, reduces production costs, and improves the performance of memory devices, while avoiding the etching difficulties encountered in existing technologies.
Smart Images
Figure CN115516654B_ABST
Abstract
Description
Background Technology
[0001] This invention relates to the field of electronics, and more particularly, to a method for manufacturing an electronic memory device and a memory device manufactured using said method.
[0002] Electronic storage devices (hereinafter referred to as "storage devices") are widely used to store data in various electronic devices, such as tablet computers, computers, wireless communication devices (e.g., smartphones), cameras, digital displays, and the like.
[0003] A memory device includes multiple memory cells, or a memory array, arranged as one or more memory cell arrays. Each memory cell is used to store data in the form of programmable logical states. For example, a binary memory cell can be programmed into two different logical states, often represented by a logic "1" (also known as a "SET" state) or a logic "0" (also known as a "RESET" state). In other systems, more than two logical states can be stored. To access the stored data, modules / units of the electronic device can read or sense the stored logical states in the memory device. To store data, modules / units of the electronic device can write to or program the logical states in the memory device.
[0004] Memory devices can be non-volatile or volatile. Non-volatile memory devices include memory cells that can retain stored data by maintaining the programmed logic state of the stored data over an extended period of time, even without external power. Volatile memory devices include memory cells that may lose their stored data over time unless periodically refreshed by an external power source.
[0005] Several types of non-volatile memory devices are known in this field, including, but not exhaustively, read-only memory devices, flash memory devices, ferroelectric random access memory (RAM) devices, magnetic memory devices (e.g., hard disk drives), optical memory devices (e.g., CD-ROM disks, DVD-ROM disks, Blu-ray disks), phase-change memory devices (PCM), and other chalcogenide-based memories.
[0006] A memory device with a vertical three-dimensional (3D) architecture is known, comprising a 3D vertical memory array, which in turn comprises multiple (e.g., 64) two-dimensional (2D) memory arrays (also referred to as “memory stacks”) stacked vertically on top of each other to form memory cells corresponding to multiple stacked levels. Attached Figure Description
[0007] Figure 1An example of a portion of a 3D vertical memory array 100 according to an embodiment of the present disclosure is described;
[0008] Figure 2A , 2B Description of embodiments of the present disclosure for manufacturing corresponding Figure 1 The first stage of the method for constructing a 3D vertical memory array 100;
[0009] Figure 3A , 3B Description of embodiments of the present disclosure for manufacturing corresponding Figure 1 The second stage of the method for constructing a 3D vertical memory array 100;
[0010] Figure 4A , 4B Description of embodiments of the present disclosure for manufacturing corresponding Figure 1 The third stage of the method for constructing a 3D vertical memory array 100;
[0011] Figures 5A to 5C Description of embodiments of the present disclosure for manufacturing corresponding Figure 1 The fourth stage of the method for constructing a 3D vertical memory array 100;
[0012] Figure 6A , 6B Description of embodiments of the present disclosure for manufacturing corresponding Figure 1 The fifth stage of the method for constructing a 3D vertical memory array 100;
[0013] Figures 7A to 7C Description of embodiments of the present disclosure for manufacturing corresponding Figure 1 The sixth stage of the method for constructing a 3D vertical memory array 100;
[0014] Figures 8A to 8C Description of embodiments of the present disclosure for manufacturing corresponding Figure 1 The seventh stage of the method for constructing a 3D vertical memory array 100;
[0015] Figure 9A , 9B Description of embodiments of the present disclosure for manufacturing corresponding Figure 1 The eighth stage of the method for constructing a 3D vertical memory array 100;
[0016] Figure 10A , 10B Description of embodiments of the present disclosure for manufacturing corresponding Figure 1 The ninth stage of the method for constructing a 3D vertical memory array 100;
[0017] Figure 11A , 11B Description of embodiments of the present disclosure for manufacturing corresponding Figure 1 The tenth stage of the method for constructing a 3D vertical memory array 100;
[0018] Figure 12 Description of embodiments of the present disclosure for manufacturing corresponding Figure 1 The eleventh stage of the method for constructing a 3D vertical memory array 100;
[0019] Figure 13 The description corresponds to the embodiments of this disclosure. Figure 1 A portion of the 3D vertical memory array 100;
[0020] Figure 14 The description corresponds to the embodiments of this disclosure. Figure 1 The access portion of the 3D vertical memory array 100, and
[0021] Figure 15 Description of the manufacturing process according to embodiments of the present disclosure Figure 14 The access method phase, and
[0022] Figure 16 A diagram illustrating the steps of the method disclosed herein. Detailed Implementation
[0023] In the following detailed description, reference is made to the accompanying drawings, which form part of this document and illustrate specific embodiments by means of illustration. In the drawings, similar reference numerals are used throughout several views to describe substantially similar components. Other embodiments may be disclosed and structural, logical, and electrical changes may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be viewed in a limiting sense.
[0024] This disclosure relates to a method for manufacturing an electronic memory device and a memory device manufactured using the method.
[0025] The memory device disclosed herein is a non-volatile memory device. For example, a 3D vertical memory array has been implemented as individual dies using a specific photolithography process.
[0026] In some instances, a 3D memory array may comprise a substrate having multiple contacts arranged in a pattern (e.g., a geometric pattern) and a first insulating material (e.g., a dielectric material) formed on the substrate. Multiple planes of a conductive material may be separated from each other by a second insulating material (e.g., a dielectric material) and formed on the substrate material. The planes of the conductive material may be examples of word lines.
[0027] The cross-point memory array is a 3D vertical memory array having memory cells formed at the topological cross-point between a first conductive access line (e.g., a word line) and a second conductive access line (e.g., a digital line).
[0028] Compared to 2D architecture, this 3D architecture allows for a significant increase in the number of memory cells that can be placed or formed on a single die or substrate.
[0029] This 3D architecture can therefore reduce production costs or increase the performance of memory devices, or both.
[0030] Crosspoint memory arrays can be fabricated by forming a stack of alternating layers of conductive material (e.g., tungsten or molybdenum) and dielectric / insulating material (e.g., silicon dioxide) on a substrate having multiple contacts. Multiple vertically stacked 2D memory arrays are formed, each associated with a corresponding conductive material layer. For each 2D memory array, a first access line (e.g., a word line) is formed from the associated conductive material layer, and memory cell data storage elements (e.g., phase change material elements) are formed to contact the first access line. A second access line (e.g., a digital line) is formed in the form of a conductive pillar, vertically spanning the alternating layers of conductive and dielectric materials up to the contacts on the substrate. Therefore, the memory cells (storage elements) of the 2D memory array can be accessed (e.g., programmed or read from their logical state) via the first access line (word line) obtained from the associated conductive material layer and via the second access line (e.g., digital line) corresponding to the conductive pillar.
[0031] To form this 3D vertically arranged first access line, memory element, and conductive pillar, the manufacturing process requires forming a stack of alternating layers of conductive and dielectric materials up to trenches on the substrate. To form these trenches, selective etching operations are performed to selectively remove portions of the stack of alternating layers of conductive and dielectric materials up to the substrate.
[0032] However, as the number of vertically stacked layers of conductive and dielectric materials increases (e.g., exceeding 64), the aforementioned selective etching operation becomes more difficult to perform. In fact, etching a portion of a layer of conductive material, such as tungsten or molybdenum, requires applying etchant over a non-negligible amount of time. When the number of vertically stacked layers is too high, the mask used for the selective etching operation may be consumed before the trench is fully formed.
[0033] Other conductive materials that can be easily etched, such as polysilicon used in floating-gate NAND memory technology, can be used as conductive layers for forming cross-point type 3D vertical memory arrays. However, their higher resistivity makes the memory devices susceptible to adverse increases in latency.
[0034] Solutions for fabricating vertical 3D NAND memory devices based on a so-called Replacement Gate architecture attempt to address this drawback by forming a stack of alternating layers of two different dielectric (insulating) materials (e.g., silicon dioxide and silicon nitride) on a substrate, rather than a stack of alternating layers of conductive and dielectric materials. According to this solution, the layer formed in one of the dielectric materials (e.g., silicon nitride) serves as a sacrificial layer, intended to be replaced by a conductive material layer at a later time.
[0035] Next, trenches are created in the stacked layers of the two dielectric materials by etching, forming memory cells and conductive pillars. Then, multiple slits are etched through the stacked layers of the two dielectric materials, for example, one slit for every four conductive pillars, and an etchant is applied through the open slits to selectively remove the sacrificial layer. The slits are then used to fill the empty spaces left by the removed sacrificial layer with a conductive material (e.g., tungsten) to be used to form the word lines.
[0036] The method described above for manufacturing vertical 3D NAND memory devices based on a replacement gate architecture is hampered by the need to form dedicated slits for removing the sacrificial layer, which disadvantageously increases the footprint of the resulting memory device. Furthermore, this method is not suitable for manufacturing cross-point type 3D vertical memory arrays because it requires replacing the sacrificial layer with conductive material only after the conductive pillars and memory cells have been formed.
[0037] In view of the foregoing, the applicant has devised a solution for manufacturing a memory device comprising a 3D vertical memory array, specifically a cross-type 3D vertical memory array which is not affected by the drawbacks of solutions known in the art.
[0038] By using specific reference schemata, all of which share the same reference frame identified by three orthogonal directions x, y, and z, Figure 1This describes an example of a portion of a 3D vertical memory array 100 according to an embodiment of the present disclosure. The 3D vertical memory array 100 includes one or more (preferably more) 2D arrays (or stacks) 105(i) (i = 1, 2, ...) of memory cells, which are stacked on top of each other in a direction parallel to the z direction over a substrate 104 (e.g., made of or comprising a dielectric material) extending parallel to directions x and y. Figure 1 In the exemplary 3D vertical memory array 100 portion described herein, only three stacks of memory cells are visible, namely the general stack 105(i) and two adjacent stacks 105(i-1) and 105(i+1), wherein stack 105(i-1) is below stack 105(i) and stack 105(i+1) is above stack 105(i).
[0039] The 3D vertical memory array 100 includes an associated word line 110(i) for each stack 105(i), which extends substantially parallel to the substrate 104 at a corresponding distance (along the z-direction) relative to the substrate 104. For example, word line 110(i+1) is associated with stack 105(i+1) and word line 110(i-1) is associated with stack 105(i-1).
[0040] The 3D vertical memory array 100 also includes digital lines 115 in the form of conductive pillars (only one is depicted in the figure), which extend substantially perpendicular to the substrate 104 (i.e., along the z direction).
[0041] The memory cells of stack 105(i) may include self-selecting memory cells.
[0042] Each memory cell of each stack 105(i) includes a data storage element 125(i) made of or comprising a storage element material, such as a chalcogenide material, such as a chalcogenide alloy and / or glass, which can serve as a self-selecting data storage element material, that is, a material that can serve as a selection device and a data storage element.
[0043] The architecture of the 3D vertical memory array 100 can be referred to as a crosspoint architecture, wherein memory cells are formed at topological intersections between word lines 110(i) and digital lines 115, wherein general-purpose data storage elements 125(i) contact the corresponding word lines 110(i) associated with the stack 105(i) and the corresponding digital lines 115. This crosspoint architecture can provide relatively high-density data storage with lower manufacturing costs compared to other memory architectures. For example, the crosspoint architecture can have memory cells with a reduced area and therefore a higher memory cell density compared to other architectures.
[0044] According to this architecture, memory cells belonging to general stack 105(i) are vertically stacked (along direction z) above the memory cells of the bottom stack 105(i-1). A data storage element 125(i) is located above a data storage element 125(i-1) and electrically insulated from the data storage element 125(i-1) by means of a dielectric (insulating) material portion 128(i), which is located between the data storage elements 125(i) and 125(i-1). A data storage element 125(i+1) may be located between dielectric (insulating) material portions 128(i+2) and 128(i+1). A data storage element 125(i-1) may be located between dielectric (insulating) material portions 128(i) and 128(i-1).
[0045] Substrate 104 may include a plurality of contacts arranged in a grid or staggered pattern. Figure 1 (Not visible in the image). For example, multiple contacts may extend through the substrate 104 and couple to the access lines (e.g., digital lines 115) of the memory array 100.
[0046] The memory cell can be accessed via selected word line 110(i) and selected digital line 115 to receive program and / or read pulses.
[0047] The general-purpose data storage element 125(i) can respond to an applied voltage, such as a program pulse. For an applied voltage less than a threshold voltage, the data storage element 125(i) can remain in a non-conductive state, such as corresponding to a "reset" state (or logic "0"). In response to an applied voltage greater than the threshold voltage, the data storage element 125(i) can enter a conductive state, such as corresponding to a "set" state (or logic "1").
[0048] Data storage element 125(i) can be programmed to a target logic state by applying a pulse (e.g., a program pulse) that satisfies a programming threshold. The amplitude, shape, or other characteristics of the program pulse can be configured to cause data storage element 125(i) to exhibit the target logic state. For example, after applying a program pulse, ions in data storage element 125(i) can be redistributed throughout data storage element 125(i), thereby changing the resistance of the memory cell detected when a read pulse is applied. In some cases, the threshold voltage of data storage element 125(i) can vary based on the applied program pulse. In other embodiments, data storage element 125(i) can be programmed to a target logic state by applying one or more pulses of positive or negative polarity to selected word line 110(i) and bit line (115).
[0049] The logic state stored in the data storage element 125(i) can be sensed, detected, or read by applying a read pulse to the storage element 125(i). The amplitude, shape, or other characteristics of the read pulse can be configured to allow the sensing component to determine what logic state is stored in the data storage element 125(i). For example, in some cases, the amplitude of the read pulse is configured to be at a level where the data storage element 125(i) will conduct (e.g., current conducts through the material) for a first logic state, such as a "set" state (or logic "1"), but will not conduct (e.g., very little to no current conducts through the material) for a second logic state, such as a "reset" state (or logic "0").
[0050] In some cases, the polarity of the pulse (whether a program pulse or a read pulse) applied to the data storage element 125(i) can affect the outcome of the operation being performed. For example, a read pulse of first polarity may cause the data storage element 125(i) to present a first logic state, while a read pulse of second polarity may cause the data storage element 125(i) to present a different second logic state. This can occur due to the asymmetric distribution of ions or other materials in the data storage element 125. A similar principle applies to program pulses and other pulses or voltages.
[0051] Examples of chalcogenide materials that can serve as data storage elements 125(i) include indium (In)-antimony (Sb)-tellurium (Te) (IST) materials, such as In2Sb2Te5, In1Sb2Te4, In1Sb4Te7, etc., and germanium (Ge)-antimony (Sb)-tellurium (Te) (GST) materials, such as Ge8Sb5Te8, Ge2Sb2Te5, Ge1Sb2Te4, Ge1Sb4Te7, Ge4Sb4Te7, etc., or other chalcogenide materials, including, for example, alloys that do not change phase during operation (e.g., selenium-based chalcogenide alloys). Furthermore, the chalcogenide materials may contain very low concentrations of other dopant materials. Other examples of chalcogenide materials may include tellurium-arsenic (As)-germanium (OTS) materials, Ge, Sb, Te, silicon (Si), nickel (Ni), gallium (Ga), As, silver (Ag), tin (Sn), gold (Au), lead (Pb), bismuth (Bi), indium (In), selenium (Se), oxygen (O), sulfur (S), nitrogen (N), carbon (C), yttrium (Y), and scandium (Sc), and combinations thereof. As used herein, hyphenated chemical composition designations indicate elements contained in a particular mixture or compound and are intended to represent all stoichiometry involving the indicated element. In some instances, chalcogenide materials may be chalcogenide glasses or amorphous chalcogenide materials. In some instances, chalcogenide materials primarily containing selenium (Se), arsenic (As), and germanium (Ge) may be referred to as SAG alloys.
[0052] In some instances, SAG alloys may contain silicon (Si), and such chalcogenide materials may be referred to as SiSAG alloys. In some instances, chalcogenide glasses may contain additional elements, each in atomic or molecular form, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F). In some instances, conductivity can be controlled by doping with various chemical species. For example, doping may involve incorporating Group 3 elements (e.g., boron (B), gallium (Ga), indium (In), aluminum (Al), etc.) or Group 4 elements (tin (Sn), carbon (C), silicon (Si), etc.) into the composition.
[0053] Now through reference Figure 2A , 2B The numbers 3A, 3B, 4A, 4B, 5A to 5C, 6A, 6B, 7A to 7C, 8A to 8C, 9A, 9B, 10A, 10B, 11A, 11B, and 12 describe the methods for manufacturing corresponding to embodiments of the present disclosure. Figure 1 A method for constructing a 3D vertical memory array 100.
[0054] Figure 2A and 2B The first stage of the manufacturing method according to the embodiment is described, wherein Figure 2A This is a bottom view of a partially fabricated 3D vertical memory array, obtained from a plane parallel to directions x and y. Figure 2B This is a side view of the same array taken from a plane parallel to directions x and z.
[0055] Figure 2A and 2B The steps of the method described herein include providing a substrate 104 made of or including a dielectric material, and forming a plurality of conductive contacts 202 extending through the substrate 104.
[0056] According to one embodiment, each conductive contact 202 is configured to contact a corresponding digital line (see, for example, via a selector transistor (not shown)). Figure 1 Multiple conductive contacts 202 can be arranged according to a grid pattern. For example, a conductive contact 202 can be surrounded by up to eight other conductive contacts 202. According to other embodiments not described, the multiple conductive contacts 202 can be arranged in an interlaced pattern or a hexagonal pattern.
[0057] According to one embodiment, this stage of the method further includes forming a stack of alternating layers of two different dielectric (insulating) materials on a substrate 104, the alternating layers including a first dielectric material layer 204 and a second dielectric material layer 206. According to one embodiment, the first dielectric material layer 204 includes a silicon dioxide layer, and the second dielectric material layer 206 includes a silicon nitride layer. Each first dielectric material layer 204 and second dielectric layer 206 is located at a different level relative to the substrate 104 (i.e., at different distances along direction z).
[0058] According to embodiments of the present disclosure, the first dielectric material layer 204 and the second dielectric material layer 206 are formed by a series of deposition operations.
[0059] Although the figures illustrate seven first dielectric material layers 204 and six second dielectric material layers 206, it should be understood that the concepts of embodiments of this disclosure can be applied to different (e.g., higher) numbers of layers, such as 64.
[0060] As will be described in more detail below, according to embodiments of this disclosure, a first dielectric material layer 204 will be used in the completed 3D vertical memory array 100 (see [link]). Figure 1 Dielectric material portions 128(i) are generated between the data storage elements 125(i) and 125(i-1) of the memory cells in adjacent stacks 105(i) and 105(i-1).
[0061] As will be described in more detail below, according to one embodiment, the second dielectric layer 206 is a sacrificial layer that is to be replaced in a subsequent method stage by a layer of conductive material to be used to form word lines 110(i) associated with the stack 105(i) of the completed 3D vertical memory array 100.
[0062] Figure 3A and 3B The following describes the next stage of the manufacturing method according to embodiments of the present disclosure, wherein... Figure 3A This is a cross-sectional view of an intermediate (i.e., partially fabricated) 3D vertical memory array obtained from a cross-sectional plane A-A' parallel to directions x and y and spanning the second dielectric material layer 206. Figure 3B A cross-sectional view of a portion of the same array obtained from a cross-sectional plane B-B' that is parallel to directions y and z and spans three conductive contacts 202.
[0063] Figure 3A and 3B The steps of the method described herein include forming a trench 305 through alternating first dielectric material layer 204 and second dielectric material layer 206 until the underlying substrate 104 and conductive contact 202 are exposed.
[0064] According to embodiments of this disclosure, trench 305 is formed by means of a selective etching operation utilizing a suitable patterned mask (not shown).
[0065] Since both the first dielectric layer 204 and the second dielectric layer 206 are made of or include dielectric materials such as silicon dioxide and silicon nitride (which are easier to etch than conductive materials such as tungsten or molybdenum), selective etching operations can be appropriately performed even when the number of the first dielectric layer 204 and the second dielectric layer 206 is large. In fact, the etching operation can be performed in a relatively fast and efficient manner, and the underlying substrate 104 can be advantageously exposed before the mask used for the selective etching operation is consumed. As mentioned above, if it is necessary to etch a large number of conductive material (e.g., molybdenum or tungsten) layers, the mask used for the etching operation will be consumed before the etching reaches the underlying substrate 104.
[0066] According to an embodiment of this disclosure, when viewed from above, the trench 305 has a spiral shape. According to an embodiment of this disclosure, the trench 305 may traverse a row of conductive contacts 202 in a first direction (e.g., parallel to direction x, from left to right), and then traverse an adjacent row of conductive contacts 202 in a second direction opposite to the first direction (e.g., parallel to direction x, from right to left). Reference Figure 3A The groove 305 passes the first row of conductive contacts 202 from left to right, parallel to the x direction, then "turns" and passes the next (second) row of conductive contacts 202 from right to left, parallel to the x direction (adjacent to the first row of conductive contacts 202 along the y direction). The groove 305 then "turns" again and passes the next (third) row of conductive contacts 202 from left to right, parallel to the x direction (adjacent to the second row of conductive contacts 202 along the y direction), and so on.
[0067] The trench 305 is arranged to divide each first dielectric material layer 204 and second dielectric material layer 206 into at least two portions: first portions 204(a), 206(a) and second portions 204(b), 206(b). Figure 3A Only portions 206(a) and 206(b) are visible in the image. As will be described in detail below, according to embodiments of the present disclosure, each (independent) portion 206(a) and 206(b) of the second dielectric material layer 206 is replaced by a corresponding conductive material portion having the same shape, and forms interleaved word lines 110(i) (e.g., even number lines 110(i) and odd number lines 110(i)) associated with the corresponding stack 105(i) of the completed 3D vertical memory array 100.
[0068] Figure 4A and 4B The following describes the next stage of the manufacturing method according to embodiments of the present disclosure, wherein... Figure 4AThis is a cross-sectional view of an intermediate (i.e., partially fabricated) 3D vertical memory array obtained from a cross-sectional plane A-A' parallel to directions x and y and spanning the second dielectric material layer 206. Figure 4B A cross-sectional view of a portion of the same array obtained from a cross-sectional plane B-B' that is parallel to directions y and z and spans three conductive contacts 202.
[0069] Figure 4A and 4B The steps of the method described herein include completely filling (e.g., via a deposition process) trench 305 with dielectric material 405 (e.g., the same dielectric material as substrate 104) until the top dielectric material layer 204 is reached and a capping layer 410 covering the top dielectric material layer 204 is formed.
[0070] Figure 5A , 5B The next stage of the manufacturing method according to an embodiment of the present disclosure is described in section 5C, wherein... Figure 5A This is a cross-sectional view of the intermediate (i.e., partially fabricated) 3D vertical memory array obtained from the cross-sectional plane A-A'. Figure 5B This is a cross-sectional view of a portion of the same array obtained from cross-sectional plane B-B', and Figure 5C A cross-sectional view of a portion of the same array obtained from a cross-sectional plane C-C' that is parallel to the cross-sectional plane B-B' and displaced along the direction x so as to be located between pairs of adjacent conductive contacts 202.
[0071] Figures 5A to 5C The method described herein includes the formation of a corresponding perforated trench 505 for each conductive contact 202, which extends along the z-direction through the top cover layer 410 and the dielectric material 405 within a spiral trench 305 until the conductive contact 202 is exposed. These perforated trenches 505 will be used to define the conductive posts that form the digital lines 115.
[0072] According to an embodiment of the present disclosure, the formation of the perforated trench 505 is carried out by means of a selective vertical etching operation, which involves etching only the spiral trench and a portion of the dielectric material 405 inside the capping layer 410, without eroding the dielectric material forming the first dielectric material layer 204 and the second dielectric material layer 206.
[0073] Figure 6A and 6B The following describes the next stage of the manufacturing method according to embodiments of the present disclosure, wherein... Figure 6A This is a cross-sectional view of a portion of the intermediate (i.e., partially fabricated) 3D vertical memory array obtained from cross-sectional plane B-B', and Figure 6B This is a cross-sectional view of a portion of the same array obtained from the cross-sectional plane C-C'.
[0074] Figure 6A and 6B The method described herein provides a stage to utilize the previously generated perforated trench 505 (which will subsequently be used to generate conductive pillars corresponding to digital lines 115) to provide access to all stacked first dielectric layers 204 and second dielectric layers 206 from a large number of different points across the array.
[0075] According to an embodiment of the present disclosure, the dielectric material of the second dielectric material layer 206 is removed using a perforated trench 505.
[0076] According to embodiments of the present disclosure, an isotropic etching operation is performed to selectively remove the dielectric material of the second dielectric layer 206. According to embodiments of the present disclosure, an etchant is provided via a perforated trench 505, configured to selectively remove the dielectric material (e.g., silicon nitride) of the second dielectric layer 206 without etching the dielectric material of the first dielectric layer 204. Because the perforated trench 505 is distributed across the 3D array structure in a high number and high density (e.g., per 60 nm), the etchant can easily reach all (i.e., at any depth along direction z) of the second dielectric layer 206 and propagate along directions x and y between adjacent first dielectric layers 204, simultaneously etching and removing the second dielectric layer 206. In this manner, according to this embodiment of the present disclosure, the second dielectric layer 206 can be effectively removed.
[0077] The resulting layered arrangement, in which the emptied cavity 605 is formed between adjacent first dielectric material layers 204, is mechanically supported by a dielectric material structure including a helical trench 305, a capping layer 410, and a substrate 104.
[0078] Figure 7A , 7B The next stage of the manufacturing method according to an embodiment of the present disclosure is described in section 7C, wherein... Figure 7A This is a cross-sectional view of the intermediate (i.e., partially fabricated) 3D vertical memory array obtained from the cross-sectional plane A-A'. Figure 7B This is a cross-sectional view of a portion of the same array obtained from cross-sectional plane B-B', and Figure 7C This is a cross-sectional view of a portion of the same array obtained from the cross-sectional plane C-C'.
[0079] Figure 7A , 7BThe method described in 7C provides a stage for reusing the perforated trenches 505, this time for accessing cavities 605 and filling the cavities 605 with a conductive material such as tungsten or molybdenum (e.g., by means of a deposition process) to form corresponding conductive material layers 705 between the first dielectric material layers 204. During this stage, the bottom and sides of each perforated trench 505 are also covered with conductive material. The conductive material layers 705 will be used to form word lines 110(i) associated with the stacks 105(i) of the completed 3D vertical memory array 100.
[0080] Similarly, since the perforated trenches 505 are distributed in a high number and high density across the 3D array structure, the conductive material can easily reach all (i.e., at any depth along direction z) cavities 605 and propagate along directions x and y. In this way, according to this embodiment of the present disclosure, cavities 605 can be effectively filled, and a conductive material layer 705 can be generated in a highly efficient manner.
[0081] Due to the dielectric material 405 of the spiral trench 305, each conductive material layer 705 is divided into a first conductive material portion 705(a) and a second conductive material portion 705(b). According to embodiments of the present disclosure, the (independent) portions 705(a) and 705(b) of each conductive material layer 705 will form interleaved word lines 110(i) associated with the corresponding stack 105(i) of the completed 3D vertical memory array 100 (e.g., portion 705(a) for odd number lines 110(i) and portion 705(b) for even number lines 110(i)).
[0082] Figure 8A , 8B And 8C describes the next stage of the manufacturing method according to an embodiment of the present disclosure, wherein Figure 8A This is a cross-sectional view of the intermediate (i.e., partially fabricated) 3D vertical memory array obtained from the cross-sectional plane A-A'. Figure 8B This is a cross-sectional view of a portion of the same array obtained from cross-sectional plane B-B', and Figure 8C This is a cross-sectional view of a portion of the same array obtained from the cross-sectional plane C-C'.
[0083] Figure 8A , 8B The manufacturing method described in 8C provides a stage for forming a plurality of notches 805 in each conductive material layer 705 at the perforated trench 505. For example, each notch 805 is formed facing the corresponding perforated trench 505.
[0084] According to embodiments of the present disclosure, the notch 805 is formed by an etching operation performed in an isotropic manner on the sidewall of the perforated trench 505.
[0085] The notches 805 are formed in such a way that the sidewalls of the general-purpose perforated trench 505 are spaced apart from each other by a first distance d1 along the direction x (between portions of the first dielectric material layers 204 facing each other in the perforated trench 505), and the pairs of facing notches 805 at the perforated trench 505 include sidewalls spaced apart from each other by a second distance d2 along the direction x above the first distance d1 (see...). Figure 8B ).
[0086] As will be described below, notch 805 will be used to form data storage element 125(i) of memory cell of completed 3D vertical memory array 100.
[0087] Figure 9A and 9B The following describes the next stage of the manufacturing method according to embodiments of the present disclosure, wherein... Figure 9A This is a cross-sectional view of the intermediate (i.e., partially fabricated) 3D vertical memory array obtained from the cross-sectional plane A-A', and Figure 9B This is a cross-sectional view of a portion of the same array obtained from the cross-sectional plane B-B'.
[0088] Figure 9A and 9B The manufacturing method described herein includes a stage in which a chalcogenide material 905, such as a chalcogenide alloy and / or glass, is conformally deposited into a porous trench 505 (e.g., conformal deposition in the sidewall direction). The chalcogenide material 905 is deposited in such a manner that it covers the bottom and sidewalls of the porous trench 505, thereby filling the recesses 805 formed in the conductive material layer 705. In this manner, the chalcogenide material 905 contacts the conductive material layer 705 (parts 705(a) and 705(b)).
[0089] Figure 10A and 10B The following describes the next stage of the manufacturing method according to embodiments of the present disclosure, wherein... Figure 10A This is a cross-sectional view of the intermediate (i.e., partially fabricated) 3D vertical memory array obtained from the cross-sectional plane A-A', and Figure 10B This is a cross-sectional view of a portion of the same array obtained from the cross-sectional plane B-B'.
[0090] Figure 10A and 10B The manufacturing method described herein provides a stage for performing a selective etching operation, which involves removing excess portions of the chalcogenide material 905 deposited in the porous trench 505, such that the remaining portion of the chalcogenide material 905 forms the data storage element 125(i) of the memory cell of the completed 3D vertical memory array 100.
[0091] According to an embodiment of this disclosure, the etching operation is performed such that the side surface of the data storage element 125(i) (i.e., the surface facing the perforated trench 505) is substantially coplanar with the surface of the portion of the first dielectric material layer 204 facing the perforated trench 505, and is spaced apart from each other by the same distance d1 along the direction y (see...). Figure 10B ).
[0092] In each notch 805, a corresponding storage element 125(i) is thus formed, the corresponding storage element 125(i) (see...) Figure 10B ):
[0093] -The corresponding portion 705(a) or 705(b) of the conductive material layer 705 is in contact with the conductive material layer 705 along the y direction, and
[0094] - Contact two corresponding portions of the two first dielectric material layers 204 along the z direction.
[0095] refer to Figure 10B as well as Figure 1 (The latter describes a portion of the completed 3D vertical memory array 100), portions 705(a) or 705(b) of the general memory element 125(i) of the contact stack 105(i) of the conductive material layer 705 correspond to the corresponding word line 110(i) for accessing the memory element 125(i), while the two portions of the contact general memory element 125(i) of the two first dielectric material layers 204 correspond to dielectric material portions 128(i) and 128(i+1), which allow the memory element 125(i) to be electrically insulated from the memory elements 125(i+1) and 125(i-1) belonging to the adjacent stacks 105(i+1), 105(i-1).
[0096] The etching operation at this stage is also carried out by removing the chalcogenide material 905 from the bottom of the perforated trench 505 to expose the conductive contact 202.
[0097] Figure 11A and 11B The following describes the next stage of the manufacturing method according to embodiments of the present disclosure, wherein... Figure 11A This is a cross-sectional view of the intermediate (i.e., partially fabricated) 3D vertical memory array obtained from the cross-sectional plane A-A', and Figure 11B This is a cross-sectional view of a portion of the same array obtained from the cross-sectional plane B-B'.
[0098] Figure 11A and 11B The manufacturing method described herein includes a stage in which a conductive material is used to fill the hole-shaped trench 505 to form conductive pillars, such as conductive pillar 1005 and conductive pillar 1005', that extend along the z-direction and contact the storage element 125(i).
[0099] According to embodiments of this disclosure, the conductive material of the conductive pillar 1005 is deposited using a conformal deposition operation in the sidewall direction. In this particular case, the conductive material must be compatible with the conformal deposition operation in the sidewall direction.
[0100] According to this embodiment, the conductive material of the conductive pillar 1005 can be the same as the conductive material used to generate the conductive material layer 705, as long as these conductive materials are compatible with the conformal deposition operation in the sidewall direction.
[0101] The 3D vertical memory array 100 completed according to embodiments of this disclosure is then obtained by covering open trenches 305 in the top cap layer 410 with the same dielectric material so as to also cover the conductive pillars 1005, as obtained from the cross-sectional plane B-B'. Figure 12 As shown in the cross-sectional view described herein.
[0102] Compared to 3D vertical memory arrays obtained using known methods, 3D vertical memory arrays that can be manufactured using the manufacturing method described herein according to embodiments of the present disclosure are more compact, thus requiring less space. In particular, higher memory cell density is achieved compared to the known methods mentioned above for manufacturing vertical 3D NAND memory devices based on replacement gate architectures. In fact, while known methods for manufacturing vertical 3D NAND memory devices based on replacement gate architectures result in wasted space due to the forced presence of numerous dedicated slits (e.g., every four conductive pillars) for removing the sacrificial layer, the manufacturing method according to embodiments of the present disclosure also advantageously utilizes perforated trenches (for generating conductive pillars) for replacing the sacrificial layer with a conductive layer corresponding to the word line.
[0103] Furthermore, the manufacturing method described herein according to embodiments of this disclosure is particularly suitable for manufacturing cross-point type 3D vertical memory arrays, as it provides the means to replace the sacrificial layer with a conductive material layer before forming the memory elements and conductive pillars.
[0104] according to Figure 13 The embodiments of this disclosure described herein can address compatibility issues between the chalcogenide material of the storage element 125(i) and the conductive material of the conductive material layer 705 and / or the conductive pillar 1005, thereby mitigating the barrier ( Figure 13 (Identified by reference numeral 1305) is inserted between the conductive material layer 705 and the storage element 125(i), and / or can block ( Figure 13 (Identified by reference numeral 1310) is inserted between conductive post 1005 and storage element 125(i) to avoid cross-contamination between materials.
[0105] As mentioned above, the manufacturing method described herein according to embodiments of the present disclosure is based on replacing the sacrificial dielectric layer (first dielectric layer 204) with a conductive material layer (conductive material layer 705), thereby utilizing a perforated trench 505, which is necessary for forming conductive pillars 1005 corresponding to digital lines 115 in the active portion of the memory array (i.e., the portion where the memory cells are located).
[0106] However, in order to access the (vertically stacked) word lines 110(i) of the 3D vertical memory array (e.g., for providing program and / or read pulses), one or more access portions are located, for example, at one or more of the edges of one or more active portions, wherein the conductive material layer 705 has staggered lengths to form "steps" on one or more edges of one or more active portions, such as... Figure 14 As illustrated in the side view.
[0107] Each corresponding "step" of the access portion corresponds to a corresponding layer of the 3D vertical memory array and includes a conductive access contact 1405 that contacts the corresponding conductive material layer 705. In some embodiments, Figure 14 The steps depicted in the text can be formed using trimming and etching techniques.
[0108] Since the access portion does not include memory cells, there is no need for hole-like trenches 505 to form conductive pillars 1005 corresponding to digital lines 115. Furthermore, the access portion has a non-negligible length (e.g., along the x-direction) to be long enough to accommodate several steps, which in turn depends on the number of stacked conductive material layers 705 (e.g., 3 to 4 μm).
[0109] The lack of perforated trenches 505 and the non-negligible length of the access portion may make it unsuitable for direct fabrication using the previously described method (replacing the sacrificial dielectric layer with a conductive material layer).
[0110] In practice, for accessing the various layers of the access portion to remove the sacrificial dielectric layer, the nearest aperture-like trench 505 through which the etchant passes (i.e., in the active portion of the array) may be too far to allow effective removal of the sacrificial dielectric layer. Similarly, the same nearest aperture-like trench 505 through which a conductive material is provided to replace the sacrificial dielectric layer may be too far to allow effective formation of a conductive material layer.
[0111] Furthermore, even if the sacrificial dielectric layer is actually removed from the access portion, the remaining dielectric material layer will still collapse due to the excessive size of the access portion.
[0112] For this reason, according to Figure 15 The embodiments of this disclosure described herein, specifically the dedicated (e.g., linear) trench 1505 (functionally similar to the reference 1505) Figure 3A , 3B The described trench 305) is formed and filled with a dielectric material (as in the reference). Figure 4A , 4B The described trench 305 is filled with dielectric material 405, and a hole-shaped trench 1510 is formed in the dedicated trench 1505.
[0113] According to embodiments of this disclosure, perforated trenches 1510 are advantageously used to remove sacrificial dielectric layers and replace them with conductive material layers, as previously described in perforated trenches 505.
[0114] In addition, the dedicated trench 1505 filled with dielectric material acts as a support structure, which advantageously prevents the remaining dielectric material layer of the access portion from collapsing after the sacrificial layer is removed.
[0115] Figure 16 The diagram illustrates the steps of the method disclosed herein. Several steps of method 1600 for manufacturing a 3D vertical array of memory cells are depicted. Steps 1610 to 1680 can be performed according to the description above with reference to Figures 2 to 13 and 14 to 15. Some details have been omitted from the diagrams of method 1600 to avoid obscuring the method flow. Method 1600 may include: at step 1610, forming a stack of dielectric material layers on a substrate, including alternating first and second dielectric material layers; at step 1620, forming a hole through the stack of dielectric material layers, the hole exposing the substrate; at step 1630, selectively removing a second material layer through the hole to form a cavity between adjacent first dielectric material layers; at step 1640, filling the cavity with a conductive material through the hole to form a corresponding conductive material layer; at step 1650, forming a first memory cell access line from the conductive material layer; at step 1660, performing conformal deposition of a chalcogenide material through the hole; at step 1670, forming a memory cell storage element from the deposited chalcogenide material; and at step 1680, filling the hole with a conductive material to form a corresponding second memory cell access line.
[0116] Several embodiments have been presented and discussed in detail in the preceding description; however, several changes to the described embodiments and different embodiments are possible without departing from the scope defined by the appended claims.
Claims
1. A method for manufacturing a 3D vertical array of memory cells, comprising: A stack of dielectric material layers is formed on a substrate, comprising alternating first dielectric material layers and second dielectric material layers; The stacked layers of dielectric material form spiral trenches that expose the substrate; The spiral trench is filled with a third dielectric material to form a top cover layer that covers the top dielectric material layer. The stack of dielectric material layers forms a hole that exposes the substrate, wherein forming the hole through the stack of dielectric material layers includes forming the hole in the third dielectric material that fills the spiral trench; The second dielectric material layer is selectively removed through the holes to form a cavity between adjacent first dielectric material layers; The cavity is filled with a conductive material through the holes to form a corresponding conductive material layer; The conductive material layer forms the first memory cell access line; Conformal deposition of chalcogenide materials is performed through the aforementioned pores; The deposited chalcogenide material is used to form memory cell storage elements; and The holes are filled with a conductive material to form access lines for the corresponding second memory cells.
2. The method of claim 1, wherein selectively removing the second dielectric material layer via the aperture comprises: Etching agent is provided through the holes.
3. The method of claim 1, wherein selectively removing the second dielectric material layer via the aperture comprises: Perform selective isotropic etching.
4. The method of claim 1, wherein the stacking of the dielectric material layers forming the helical trench comprises: Perform selective vertical etching.
5. The method of claim 1, wherein forming the pores in the third dielectric material filling the spiral trench comprises: Perform selective vertical etching.
6. The method of claim 1, wherein the stack of dielectric material layers forms the spiral trench in a corresponding first portion of the second dielectric material layer and in a second portion of the second dielectric material layer, further dividing each second dielectric material layer, and the cavity is filled with a conductive material such that: Each first portion of the second dielectric material layer is replaced by the corresponding first portion of the conductive material layer; and Each second portion of the second dielectric material layer is replaced by the corresponding second portion of the conductive material layer.
7. The method of claim 6, wherein forming the first memory cell access line from the conductive material layer comprises forming the first memory cell access line from the first portion and the second portion of the conductive material.
8. The method of claim 1, further comprising: Another trench is formed in the stack of dielectric material layers through the access portion of the 3D vertical array of the memory cell; The other trench is filled using the third dielectric material; Other pores are formed in the third dielectric material that fills the other trench; The second dielectric material layer is selectively removed in the access portion via the other holes to form other cavities in the access portion between adjacent first dielectric material layers; and The other cavities are filled with conductive material through the other holes to form a corresponding conductive material layer in the access portion.
9. The method of claim 1, further comprising forming a plurality of conductive contacts extending through the substrate, each conductive contact being associated with a corresponding second access memory line.
10. The method of claim 9, wherein the stacking of the dielectric material layers forming the hole comprises: A hole is formed at the conductive contact to expose the conductive contact.
11. The method of claim 10, wherein filling the hole with a conductive material comprises bringing the conductive contact into contact with the conductive material.
12. A method for manufacturing a 3D vertical array of memory cells, comprising: A stack of dielectric material layers is formed on a substrate, comprising alternating first dielectric material layers and second dielectric material layers; The stacked layers of dielectric material form spiral trenches that expose the substrate; The spiral trench is filled with a third dielectric material to form a top cover layer covering the top dielectric material layer; a hole is formed through the stack of dielectric material layers, the hole exposing the substrate, wherein forming the hole through the stack of dielectric material layers includes forming the hole in the third dielectric material filling the spiral trench; The second dielectric material layer is selectively removed through the holes to form a cavity between adjacent first dielectric material layers; The cavity is filled with conductive material through the holes to form a corresponding conductive material layer for forming the first access line of the memory cell; A memory cell storage element is formed through the notch of the hole; and The holes are filled with a conductive material to form access lines for the corresponding second memory cells.
13. The method of claim 12, further comprising forming a plurality of notches in the conductive material layer at the holes, and performing conformal deposition of a chalcogenide material through the notches of the holes to fill the notches with the chalcogenide material.
14. The method of claim 12, wherein the first dielectric layer comprises silicon dioxide and the second dielectric layer comprises silicon nitride.
15. A 3D vertical array of memory cells manufactured by the method according to any one of claims 1-14, comprising: Multiple 2D arrays of memory cells are stacked on top of a semiconductor substrate; The word lines associated with each 2D array extend substantially parallel to the substrate; Digital lines in the form of conductive pillars extend substantially perpendicular to the substrate; The memory cell includes a data storage element formed at the topological intersection between word lines and digital lines; Word lines associated with adjacent 2D arrays are separated from each other by dielectric material.
16. The 3D vertical array according to claim 15, wherein the dielectric material comprises one of silicon dioxide and silicon nitride.
17. The 3D vertical array of claim 15, wherein the word lines and the number lines are formed of a conductive material comprising tungsten or molybdenum.