A method for detecting defects in flip-chip packaging

Abstract

This invention relates to the field of chip manufacturing technology, and provides a method for detecting defects in flip-chip packaging. The method involves first preparing the chip to be tested, specifically by sputtering a seed layer onto the surface of a bare wafer, then preparing a solder joint array on the seed layer to obtain an initial wafer. Multiple solder joints in the initial wafer's solder joint array are connected through the seed layer. The initial wafer is then diced, soldered, and has its leads formed to obtain a chip set to be tested. This chip set includes multiple chips to be tested. Each chip in the chip set is then subjected to circuit testing to obtain a corresponding circuit testing result. Based on the circuit testing result for each chip, it is determined whether the chip is a qualified chip. This chip electrical performance-based testing method has high testing efficiency and requires testing all chips on the wafer, avoiding missed detections and improving testing accuracy.

Description

Technical Field

[0001] This invention relates to the field of chip manufacturing technology, and in particular to a method for detecting defects in flip-chip packaging. Background Technology

[0002] After the chip is fabricated, it needs to be soldered to external pins. However, the soldering process can lead to problems such as poor soldering. To ensure the feasibility of the soldering process and the yield rate, the structure of the chip after soldering needs to be inspected. Generally, solder joints are first prepared on the bare wafer, and then packaging, cutting and other processes are carried out to form a single chip. Then, X-ray (X-RAY) inspection equipment and scanning electron microscope (SEM) are used to confirm whether the structure of the single chip meets the process requirements (e.g., whether there is a cold solder joint). Since there are tens of thousands of chips on a wafer, sampling and monitoring on a single chip basis is prone to missing anomalies. Moreover, the above-mentioned X-RAY and SEM inspection methods require manual inspection of each chip, which makes the inspection efficiency low. Summary of the Invention

[0003] The present invention aims to solve the technical problems of low efficiency and low accuracy in chip welding and inspection in the prior art.

[0004] To address the aforementioned technical problems, this application discloses a method for detecting defects in flip-chip packaging, comprising:

[0005] Sputtering a seed layer onto the surface of a bare wafer;

[0006] A solder joint array is fabricated on the seed layer to obtain an initial wafer; multiple solder joints in the solder joint array of the initial wafer are connected through the seed layer.

[0007] The initial wafer is cut, soldered, and pin-shaped to obtain a chip set to be tested; the chip set to be tested includes multiple chips to be tested.

[0008] Circuit testing is performed on each of the multiple chips in the chip set to be tested, and the circuit testing result corresponding to each chip is obtained.

[0009] The test results for each chip under test are used to determine whether the chip under test is a qualified chip.

[0010] Optionally, determining whether a chip is a qualified chip based on the circuit test results corresponding to each chip under test includes:

[0011] If the circuit detects that the current is greater than the preset current, then the chip under test is a qualified chip.

[0012] Optionally, the method further includes:

[0013] If the circuit detects that the current is less than or equal to the preset current, then the chip under test is a defective chip.

[0014] Optionally, determining whether a chip is a qualified chip based on the circuit test results corresponding to each chip under test includes:

[0015] If the circuit detects a voltage less than or equal to a preset voltage, then the chip under test is a qualified chip.

[0016] Optionally, the method further includes:

[0017] If the circuit detects a voltage greater than the preset voltage, then the chip under test is a defective chip.

[0018] Optionally, the preset voltage includes 0 volts.

[0019] Optionally, after performing circuit testing on each of the multiple chips in the chip set to be tested, the method further includes:

[0020] The defective chip underwent morphological inspection.

[0021] Optionally, a solder joint array is fabricated on the seed layer to obtain an initial wafer, including:

[0022] A barrier layer is prepared on the surface of the seed layer, and the barrier layer is patterned to form a via array; the via array includes multiple vias;

[0023] A weld pillar is prepared on each of the multiple through holes using an electroplating process;

[0024] The barrier layer is removed, and the solder post is reflowed to obtain the initial wafer.

[0025] Optionally, before dicing, soldering, and pin-forming the initial wafer to obtain the chip assembly to be tested, the process further includes:

[0026] The initial wafer is then thinned.

[0027] Optionally, the initial wafer is diced, soldered, and pin-formed to obtain a chip set to be tested, including:

[0028] The initial wafer is diced to obtain a chip assembly; the chip assembly consists of multiple chips.

[0029] Each chip in the chip set is subjected to lead frame soldering, molding, and lead forming to obtain the chip set to be tested.

[0030] By adopting the above technical solution, the method for detecting defects in flip-chip packaging provided in this application has the following beneficial effects:

[0031] The detection method provided in this application first prepares the chip to be tested. Specifically, a seed layer is sputtered onto the surface of a bare wafer, and a solder joint array is prepared on the seed layer to obtain an initial wafer. Multiple solder joints in the solder joint array of the initial wafer are connected through the seed layer. The initial wafer is then cut, soldered, and pin-shaped to obtain a chip set to be tested. This chip set includes multiple chips to be tested. Circuit testing is then performed on each chip in the chip set to obtain a circuit test result for each chip. Based on the circuit test result for each chip, it is determined whether the chip is a qualified chip. This application tests the electrical performance of each chip to be tested, and the qualification of the chip can be determined directly by measuring the current or voltage value. This method has high detection efficiency and requires testing all chips on the wafer, achieving full inspection, avoiding missed detections, and improving detection accuracy. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a flowchart of an optional method for detecting defects in flip-chip packaging according to this application;

[0034] Figure 2 This is a schematic diagram of an optional reflowed chip structure according to this application;

[0035] Figure 3 A flowchart illustrating another optional method for detecting defects in flip-chip packaging according to this application;

[0036] Figure 4 This is a schematic diagram of an optional encapsulated single chip structure according to this application;

[0037] Figure 5 This is a cross-sectional scan of an optional diced single chip according to this application;

[0038] Figure 6 for Figure 5 Enlarged view of the area indicated by the dashed line.

[0039] The following is supplementary explanation of the attached figures:

[0040] 1-Bare wafer; 2-Seed layer; 3-Solder array; 4-Plastic encapsulation housing; 5-Pin. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0042] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this application. In the description of this application, it should be understood that the terms "upper," "lower," "top," "bottom," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein.

[0043] Typically, existing methods for monitoring chip packaging processes involve first preparing solder joints on a bare wafer, then performing packaging, dicing, and other processes to form a single chip. X-ray inspection and SEM are then used to confirm whether the individual chip structure meets process requirements (e.g., whether there are cold solder joints). Since a wafer contains tens of thousands of chips, sampling and monitoring on a chip-by-chip basis easily misses anomalies. Furthermore, the aforementioned X-ray and SEM methods require manual inspection of each chip, resulting in low inspection efficiency. Therefore, see [reference needed]. Figure 1 , Figure 1 This is a flowchart illustrating an optional method for detecting defects in flip-chip packaging according to this application. The method includes the following steps:

[0044] S101: Sputter seed layer 2 onto the surface of bare wafer 1, see [reference] Figure 2 , Figure 2 This is a schematic diagram of an optional reflowed chip structure according to this application.

[0045] Optionally, the bare wafer 1 is a silicon-based wafer with no circuit layer on its surface, which has the advantage of low cost.

[0046] Optionally, the seed layer 2 can be sputtered across the entire surface of the bare wafer 1; the material of the seed layer 2 includes, but is not limited to, Ti / Cu, that is, it can also be other conductive metals.

[0047] Optionally, the thickness range of titanium is [missing information]. The thickness range of copper is

[0048] Optionally, the thickness of the bare wafer 1 is greater than 450 micrometers. The thickness of the bare wafer 1 can be different for different sizes. Generally, the larger the size, the thicker the bare wafer 1. For example, the thickness of a 4-inch bare wafer 1 is greater than or equal to 450 micrometers, the thickness of a 6-inch bare wafer 1 is greater than or equal to 525 micrometers, the thickness of an 8-inch bare wafer 1 is greater than or equal to 650 micrometers, and the thickness of a 12-inch bare wafer 1 is greater than or equal to 750 micrometers.

[0049] S102: A solder joint array 3 is fabricated on the seed layer 2 to obtain an initial wafer; multiple solder joints in the solder joint array 3 of the initial wafer are connected through the seed layer 2; see reference. Figure 2 .

[0050] In one possible embodiment, see [reference] Figure 3 , Figure 3 This is a flowchart of another optional method for detecting defects in flip-chip packaging according to this application. Step S102 can be specifically described as follows:

[0051] S1021: A barrier layer is prepared on the surface of the seed layer 2, and the barrier layer is patterned to form a through-hole array; the through-hole array includes multiple through holes.

[0052] Optionally, the barrier layer can be photoresist.

[0053] Optionally, the process of patterning the barrier layer can involve exposing, developing, and etching the barrier layer. In practice, the barrier layer can also be formed by sputtering and patterned using photolithography; the choice can be flexible and tailored to the specific requirements.

[0054] S1022: A weld post is prepared on each of the multiple through holes using an electroplating process.

[0055] S1023: Remove the barrier layer and reflow the solder post to obtain the initial wafer.

[0056] See Figure 2The solder column includes a first metal layer and a second metal layer; optionally, the material of the first metal layer includes, but is not limited to, copper, gold and silver; the material of the second metal layer is tin, which facilitates flip-chip soldering with external circuits, and after reflow processing, the surface of the second metal layer will form a spherical shape.

[0057] Optionally, after reflowing the solder pillars, each solder joint in the solder joint array 3 is inspected, and qualified chips in the solder joint array 3 are selected.

[0058] It should be noted that in step S101, the seed layer 2 is fully covered on one surface of the bare wafer 1. After steps S1021-S1023, the solder joint array 3 of the chip can conduct under the connection of the seed layer. In contrast, conventional products remove the seed layer 2 after fabricating the solder joint array 3, and the solder joints in the solder joint array 3 are not conductive. Of course, the coverage area of ​​the seed layer 2 in step S101 or the final coverage area of ​​the seed layer 2 can be adjusted as needed.

[0059] S103: The initial wafer is cut, soldered and pin-shaped to obtain a chip set to be tested; the chip set to be tested includes multiple chips to be tested.

[0060] In one feasible embodiment, prior to step S103, the method further includes: thinning the initial wafer. This ensures that the thickness of the initial wafer is consistent with that of the actual manufactured chip, thereby improving the accuracy of the test results.

[0061] In one feasible embodiment, step S103 can be specifically described as follows: the initial wafer is diced to obtain a chip set; the chip set includes multiple chips; each chip in the multiple chips of the chip set is subjected to lead frame soldering, molding, and lead forming to obtain the chip set to be tested.

[0062] A single initial wafer contains tens of thousands of chips. Current technologies use sampling and monitoring on a chip-by-chip basis, and this manual inspection is inefficient. Insufficient sampling can lead to process monitoring failures, causing anomalies to occur at the customer's end and resulting in losses. This application inspects all chips, improving the effectiveness and accuracy of monitoring results.

[0063] Optional, see below Figure 4 , Figure 4 This is a schematic diagram of an optional molded single chip structure according to this application. Step S103 specifically involves first dicing the initial wafer to obtain multiple single chips, then soldering each chip onto the lead frame using a flip-chip reflow process, and finally performing molding and curing treatment on each chip to obtain the desired result. Figure 4The plastic casing 4 shown is then cut into the pin frame, and the pins 5 of the cut individual chips are electroplated to obtain the chip to be tested.

[0064] It should be noted that multiple chips can be soldered onto this pin frame.

[0065] S104: Perform circuit testing on each of the multiple chips in the chip set to be tested, and obtain the circuit testing result corresponding to each chip to be tested.

[0066] S105: Determine whether the chip under test is a qualified chip based on the circuit test results corresponding to each chip under test.

[0067] Based on the circuit detection principle, the detection can specifically include the following two methods: one is based on current detection. In one feasible embodiment, step S105 can be specifically described as follows:

[0068] If the circuit detects that the current is greater than the preset current, the chip under test is a qualified chip; if the circuit detects that the current is less than or equal to the preset current, the chip under test is a defective chip.

[0069] Based on this current detection principle, the presence of seed layer 2 (conductive layer) ensures overall conductivity. When there is a cold solder joint between the solder joint and the lead frame, refer to [the relevant documentation]. Figure 5-6 As shown, Figure 5 This is a cross-sectional scan of an optional diced single chip according to this application; Figure 6 for Figure 5 The magnified view of the area indicated by the dashed line shows that the detected current value will be larger than the detected current value when there is no cold solder joint issue. Generally, during testing, the normal state is a short circuit, meaning the detected current is infinitely large. Conversely, when a cold solder joint exists in an open circuit state, the detected current is 0.

[0070] It should be noted that, in practice, the preset current can be set to any integer from 0, 1, 2, ..., N, or it can be a decimal. The same applies to the detection voltage mentioned below, which is not restricted here.

[0071] Another method is to determine the chip based on the detection voltage. In one feasible embodiment, step S105 can be specifically described as follows: if the detection result of the circuit is that the detection voltage is less than or equal to the preset voltage, then the chip to be tested is a qualified chip; if the detection result of the circuit is that the detection voltage is greater than the preset voltage, then the chip to be tested is a defective chip.

[0072] In one feasible embodiment, the preset voltage includes 0 volts. Generally, during testing, the normal state is a short circuit, i.e., the detected voltage is 0. Conversely, when an open circuit with a poor solder joint exists, the detected voltage is higher.

[0073] In one feasible embodiment, after step S105, the detection method further includes: performing morphological inspection on the defective chip. Further structural analysis can be performed on the defective chip to promote the research and improvement of chip manufacturing processes.

[0074] Optionally, the morphology detection method includes scanning electron microscopy, X-ray, etc.

[0075] Because existing sampling inspections of chips have no wiring on the surface, electrical performance testing of these chips, regardless of whether there is a cold solder joint, will always show an open circuit, making it impossible to distinguish between them. Furthermore, after molding, the presence of cold solder joints cannot be directly detected. Transmission testing methods are not only costly but also inefficient. This invention provides a method for detecting defects in flip-chip packaging. It involves preparing a seed layer 2, a solder joint array 3, flip-chip bonding, and molding on a bare wafer 1 (without wiring) to obtain the chip to be tested. The electrical performance characteristics of the chip are used to detect flip-chip bonding defects. Cold solder joint structures are revealed in the test results. Testing is performed on a fully automated machine, batch confirmation of process normality, and targeted structural analysis of chips with abnormalities. This method is highly efficient, ensures no sampling omissions, and allows for process monitoring before mass production of customer chips, enabling targeted process improvements and avoiding yield losses in subsequent customer chips. This method is applicable to most flip-chip packaging types, including SOT, DFN, and QFN, and is not limited to a single packaging type.

[0076] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for detecting defects in flip-chip packaging, characterized in that, include: A seed layer (2) is sputtered onto the surface of the bare wafer (1); A solder joint array (3) is prepared on the seed layer (2) to obtain an initial wafer; multiple solder joints in the solder joint array (3) of the initial wafer are connected through the seed layer (2); The initial wafer is cut, soldered, and pin-shaped to obtain a chip set to be tested; the chip set to be tested includes multiple chips to be tested. Circuit testing is performed on each of the multiple chips in the chip set to be tested to obtain the circuit testing result corresponding to each chip to be tested; The test chip is determined as a qualified chip based on the circuit test results corresponding to each chip under test.

2. The detection method according to claim 1, characterized in that, The step of determining whether a chip under test is a qualified chip based on the circuit detection results corresponding to each chip under test includes: If the circuit detection result shows that the detected current is greater than the preset current, then the chip to be tested is a qualified chip.

3. The detection method according to claim 2, characterized in that, The method further includes: If the circuit detection result is that the detected current is less than or equal to the preset current, then the chip to be tested is a defective chip.

4. The detection method according to claim 1, characterized in that, The step of determining whether a chip under test is a qualified chip based on the circuit detection results corresponding to each chip under test includes: If the circuit detection result is that the detection voltage is less than or equal to the preset voltage, then the chip to be tested is a qualified chip.

5. The detection method according to claim 4, characterized in that, The method further includes: If the circuit detection result shows that the detected voltage is greater than the preset voltage, then the chip to be tested is a defective chip.

6. The detection method according to claim 5, characterized in that, The preset voltage includes 0 volts.

7. The detection method according to claim 3, characterized in that, After performing circuit testing on each of the multiple chips in the chip set to be tested, the method further includes: The defective chips were subjected to morphological inspection.

8. The detection method according to claim 1, characterized in that, The process of preparing a solder joint array (3) on the seed layer (2) to obtain an initial wafer includes: A barrier layer is prepared on the surface of the seed layer (2), and the barrier layer is patterned to form a through-hole array; the through-hole array includes a plurality of through holes; A weld pillar is prepared on each of the plurality of through holes using an electroplating process; The barrier layer is removed, and the solder pillars are reflowed to obtain the initial wafer.

9. The detection method according to claim 1, characterized in that, Before performing dicing, soldering, and pin forming on the initial wafer to obtain the chip set to be tested, the process further includes: The initial wafer is then thinned.

10. The detection method according to claim 1, characterized in that, The process of cutting, soldering, and pin forming of the initial wafer to obtain the chip set to be tested includes: The initial wafer is diced to obtain a chip assembly; the chip assembly includes multiple chips. Each chip in the chip set is subjected to lead frame soldering, molding, and lead forming processes to obtain the chip set to be tested.

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