A method and apparatus for reducing chip power consumption

Abstract

The application provides a method and device for reducing chip power consumption, the method comprising: after receiving a sleep instruction, obtaining a sleep duration and a data volume of target data to be saved during the sleep; according to the sleep duration, the data volume to be saved during the sleep and data processing capacity data of at least two memories, estimating power consumption required by each memory for saving the target data; selecting the memory with the minimum power consumption required for saving the target data, and performing an operation of saving the target data during the sleep of the chip. In the application, by designing a method strategy according to a standby duration and power consumption characteristics of a data storage device, different data storage schemes are selected, a more scientific and reasonable data storage method in a sleep process is realized, and the power consumption of the chip is reduced.

Description

Technical Field

[0001] This invention relates to the field of chip design, and more particularly to a method and apparatus for reducing chip power consumption. Background Technology

[0002] With the continuous development and application of electronic devices, the requirements for chip performance are constantly increasing, and therefore, the requirements for low power consumption of chips are also constantly increasing.

[0003] In existing technologies, most solutions for reducing chip power consumption involve reducing the module's power supply voltage or clock frequency based on usage conditions, rather than designing power reduction strategies for specific application scenarios. Summary of the Invention

[0004] This invention provides a method and apparatus for reducing chip power consumption, addressing the problem in the prior art that there are no power consumption reduction methods or strategies designed for specific application scenarios.

[0005] To solve the above-mentioned technical problems, the present invention is implemented as follows:

[0006] In a first aspect, the present invention provides a method for reducing chip power consumption, comprising:

[0007] Upon receiving a hibernation instruction, obtain the hibernation duration and the amount of target data to be saved during hibernation;

[0008] Based on the sleep duration, the amount of data to be saved during sleep, and the data processing capabilities of at least two memory devices, the power consumption required for each of the memory devices to save the target data is estimated.

[0009] Select the memory with the lowest power consumption required to store the target data, and perform the operation of saving the target data when the chip is in sleep mode.

[0010] Optionally, the at least two memories include a first memory and a second memory, and after selecting the memory that requires the least power to store the target data, the system further includes:

[0011] A flag is set in the first memory to indicate whether the first memory performs the operation of saving the target data when the chip is in sleep mode.

[0012] Optionally, after setting the flag bit in the first memory of the at least two memories, the method further includes:

[0013] After the sleep duration ends, read the flag bit in the first memory;

[0014] If the flag indicates that the first memory performs the operation of saving the target data when the chip is in sleep mode, then the target data stored in the first memory is used directly for operation;

[0015] If the flag indicates that the operation of saving the target data during chip sleep is not performed by the first memory, then the target data stored in the second memory is restored to the first memory, and the operation is carried out using the target data restored to the first memory.

[0016] Optionally, the first memory is a RAM memory.

[0017] Optionally, the second memory is a FLASH memory.

[0018] Optionally, the RAM memory data processing capability data includes at least one of the following: static current when storing the target data and static voltage when storing the target data.

[0019] Optionally, the FLASH memory data processing capability data includes at least one of the following: the current value when reading the target data, the current value when writing the target data, the voltage value when reading the target data, the voltage value when writing the target data, the time required to read the target data, and the time required to write the target data.

[0020] In a second aspect, the present invention provides an apparatus for reducing chip power consumption, comprising:

[0021] The acquisition module is used to acquire the hibernation duration and the amount of target data to be saved during hibernation after receiving the hibernation instruction;

[0022] The calculation module is used to estimate the power consumption required by each of the memories to store the target data based on the hibernation duration, the amount of data to be saved during hibernation, and the data processing capabilities of at least two memories.

[0023] An execution module is used to select the memory with the lowest power consumption required to save the target data, and to perform the operation of saving the target data when the chip is in sleep mode.

[0024] Optionally, the at least two memories include a first memory and a second memory, and further include: a flag bit indication module, used to set a flag bit in the first memory to indicate whether the first memory performs the operation of saving the target data when the chip is in sleep mode.

[0025] Optionally, a read module is used to read the flag bit in the first memory after the sleep duration ends;

[0026] The first processing module is configured to directly use the target data stored in the first memory to run if the flag bit indicates that the first memory performs the operation of saving the target data when the chip is in sleep mode.

[0027] The second processing module is configured to restore the target data stored in the second memory to the first memory and run the program if the flag indicates that the operation of saving the target data during chip sleep is not performed by the first memory.

[0028] Optionally, the first memory is a RAM memory.

[0029] Optionally, the second memory is a FLASH memory.

[0030] Optionally, the RAM memory data processing capability data includes at least one of the following: static current when storing the target data and static voltage when storing the target data.

[0031] Optionally, the FLASH memory data processing capability data includes at least one of the following: the current value when reading the target data, the current value when writing the target data, the voltage value when reading the target data, the voltage value when writing the target data, the time required to read the target data, and the time required to write the target data.

[0032] Thirdly, the present invention provides a chip comprising: a processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps of the method for reducing chip power consumption as described in any one of the first aspects.

[0033] Fourthly, the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method for reducing chip power consumption as described in any one of the first aspects.

[0034] In this invention, by selecting different data storage schemes based on standby time and the power consumption characteristics of data storage devices, a more scientific and reasonable method for storing data during hibernation is chosen, thereby reducing chip power consumption and solving the problem in the prior art of not designing power reduction methods and strategies for specific application scenarios. Attached Figure Description

[0035] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0036] Figure 1 This is a flowchart of a method for reducing chip power consumption provided in an embodiment of the present invention;

[0037] Figure 2 A schematic diagram of a chip structure provided in an embodiment of the present invention;

[0038] Figure 3 A flowchart illustrating the sleep mode preparation method for reducing chip power consumption, as provided in an embodiment of the present invention;

[0039] Figure 4 A flowchart illustrating a method for reducing chip power consumption after sleep mode, provided in an embodiment of the present invention;

[0040] Figure 5 A schematic diagram of a device for reducing chip power consumption provided in an embodiment of the present invention;

[0041] Figure 6 This is a schematic diagram of another chip structure provided in an embodiment of the present invention. Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] Please refer to Figure 1 This invention provides a method for reducing chip power consumption, comprising:

[0044] Step 11: After receiving the hibernation instruction, obtain the hibernation duration and the amount of target data to be saved during hibernation;

[0045] Step 12: Based on the sleep duration, the amount of data to be saved during sleep, and the data processing capabilities of at least two memory devices, estimate the power consumption required for each of the memory devices to save the target data;

[0046] Step 13: Select the memory with the lowest power consumption required to save the target data, and perform the operation of saving the target data when the chip is in sleep mode.

[0047] In the embodiments of this invention, please refer to Figure 2 The chip in question is a System on Chip (SOC), consisting of a processor and at least two memory modules. Please refer to [link / reference needed]. Figure 3 After the chip completes its business process, it enters a sleep state. Upon receiving a sleep instruction, the chip's processor prepares for sleep and obtains the sleep duration. In step 12, the at least two memories include a first memory and a second memory. The first memory is selected as RAM; the second memory is selected as FLASH memory. The processor is responsible for process processing and data calculation. The RAM memory can be used to store data, but the data stored will be lost in the event of a power outage. The FLASH memory can be used to store data, but the data stored will not be lost in the event of a power outage. The selection of the memory is not limited to the above two types; ROM memory, etc., can also be selected. The data processing capability data of the two memories includes: the RAM memory data processing capability data includes at least one of the following: the static current when storing the target data and the static voltage when storing the target data; the FLASH memory data processing capability data includes at least one of the following: the current value when reading the target data. The data processing parameters are: the current value when writing the target data, the voltage value when reading the target data, the time required to read the target data, and the time required to write the target data. Based on the sleep duration, the amount of data to be saved during sleep, and the aforementioned data processing capabilities, the chip processor estimates the power consumption required for the RAM and FLASH memory to save the target data. In step 13, the processor selects the memory with lower power consumption to perform the operation of saving the target data during sleep. If the calculated power consumption required for the RAM memory to save the target data is lower, the RAM memory is selected to perform the operation of saving the target data during chip sleep, and the processor enters a sleep state. If the calculated power consumption required for the FLASH memory to save the target data is lower, the data originally stored in the RAM memory is written to the FLASH memory, the operation of saving the target data during chip sleep is performed, and the processor enters a sleep state.

[0048] In this embodiment of the invention, by selecting different data storage schemes based on the sleep duration and the power consumption characteristics required for the data storage to store the target data, a more scientific and reasonable method for storing data during the sleep process is selected, thereby reducing the power consumption of the chip and solving the problem in the prior art that there are no methods or strategies for reducing power consumption for specific application scenarios.

[0049] In this embodiment of the invention, optionally, the at least two memories include a first memory and a second memory, and after selecting the memory with the lowest power consumption required to store the target data, the invention further includes:

[0050] A flag is set in the first memory to indicate whether the first memory performs the operation of saving the target data when the chip is in sleep mode.

[0051] In an embodiment of the present invention, optionally, after setting the flag bit in the first memory of the at least two memories, the method further includes:

[0052] After the sleep duration ends, read the flag bit in the first memory;

[0053] If the flag indicates that the first memory performs the operation of saving the target data when the chip is in sleep mode, then the target data stored in the first memory is used directly for operation;

[0054] If the flag indicates that the operation of saving the target data during chip sleep is not performed by the first memory, then the target data stored in the second memory is restored to the first memory, and the operation is carried out using the target data restored to the first memory.

[0055] Please refer to Figure 4 In this embodiment of the invention, a flag bit is set in the first memory, i.e., the RAM memory, so as to read which memory performed the operation of saving the target data during hibernation when exiting the hibernation state; and read the flag bit in the first memory, i.e., the RAM memory;

[0056] If the flag indicates that the operation of saving the target data during chip sleep is performed by the RAM memory, then the target data stored in the RAM memory is used directly for operation;

[0057] If the flag indicates that the operation of saving the target data during chip hibernation is not performed by the RAM memory, then the target data stored in the second memory, i.e. the FLASH memory, is restored to the RAM memory, and the operation is carried out using the target data restored to the RAM memory.

[0058] In this embodiment of the invention, optionally, the first memory is a RAM memory.

[0059] In this embodiment of the invention, optionally, the RAM memory is a retention RAM memory.

[0060] In this embodiment of the invention, the first memory may be, but is not limited to, a RAM memory, and the RAM memory may be, but is not limited to, a Retention RAM memory.

[0061] In this embodiment of the invention, optionally, the second memory is a FLASH memory.

[0062] In this embodiment of the invention, the second memory may be, but is not limited to, the FLASH memory.

[0063] In this embodiment of the invention, optionally, the RAM memory data processing capability data includes at least one of the following: static current when storing the target data and static voltage when storing the target data.

[0064] In this embodiment of the invention, optionally, the FLASH memory data processing capability data includes at least one of the following: the current value when reading the target data, the current value when writing the target data, the voltage value when reading the target data, the voltage value when writing the target data, the time required to read the target data, and the time required to write the target data.

[0065] In this embodiment of the invention, by selecting different data storage schemes based on the sleep duration and the power consumption characteristics required for the data storage to store the target data, a more scientific and reasonable method for storing data during the sleep process is selected, thereby reducing the power consumption of the chip and solving the problem in the prior art that there are no methods or strategies for reducing power consumption for specific application scenarios.

[0066] Please refer to Figure 5 The present invention provides an apparatus for reducing chip power consumption, comprising:

[0067] The acquisition module 51 is used to acquire the sleep duration and the amount of target data to be saved during sleep after receiving the sleep instruction;

[0068] The calculation module 52 is used to estimate the power consumption required by each of the memories to store the target data based on the hibernation duration, the amount of data to be saved during hibernation, and the data processing capabilities of at least two memories.

[0069] The execution module 53 is used to select the memory with the lowest power consumption required to save the target data, and to perform the operation of saving the target data when the chip is in sleep mode.

[0070] In this embodiment of the invention, optionally, the at least two memories include a first memory and a second memory, and further include: a flag bit indication module, used to set a flag bit in the first memory to indicate whether the first memory performs the operation of saving the target data when the chip is in sleep mode.

[0071] In this embodiment of the invention, optionally, the reading module is used to read the flag bit in the first memory after the sleep duration ends;

[0072] The first processing module is configured to directly use the target data stored in the first memory to run if the flag bit indicates that the first memory performs the operation of saving the target data when the chip is in sleep mode.

[0073] The second processing module is configured to restore the target data stored in the second memory to the first memory and run the program if the flag indicates that the operation of saving the target data during chip sleep is not performed by the first memory.

[0074] In this embodiment of the invention, optionally, the first memory is a RAM memory.

[0075] In this embodiment of the invention, optionally, the second memory is a FLASH memory.

[0076] In this embodiment of the invention, optionally, the RAM memory data processing capability data includes at least one of the following: static current when storing the target data and static voltage when storing the target data.

[0077] In this embodiment of the invention, optionally, the FLASH memory data processing capability data includes at least one of the following: the current value when reading the target data, the current value when writing the target data, the voltage value when reading the target data, the voltage value when writing the target data, the time required to read the target data, and the time required to write the target data.

[0078] The device for reducing chip power consumption provided in this embodiment of the invention can achieve... Figure 1 The various processes involved in reducing chip power consumption in the method embodiments are not described in detail here to avoid repetition.

[0079] Please refer to Figure 6This invention also provides a network device 60, including a processor 61, a memory 62, and a computer program stored in the memory 62 and executable on the processor 61. When the computer program is executed by the processor 61, it implements the various processes of the above-described method embodiments for reducing chip power consumption and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0080] This invention also provides a computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the various processes of the above-described method embodiments for reducing chip power consumption and achieves the same technical effects. To avoid repetition, these details will not be repeated here. The computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0081] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0082] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0083] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

Claims

1. A method for reducing chip power consumption, characterized in that, include: Upon receiving a hibernation instruction, obtain the hibernation duration and the amount of target data to be saved during hibernation; Based on the sleep duration, the amount of data to be saved during sleep, and the data processing capabilities of at least two memory devices, the power consumption required for each of the memory devices to save the target data is estimated. Select the memory with the lowest power consumption required to save the target data, and perform the operation of saving the target data when the chip is in sleep mode; The at least two memories include a first memory and a second memory, and after selecting the memory that requires the least power consumption to store the target data, the following are also included: A flag bit is set in the first memory to indicate whether the first memory performs the operation of saving the target data when the chip is in sleep mode; After setting the flag bit in the first memory of the at least two memories, the method further includes: After the sleep duration ends, read the flag bit in the first memory; If the flag indicates that the first memory performs the operation of saving the target data when the chip is in sleep mode, then the target data stored in the first memory is used directly for operation; If the flag indicates that the operation of saving the target data during chip sleep is not performed by the first memory, then the target data stored in the second memory is restored to the first memory, and the operation is carried out using the target data restored to the first memory.

2. The method for reducing chip power consumption according to claim 1, characterized in that, The first memory is a RAM memory.

3. The method for reducing chip power consumption according to claim 1, characterized in that, The second memory is a FLASH memory.

4. The method for reducing chip power consumption according to claim 2, characterized in that, The RAM memory data processing capability data includes at least one of the following: static current when storing the target data and static voltage when storing the target data.

5. The method for reducing chip power consumption according to claim 3, characterized in that, The FLASH memory data processing capability data includes at least one of the following: the current value when reading the target data, the current value when writing the target data, the voltage value when reading the target data, the voltage value when writing the target data, the time required to read the target data, and the time required to write the target data.

6. A device for reducing chip power consumption, characterized in that, include: The acquisition module is used to acquire the hibernation duration and the amount of target data to be saved during hibernation after receiving the hibernation instruction; The calculation module is used to estimate the power consumption required by each of the memories to store the target data based on the hibernation duration, the amount of data to be saved during hibernation, and the data processing capabilities of at least two memories. The execution module is used to select the memory with the lowest power consumption required to save the target data, and to perform the operation of saving the target data when the chip is in sleep mode; The at least two memories include a first memory and a second memory. After selecting the memory that requires the least power to store the target data, the system further includes: A flag bit is set in the first memory to indicate whether the first memory performs the operation of saving the target data when the chip is in sleep mode; After setting the flag bit in the first memory of the at least two memories, the method further includes: After the sleep duration ends, read the flag bit in the first memory; If the flag indicates that the first memory performs the operation of saving the target data when the chip is in sleep mode, then the target data stored in the first memory is used directly for operation; If the flag indicates that the operation of saving the target data during chip sleep is not performed by the first memory, then the target data stored in the second memory is restored to the first memory, and the operation is carried out using the target data restored to the first memory.

7. A chip, characterized in that, include: A processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps of the method for reducing chip power consumption as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method for reducing chip power consumption as described in any one of claims 1 to 5.

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