Electro-optical device and electronic equipment

Abstract

An electro-optical device and an electronic device that suppress a linear decrease in output voltage caused by parasitic capacitance. The DA conversion circuit (500) includes: a first DA conversion circuit section (Upb) corresponding to high-order bits, having capacitor elements (C5 to C9) and selection circuits (515 to 519); a second DA conversion circuit section (Lwb) corresponding to low-order bits, having capacitor elements (C0 to C4) and selection circuits (510 to 514); a capacitor element (Cser) provided between the first and second DA conversion circuit sections, and the selection circuits (515 to 519) supply a potential (VL) or (VPH) to one end of the capacitor elements (C5 to C9), and the selection circuits (510 to 514) supply a potential (VL) or (VPL) to one end of the capacitor elements (C0 to C4). The potential (VPL) is different from the potential (VPH), for example, VPL > VPH.

Description

Technical Field

[0001] The present invention relates to a DA conversion circuit, an electro-optical device, and an electronic device. Background Art

[0002] There is known an electro-optical device using, for example, an OLED as a display element. OLED is an abbreviation for Organic Light Emitting Diode. In this electro-optical device, a pixel circuit including a transistor or the like for causing current to flow through the display element is provided corresponding to each pixel of a displayed image. The transistor supplies a current corresponding to a luminance level to the display element. Thereby, the display element emits light with a luminance corresponding to the current.

[0003] In the above electro-optical device, a voltage corresponding to luminance is applied to a gate node of a driving transistor via a data line. Specifically, digital data specifying luminance is converted into an analog voltage by a DA conversion circuit, and the converted voltage is applied to the gate node of the driving transistor via the data line.

[0004] As a technique applied to such a DA conversion circuit, for example, the following technique is known. Specifically, there is known a technique including: a capacitance element corresponding to a high-order bit; a capacitance element corresponding to a low-order bit; a switching element provided corresponding to the capacitance element, which selects a potential Gnd or Vref according to a bit and supplies it to one end of the capacitance element; and a coupling capacitance provided between the other end of the capacitance element corresponding to the high-order bit and the other end of the capacitance element corresponding to the low-order bit (for example, refer to Patent Document 1).

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2002-1907384

[0006] However, in the technique described in Patent Document 1, there is a problem that the accuracy of converting input data composed of a plurality of bits into an analog voltage sometimes decreases, specifically, the linearity sometimes deteriorates. Summary of the Invention

[0007] A DA conversion circuit according to one embodiment of the present disclosure includes: a first DA conversion circuit section corresponding to high-order bits among a plurality of bits; a second DA conversion circuit section corresponding to low-order bits among the plurality of bits; and a coupling capacitor provided between the first DA conversion circuit section and the second DA conversion circuit section. The first DA conversion circuit section includes a high-order capacitor element section and a high-order switch element section, the second DA conversion circuit section includes a low-order capacitor element section and a low-order switch element section, the high-order switch element section supplies either a first potential or a second potential to one end of the high-order capacitor element section, and the low-order switch element section supplies either the first potential or a third potential to one end of the low-order capacitor element section, where the third potential is different from the second potential. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. 6 is a perspective view of an electro-optical device to which the DA conversion circuit of the first embodiment is applied.

[0009] Figure 2 FIG. 7 is a block diagram showing the electrical configuration of the electro-optical device.

[0010] Figure 3 FIG. 8 is a circuit diagram showing a pixel circuit in the electro-optical device.

[0011] Figure 4 FIG. 9 is a circuit diagram showing the DA conversion circuit in the data signal output circuit.

[0012] Figure 5 FIG. 10 is a diagram showing an equivalent circuit of the DA conversion circuit.

[0013] Figure 6 FIG. 11 is a timing diagram showing the operation of the electro-optical device.

[0014] Figure 7 FIG. 12 is a diagram for explaining the operation of the electro-optical device.

[0015] Figure 8 FIG. 13 is a diagram for explaining the operation of the electro-optical device.

[0016] Figure 9 FIG. 14 is a diagram for explaining the operation of the electro-optical device.

[0017] Figure 10 FIG. 15 is a diagram for explaining the operation of the electro-optical device.

[0018] Figure 11 FIG. 16 is a diagram showing the output characteristics of the DA conversion circuit.

[0019] Figure 12 FIG. 17 is a diagram showing the output characteristics of the DA conversion circuit according to the second embodiment.

[0020] Figure 13 It is a diagram showing the output characteristics of the DA conversion circuit of the third embodiment.

[0021] Figure 14 It is a top view showing the arrangement of each element in the electro-optical device.

[0022] Figure 15 It is a diagram showing the arrangement of pixel circuits in the electro-optical device.

[0023] Figure 16 It is a diagram showing the configuration of the data signal output circuit in the fourth embodiment.

[0024] Figure 17 It is a top view showing an example of a capacitive element in the DA conversion circuit.

[0025] Figure 18 It is a top view showing an example of a capacitive element in the DA conversion circuit.

[0026] Figure 19 It is a top view showing an example of a capacitive element in the DA conversion circuit.

[0027] Figure 20 It is a top view showing an example of a capacitive element in the DA conversion circuit.

[0028] Figure 21 It is a top view showing an example of a capacitive element in the DA conversion circuit.

[0029] Figure 22 It is along Figures 17 to 21 A partial cross-sectional view taken along the P-p line in

[0030] Figure 23 It is along Figures 17 to 21 A partial cross-sectional view taken along the Q-q line in

[0031] Figure 24 It is a perspective view showing a head-mounted display using the electro-optical device.

[0032] Figure 25 It is a diagram showing the optical structure of the head-mounted display.

[0033] Reference numeral description

[0034] 10: Electro-optical device; 12: Scan line; 14: Data line; 14b: Relay line; 100: Display area; 110: Pixel circuit; 121 - 125: Transistor; 130: OLED; 140: Capacitive element; 300: Head-mounted display; 500: DA conversion circuit; Upb: First DA conversion circuit section; Lwb: Second DA conversion circuit section; C0 - C9: Capacitive element; Cser: Capacitive element (coupling capacitor). Detailed implementation mode

[0035] Hereinafter, the DA conversion circuit according to the embodiment of the present invention will be described with reference to the accompanying drawings.

[0036] In addition, in each figure, the sizes and scales of the respective parts are appropriately different from the actual ones. In addition, the following-described embodiments are preferred specific examples, and thus various technically preferred limitations are added. However, as long as there is no specific limitation on the meaning of the present invention in the following description, the scope of the present invention is not limited to these embodiments.

[0037] [First Embodiment]

[0038] Figure 1 FIG. is a perspective view of the electro-optical device 10 to which the DA conversion circuit according to the first embodiment is applied. The electro-optical device 10 is, for example, a micro display panel that displays an image in a head-mounted display or the like. The electro-optical device 10 includes a pixel circuit, a drive circuit that drives the pixel circuit, etc., and the pixel circuit includes a display element. The pixel circuit and the drive circuit are integrated on a semiconductor substrate. The semiconductor substrate is typically a silicon substrate, but may also be other semiconductor substrates.

[0039] The electro-optical device 10 is housed in a frame-shaped housing 192 that opens in the display area 100. The electro-optical device 10 is connected to one end of the FPC substrate 194. FPC is an abbreviation for Flexible Printed Circuits (flexible printed circuit). A plurality of terminals 196 for connecting to a host device (not shown) are provided at the other end of the FPC substrate 194. When the plurality of terminals 196 are connected to the host device, video data, a synchronization signal, etc. are supplied from the host device to the electro-optical device 10 via the FPC substrate 194.

[0040] In addition, in the figure, the X direction represents the extending direction of the scanning lines in the electro-optical device 10, and the Y direction represents the extending direction of the data lines. The two-dimensional plane determined by the X direction and the Y direction is the substrate surface of the semiconductor substrate. The Z direction is perpendicular to the X direction and the Y direction and is the emission direction of the light emitted from the display element.

[0041] Figure 2 FIG. is a block diagram showing the electrical structure of the electro-optical device 10. As shown in the figure, the electro-optical device 10 is roughly divided into a power supply circuit 15, a control circuit 30, a data signal output circuit 50, an initialization circuit 60, a display area 100, and a scanning line drive circuit 120.

[0042] In the display area 100, m rows of scanning lines 12 are arranged along the X direction in the figure, and n columns of data lines 14 are arranged along the Y direction in such a manner as to ensure electrical insulation from each of the scanning lines 12. In addition, m and n are integers of 2 or more.

[0043] In the display area 100, pixel circuits 110 are provided corresponding to the intersections of the scanning lines 12 of m rows and the data lines 14 of n columns. Therefore, the pixel circuits 110 are arranged in a matrix of m rows in the vertical direction and n columns in the horizontal direction. In the matrix arrangement, in order to distinguish the rows (low), they are sometimes referred to as the 1st, 2nd, 3rd, ……, (m - 1)th, and mth rows in order from the top in the figure. Similarly, in order to distinguish the columns (column) of the matrix, they are sometimes referred to as the 1st, 2nd, 3rd, ……, (n - 1)th, and nth columns in order from the left in the figure.

[0044] In addition, in order to generally describe the scanning lines 12, an integer i from 1 to m is used. Similarly, in order to generally describe the data lines 14, an integer j from 1 to n is used.

[0045] The control circuit 30 controls each part based on the video data Vid and the synchronization signal Sync supplied from the host device. The video data Vid designates, for example, the gray level of the pixels in the image to be displayed in 8 bits for each of the three primary colors.

[0046] The synchronization signal Sync includes a vertical synchronization signal indicating the start of vertical scanning of the video data Vid, a horizontal synchronization signal indicating the start of horizontal scanning, and a dot clock signal representing the timing of one pixel of the video data.

[0047] In the present embodiment, the pixels of the image to be displayed correspond one-to-one with the pixel circuits 110 in the display area 100.

[0048] The characteristics of the luminance at the gray level represented by the video data Vid supplied from the host device do not necessarily match the characteristics of the luminance in the OLEDs included in the pixel circuits 110.

[0049] Therefore, in order to make the OLED emit light with a luminance corresponding to the gray level represented by the video data Vid, the control circuit 30, for example, up-converts the 8 bits of the video data Vid to 10 bits in the present embodiment and outputs it as the video data Vdata. Therefore, the 10-bit video data Vdata becomes data corresponding to the gray level specified by the video data Vid.

[0050] In addition, in the up-conversion, a look-up table in which the correspondence between the 8 bits of the input video data Vid and the 10 bits of the output video data Vdata is stored in advance is used. In addition, the control circuit 30 generates various control signals for controlling each part, and the detailed content will be described later.

[0051] The scan line driving circuit 120 is a circuit for outputting various signals, and thus driving the pixel circuits 110 arranged in m rows and n columns row by row according to the control of the control circuit 30. For example, the scan line driving circuit 120 sequentially supplies scan signals / Gwr(1), / Gwr(2),..., / Gwr(m - 1), / Gwr(m) to the scan lines 12 of the first, second, third,..., (m - 1), m-th rows. Usually, the scan signal supplied to the scan line 12 of the i-th row is denoted as / Gwr(i). The scan line driving circuit 120 outputs various control signals in addition to the scan signals / Gwr(1) to / Gwr(m), and the details will be described later.

[0052] The data signal output circuit 50 is a circuit that outputs data signals corresponding to the voltage and brightness to the pixel circuits 110 located in the rows selected by the scan line driving circuit 120. Specifically, the data signal output circuit 50 includes a selection circuit group 52, a first latch circuit group 54, a second latch circuit group 56, and n DA conversion circuits 500. The selection circuit group 52 includes selection circuits 520 corresponding to n columns respectively, the first latch circuit group 54 includes first latch circuits L1 corresponding to n columns respectively, and the second latch circuit group 56 includes second latch circuits L2 corresponding to n columns respectively.

[0053] That is, a group of selection circuits 520, first latch circuits L1, second latch circuits L2, and DA conversion circuits 500 are provided corresponding to each column. The selection circuit 520 of the j-th column instructs the first latch circuit L1 of the j-th column to select the image data of the j-th column from the image data Vdata output from the control circuit 30, and the first latch circuit L1 of the j-th column latches the image data Vdata according to this instruction. The second latch circuit L2 of the j-th column outputs the image data Vdata latched by the first latch circuit L1 of the j-th column to the DA conversion circuit 500 of the j-th column during the writing period to be described later according to the control of the control circuit 30.

[0054] The DA conversion circuit 500 of the j-th column converts the 10-bit image data Vdata output from the second latch circuit L2 of the j-th column into a data signal of an analog voltage, and outputs it as a data signal to the data line 14 of the j-th column. In addition, the details of the DA conversion circuit 500 will be described later.

[0055] The initialization circuit 60 is an aggregate of transistors 66 provided in one-to-one correspondence with the data lines 14. One end of the transistor 66 corresponding to the j-th column is connected to the power supply line of the potential Vini, and the other end of the transistor 66 is connected to the data line 14 of the j-th column. In addition, the control signal / Gini of the control circuit 30 is commonly supplied to the gate nodes of the transistors 66 in each column.

[0056] In the figure, the potentials of the data lines 14 in the 1st, 2nd, ……, (n - 1)th, and nth columns are sequentially described as Vd(1), Vd(2), ……, Vd(n - 1), Vd(n). Usually, the potential of the data line 14 in the jth column is described as Vd(j).

[0057] The power supply circuit 15 generates various power supply potentials, power supply voltages, etc. used in the electro-optical device 10. Examples of the various power supply potentials and power supply voltages include the power supply voltages in the scan line driver circuit 120 and the data signal output circuit 50, and the potentials Vel, Vini, Vorst, Vrst, VL, VPL, VPH, etc.

[0058] In addition, the reference for zero voltage is the ground potential Gnd (not shown in the figure), but other than this, there is no strict distinction between the use of potential and voltage in this description. In addition, in this description, the power supply potential and the power supply voltage refer to voltages and potentials that are substantially constant over time.

[0059] Figure 3 It is a circuit diagram showing the pixel circuit 110. The pixel circuits 110 arranged in m rows and n columns are identical to each other electrically. Therefore, regarding the pixel circuit 110, the pixel circuit 110 located in the ith row and jth column is used as a representative for explanation.

[0060] As shown in the figure, the pixel circuit 110 includes an OLED 130, P-channel transistors 121 to 125, and a capacitor element 140. The transistors 121 to 125 are, for example, MOS. In addition, MOS is an abbreviation for Metal - Oxide - Semiconductor field - effect transistor (metal oxide semiconductor field - effect transistor).

[0061] In addition to the scan signal / Gwr(i), the control signals / Gel(i), / Gcmp(i), / Gorst(i) are also supplied from the scan line driver circuit 120 to the pixel circuit 110 in the ith row.

[0062] The control signal / Gel(i) is a signal that generally describes the control signals / Gel(1), / Gel(2), ……, / Gel(m - 1), / Gel(m) supplied in sequence corresponding to the 1st, 2nd, ……, (m - 1)th, and mth rows. Similarly, the control signal / Gcmp(i) is a signal that generally describes the control signals / Gcmp(1), / Gcmp(2), ……, / Gcmp(m - 1), / Gcmp(m) supplied in sequence corresponding to the 1st, 2nd, ……, (m - 1)th, and mth rows. The same applies to the control signal / Gorst(i), which is a signal that generally describes the control signals / Gorst(1), / Gorst(2), ……, / Gorst(m - 1), / Gorst(m) supplied in sequence corresponding to the 1st, 2nd, ……, (m - 1)th, and mth rows.

[0063] The OLED 130 is a display element in which a light-emitting functional layer 132 is sandwiched between a pixel electrode 131 and a common electrode 133. The pixel electrode 131 functions as an anode, and the common electrode 133 functions as a cathode. In addition, since the common electrode 133 has light reflectivity and light transmissivity, it is an example of a semi-reflective and semi-transmissive reflective layer. In the OLED 130, when current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting functional layer 132 to generate excitons, producing white light.

[0064] In the case of color display, the generated white light resonates, for example, in an optical resonator composed of a reflective layer and a semi-reflective and semi-transmissive layer (not shown), and is emitted at a resonance wavelength set to correspond to any one of R (red), G (green), and B (blue). A color filter corresponding to this color is provided on the light-emitting side of the light from the optical resonator. Therefore, the light emitted from the OLED 130 is colored based on the optical resonator and the color filter and is seen by the observer. In addition, the illustration of the optical resonator is omitted. In addition, when the electro-optical device 10 displays only a monochrome image of light and dark, the above color filter is omitted.

[0065] In the transistor 121 of the pixel circuit 110 at the i-th row and j-th column, the gate node g is connected to the drain node of the transistor 122, the source node s is connected to the power supply line 116, which is a power supply wiring supplied with the potential Vel, and the drain node d is connected to the source node of the transistor 123 and the source node of the transistor 124. One end of the capacitor element 140 is connected to the gate node g of the transistor 121, and the other end is connected to the power supply line 116. Therefore, the capacitor element 140 holds the voltage between the gate node g and the source node s in the transistor 121.

[0066] In addition, as long as the potential of the other end of the capacitor element 140 remains substantially constant, it may also be connected to other power supply lines other than the power supply line 116.

[0067] In the present embodiment, as the capacitor element 140, for example, a so-called MOS capacitor formed by sandwiching a gate insulating layer of a transistor between a semiconductor layer and a gate electrode layer of the transistor is used. In addition, as the capacitor element 140, the parasitic capacitance of the gate node g of the transistor 121 may also be used, and a so-called metal capacitor formed by sandwiching an insulating layer with different conductive layers in a semiconductor substrate may also be used.

[0068] In the transistor 122 of the pixel circuit 110 in the i-th row and j-th column, the gate node is connected to the scanning line 12 of the i-th row, and the source node is connected to the data line 14 of the j-th column. In the transistor 123 of the pixel circuit 110 in the i-th row and j-th column, the gate node is supplied with the control signal / Gcmp(i), and the drain node is connected to the data line 14 of the j-th column. In the transistor 124 of the pixel circuit 110 in the i-th row and j-th column, the gate node is supplied with the control signal / Gel(i), and the drain node is connected to the pixel electrode 131 serving as the anode of the OLED 130 and the drain node of the transistor 125.

[0069] In the transistor 125 of the pixel circuit 110 in the i-th row and j-th column, the gate node is supplied with the control signal / Gorst(i), and the source node is connected to the power supply line supplied with the potential Vorst.

[0070] In addition, the potential Vorst is, for example, the ground potential Gnd or a low potential close to the ground potential Gnd. Specifically, the potential Vorst is a potential at which no current flows through the OLED 130 when supplied to the pixel electrode 131 in the OLED 130. In addition, the potential Vct is supplied to the common electrode 133 that functions as the cathode of the OLED 130.

[0071] Figure 4 It is a circuit diagram showing the DA conversion circuit 500 corresponding to the j-th column.

[0072] Bits D0 to D9 are supplied from the second latch circuit L2 of the j-th column to the DA conversion circuit 500 of the j-th column. In addition, the control signals Enb0 to Enb9 and the control signal / Rst are supplied from the control circuit 30 to the DA conversion circuit 500 of the j-th column, and the potentials Vrst, VL, VPL, and VPH are supplied from the power supply circuit 15 to the DA conversion circuit 500 of the j-th column.

[0073] Bits D0 to D9 are 10 bits of the video data Vdata output from the second latch circuit L2 in the j-th column, and are the target data to be converted by the DA conversion circuit 500. The lowest bit among these 10 bits is D0, and starting from this bit D0, the weights increase in sequence as D1, D2, ……, and the highest bit is D9.

[0074] The control signals Enb0 to Enb9 are signals that sequentially specify the timing for taking in bits D0 to D9. The control signal / Rst is a signal for resetting the capacitor elements.

[0075] As shown in the figure, the DA conversion circuit 500 includes capacitor elements C0 to C9, Cser, switch Rsw, and selection circuits 510 to 519. The capacitor elements C0 to C9 and the selection circuits 510 to 519 are paired as follows corresponding to each bit. Specifically, corresponding to bit D0, the selection circuit 510 is paired with the capacitor element C0, corresponding to bit D1, the selection circuit 511 is paired with the capacitor element C1, and so on. Corresponding to bit D9, the selection circuit 519 is paired with the capacitor element C9.

[0076] In addition, in the present embodiment, among the 10 bits of the video data Vdata, bits D5 to D9 are an example of high-order bits, and bits D0 to D4 are an example of low-order bits.

[0077] The selection circuits 510 to 514 corresponding to the low-order bits select the potential VL or VPL and supply the selected potential to one end of the corresponding capacitor element. In addition, the selection circuits 515 to 519 corresponding to the high-order bits select the potential VL or VPH and supply the selected potential to one end of the corresponding capacitor element.

[0078] For example, the selection circuit 510 corresponding to bit D0 takes in bit D0 at the timing specified by the control signal Enb0, selects the potential VL or VPL according to the logic level of the taken-in bit D0, and supplies the selected potential to one end of the capacitor element C0. And for example, the selection circuit 516 corresponding to bit D6 takes in bit D6 at the timing specified by the control signal Enb6, selects the potential VL or VPH according to the logic level of the taken-in bit D6, and supplies the selected potential to one end of the capacitor element C6.

[0079] The capacitance values of the capacitor elements C0 to C9 are in the following ratio in the present embodiment. Specifically, if the capacitance value of the capacitor element C0 is set to “1”, then the capacitance values of the capacitor elements C1, C2, C3, C4, C5, C6, C7, C8, C9 are “2”, “4”, “8”, “16”, “1”, “2”, “4”, “8”, “16” in sequence.

[0080] When considering the 10 bits as a whole, the weights of bits D0 to D9 are "1", "2", "4", "8", "16", "32", "64", "128", "256", "512" in sequence. Therefore, the capacitance values of capacitor elements C0 to C9 do not match the weights. However, when bits D0 to D9 are divided into lower bits D0 to D4 and higher bits D5 to D9, if bit D5 in bits D5 to D9 is set as the lowest bit and the weight is regarded as "1", then the weights of bits D5 to D9 are "1", "2", "4", "8", "16" in sequence. In this description, it is also necessary to consider the case where bits D0 to D9 are divided into lower bits D0 to D4 and higher bits D5 to D9, so it is expressed that capacitor elements C0 to C9 have capacitance values corresponding to the weights of bits D0 to D9.

[0081] In addition, capacitor element Cser is an example of a coupling capacitor, and the capacitance value of this capacitor element Cser is "1" in the first embodiment. In addition, regarding the capacitance values of capacitor elements C0 to C9 and Cser, as long as the linearity described later is maintained, a certain degree of error is allowed.

[0082] In this embodiment, since MOS capacitors are used as capacitor elements 140 in pixel circuit 110, it is preferable to also use MOS capacitors for capacitor elements C0 to C9 and Cser, but metal capacitors can also be used.

[0083] The other ends of capacitor elements C0 to C4 corresponding to the lower 5 bits among capacitor elements C0 to C9 are electrically connected to one end of capacitor element Cser. For convenience, the connection line between the other ends of capacitor elements C0 to C4 and one end of capacitor element Cser is described as relay line 14b. In addition, the other ends of capacitor elements C5 to C9 corresponding to the higher 5 bits among capacitor elements C0 to C9 are electrically connected to the output terminal Out of DA conversion circuit 500, i.e., data line 14 and the other end of capacitor element Cser.

[0084] In addition, in this description, "electrically connected" means a direct or indirect connection or combination between two or more elements, and also includes, for example, in a semiconductor substrate, a case where two or more elements are not directly connected but are connected via different wiring layers and contact holes.

[0085] Between the power supply line of potential Vrst and relay line 14b, switch Rsw becomes in an on state or an off state according to control signal / Rst. Specifically, switch Rsw becomes in an on state when control signal / Rst is at L level and becomes in an off state when control signal / Rst is at H level.

[0086] In this description, the "on / conducting state" of a switch or a transistor means that the two ends of the switch, or the source node / drain node in the transistor, are electrically closed to form a low-impedance state. Additionally, the "off / cut-off state" of a switch or a transistor means that the two ends of the switch, or the source node / drain node, are electrically open to form a high-impedance state.

[0087] The switch Rsw is preferably composed of a NOT circuit Lg0 that outputs the negative signal of the output control signal / Rst and a transmission gate Tg0. The transmission gate Tg0 is an analog switch formed by combining an n-type transistor that supplies the negative signal based on the NOT circuit Lg0 to the gate node and a p-type transistor that supplies the control signal / Rst to the gate node.

[0088] The selection circuit 510 paired with the capacitor element C0 includes an AND circuit Ds, a level shifter Ls, and a selector Sel. Among them, the AND circuit Ds outputs the logical AND signal of the bit D0 of the image data Vdata output from the second latch circuit L2 in the j-th column and the control signal Enb0 supplied from the control signal 30. The AND circuit Ds is actually composed of a NAND circuit Lg1 that outputs the NAND signal of the bit D0 and the control signal Enb0 and a NOT circuit Lg2 that outputs the negative signal of the NAND signal.

[0089] The level shifter Ls converts the logical amplitude of the logical AND signal output from the AND circuit Ds, outputs a positive-phase signal that maintains the logical level of the logical AND signal from the output terminal Out, and outputs an inverted-phase signal obtained by inverting the logical level of the logical AND signal from the output terminal / Out. Additionally, the power supply potentials of the level shifter Ls are not particularly shown, but are Vddh and Vssh. Therefore, in the positive-phase signal or inverted-phase signal output from the level shifter Ls, the H level is the potential Vddh, and the L level is the potential Vssh.

[0090] If the positive-phase signal output from the level shifter Ls is at the H level and the inverted-phase signal is at the L level, the selector Sel in the selection circuit 510 selects the potential VPL. That is, if the bit D0 is "1" (H level) and the control signal Enb0 is at the H level, the selector Sel selects the potential VPL.

[0091] Additionally, if the positive-phase signal output from the level shifter Ls is at the L level and the inverted-phase signal is at the H level, the selector Sel selects the potential VL. That is, if the bit D0 is "0" (L level) or the control signal Enb0 is at the L level, the selector Sel selects the potential VL.

[0092] The selector Sel is actually composed of a transmission gate Tg1 provided between a power supply line at potential VPL and one end of a capacitor element C0, and a transmission gate Tg2 provided between a power supply line at potential VL and one end of the capacitor element C0.

[0093] In this structure, if the positive-phase signal output from the level shifter Ls is at the H level and the anti-phase signal is at the L level, the transmission gate Tg1 becomes conductive and the transmission gate Tg2 becomes non-conductive. If the positive-phase signal output from the level shifter Ls is at the L level and the anti-phase signal is at the H level, the transmission gate Tg1 becomes non-conductive and the transmission gate Tg2 becomes conductive.

[0094] Here, the selection circuit 510 paired with the capacitor element C0 has been described. However, regarding the other selection circuits 511 to 514 corresponding to the lower bits, except that the input signal bits D1 to D4 and the control signals Enb1 to Enb4 are different, they have the same structure as the selection circuit 510.

[0095] In addition, regarding the selection circuits 515 to 519 corresponding to the higher bits, except that the potential VPH is selected when the positive-phase signal output from the level shifter Ls is at the H level and the anti-phase signal is at the L level, and the input signal bits D5 to D9 and the control signals Enb5 to Enb9 are different, they have the same structure as the selection circuits 510 to 514.

[0096] Figure 5 It is a diagram showing the equivalent circuit in the DA conversion circuit 500 of the j-th column.

[0097] The selection circuit 510 is described as a single-pole double-throw switch. If the logical AND signal (D0·Enb0) of the bit D0 and the control signal Enb0 is at the L level, the potential VL is selected. If this logical AND signal is at the H level, the potential VPL is selected. Regarding the selection circuits 511 to 514, they are also described as single-pole double-throw switches similar to the selection circuit 510.

[0098] The selection circuit 515 is described as a single-pole double-throw switch. If the logical AND signal (D5·Enb5) of the bit D5 and the control signal Enb5 is at the L level, the potential VL is selected. If this logical AND signal is at the H level, the potential VPH is selected. Regarding the selection circuits 516 to 519, they are also described as single-pole double-throw switches similar to the selection circuit 515.

[0099] In Figure 4 and Figure 5 the DA conversion circuit 500 of the j-th column has been described, but the DA conversion circuits 500 corresponding to other columns also have the same structure. In addition, Figure 4 and Figure 5Only the electrical structure is shown, and the positions and arrangements of the elements constituting the DA conversion circuit 500 are not shown.

[0100] The operation of the DA conversion circuit 500 is divided into a reset period and an output period. In addition, the reset period of the DA conversion circuit 500 is the initialization period (a) and the compensation period (b) during the operation period of the electro-optical device 10 described later, and the output period of the DA conversion circuit 500 is the writing period (c) of the operation period of the electro-optical device 10.

[0101] In the DA conversion circuit 500, during the reset period, the switch Rsw is turned on, and in addition, the selection circuits 510 to 519 select the potential VL. In addition, at the end of the reset period, through the elements not shown in Figure 5 the data line 14 at the output terminal Out becomes a potential substantially the same as the potential Vrst, specifically, a voltage corresponding to the threshold value of the transistor 121 described later. Therefore, charges corresponding to the capacitance values are accumulated in the capacitor elements C0 to C9.

[0102] During the output period of the DA conversion circuit 500, the selection circuits 510 to 514 maintain the selection of the potential VL when the corresponding logical AND signal is at the L level, and select the potential VPL when the corresponding logical AND signal is at the H level. In addition, during the output period, the selection circuits 515 to 519 maintain the selection of the potential VL when the corresponding logical AND signal is at the L level, and select the potential VPH when the corresponding logical AND signal is at the H level. As described later, at the end of the output period, the control signals Enb0 to Enb9 are at the H level, so the selection circuits 510 to 519 select the potential VL or VPL (or VPH) according to the logical levels of the bits D0 to D9.

[0103] That is, during the output period, the voltage at one end of the capacitor elements C0 to C9 becomes either changing (increasing) or maintaining according to the bits D0 to D9. Therefore, at the other end of the capacitor elements C0 to C9 in which the voltage at one end has changed, the voltage rises corresponding to the capacitance value from the voltage at the end of the reset period due to the discharge of the accumulated charge.

[0104] At the other end of the capacitor elements C5 to C9 corresponding to the high-order bits, the voltage of the data line 14 rises according to the capacitance value. On the other hand, the other end of the relay line 14b of the capacitor elements C0 to C4 corresponding to the low-order bits is connected to the data line 14 via the capacitor element Cser, so the voltage change of the relay line 14b is compressed at a ratio determined by the capacitor elements C0 to C4 and Cser, causing the voltage change of the data line 14. If this ratio is described as the compression ratio k, this compression ratio k is expressed by the following formula (1).

[0105] k = Cser / (Cser + C0 + C1 + C2 + C3 + C4)……(1)

[0106] In addition, in the first embodiment, the compression ratio k is 1 / 32 (= 1 / (1 + 1 + 2 + 4 + 8 + 16)).

[0107] In Figure 5 , the circuit including the capacitor elements C5 to C9 and the selection circuits 515 to 519 is referred to as the first DA conversion circuit section Upb. Among them, the capacitor elements C5 to C9 are an example of the high-order capacitor element section, and the selection circuits 515 to 519 are an example of the high-order switch element section. Such a first DA conversion circuit section Upb outputs the voltages corresponding to the bits D5 to D9 to the data line 14.

[0108] Similarly, the circuit including the capacitor elements C0 to C4 and the selection circuits 510 to 514 is referred to as the second DA conversion circuit section Lwb. Among them, the capacitor elements C0 to C4 are an example of the low-order capacitor element section, and the selection circuits 510 to 514 are an example of the low-order switch element section. Such a second DA conversion circuit section Lwb outputs the voltages corresponding to the bits D0 to D4 to the relay line 14b. However, the voltage change of the relay line 14b is compressed to 1 / 32 of the compression ratio k and output to the data line 14.

[0109] Therefore, even if the bits D0 to D4 are the same as the bits D5 to D9 in sequence, the voltage change of the data line 14 caused by the second DA conversion circuit section Lwb is 1 / 32 of the voltage change of the data line 14 caused by the first DA conversion circuit section Upb.

[0110] Therefore, the DA conversion circuit 500 causes the voltage change of the data line 14 from the end of the reset period to correspond to the weights of the bits D0 to D9.

[0111] Figure 6 is a timing chart for explaining the operation of the electro-optical device 10.

[0112] In the electro-optical device 10, the m scanning lines 12 of the m rows are each scanned one row in the order of the 1st, 2nd, 3rd, ……, mth rows during the frame (V). Specifically, as shown in the figure, the scanning signals / Gwr(1), / Gwr(2), ……, / Gwr(m - 1), / Gwr(m) sequentially and exclusively become the L level through the scanning line driving circuit 120 during each horizontal scanning period (H).

[0113] In addition, in the present embodiment, among the scan signals / Gwr(1) to / Gwr(m), the periods during which adjacent scan signals become the L level are separated in time. Specifically, after the scan signal / Gwr(i - 1) changes from the L level to the H level, the next scan signal / Gwr(i) becomes the L level after an intervening period. This period corresponds to the horizontal blanking period.

[0114] In this description, the period of 1 frame (V) refers to the period required to display one frame of the image specified by the video data Vid. Regarding the length of the period of 1 frame (V), if it is the same as the vertical synchronization period, and for example, if the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz, it is 16.7 milliseconds corresponding to one cycle of the vertical synchronization signal. In addition, the horizontal scanning period (H) is the interval of time during which the scan signals / Gwr(1) to / Gwr(m) sequentially become the L level, but for convenience in the figure, the start timing of the horizontal scanning period (H) is set to approximately the center of the horizontal blanking period.

[0115] In the electro - optical device 10, one horizontal scanning period (H) is mainly divided into three periods: an initialization period (a), a compensation period (b), and a writing period (c). In addition, as the operation of the pixel circuit 110, a light - emitting period (d) is added in addition to the above three periods.

[0116] During the initialization period (a) in each horizontal scanning period (H), the control signal / Gini is at the L level, the control signal / Rst is at the L level, and the control signal Enb is at the L level. In addition, the control signal Enb is a signal that collectively refers to the control signals Enb0 to Enb9. As will be described later, the control signals Enb0 to Enb9 are phase - shifted in sequence during the writing period (c), but since they have the same waveform in other periods, they are collectively referred to as the control signal Enb.

[0117] During the compensation period (b), the control signal / Gini is at the H level, and the control signals / Rst and Enb remain at the L level.

[0118] During the writing period (c), the control signal / Gini remains at the H level, and the control signals / Rst and Enb become the H level.

[0119] Regarding the operation during the horizontal scanning period (H), it will be described by taking the i - th row as an example. In addition, regarding the pixel circuit 110, the pixel circuit 110 at the i - th row and j - th column will be taken as an example.

[0120] During the horizontal scan period (H) of the i-th row, before the scan signal / Gwr(i) becomes the L level, the initialization period (a) of the i-th row starts. The initialization period (a) is a period for resetting the voltage or charge remaining in each part during the horizontal scan period (H) of the (i - 1)-th row.

[0121] Figure 7 It is a diagram for explaining the operations of the pixel circuit 110 at the i-th row and j-th column and the DA conversion circuit 500 corresponding to the data line 14 of the j-th column during the initialization period (a) of the i-th row.

[0122] During the initialization period (a), since the transistor 66 becomes conductive due to the control signal / Gini becoming the L level, the data line 14 is initialized to the potential Vini. In addition, during the initialization period (a), since the switch Rsw becomes closed due to the control signal / Rst becoming the L level, the relay line 14b becomes the potential Vrst. During the initialization period (a), the control signal Enb is at the L level. Therefore, regardless of the logic levels of the bits D0 to D9 output from the second latch circuit L2, the logical AND signals of the AND circuits Ds in the selection circuits 510 to 519 become the L level. Thus, the selection circuits 510 to 519 respectively select the potential VL.

[0123] Therefore, during the initialization period (a), one end of the capacitor elements C0 to C9 becomes the potential VL, one end of the capacitor element Cser and the other ends of the capacitor elements C0 to C4 become the potential Vrst, and the other end of the capacitor element Cser and the other ends of the capacitor elements C5 to C9 become the applied potential Vini via the data line 14. In this way, during the initialization period (a), while the data line 14 is initialized, the charges stored in the capacitor elements C0 to C9 and Cser are initialized.

[0124] In addition, during the initialization period (a) of the i-th row, the control signal / Gel(i) becomes the H level and the control signal / Gorst(i) becomes the L level. Therefore, in the pixel circuit 110 of the i-th row, the transistor 124 becomes the cut-off state and the transistor 125 becomes the conductive state. So, the anode of the OLED 130, i.e., the pixel electrode 131, becomes the potential Vorst. Therefore, the OLED 130 is turned off, and the pixel electrode 131 is reset to the potential Vorst.

[0125] In addition, since there is parasitic capacitance in the OLED 130, resetting the pixel electrode 131 is to eliminate the influence of the voltage applied during the immediately preceding light-emitting period.

[0126] After the end of (a) during initialization, it becomes the compensation period (b). The compensation period (b) is a period for causing the gate nodes g of the respective transistors 121 in the n pixel circuits 110 located in the i-th row to converge to a voltage equivalent to the threshold of the transistor 121.

[0127] Figure 8 It is a diagram for explaining the operations of the pixel circuit 110 at the i-th row and j-th column and the DA conversion circuit 500 corresponding to the data line 14 of the j-th column during the compensation period (b) of the i-th row.

[0128] During the compensation period (b), the transistor 66 becomes in the cut-off state by the control signal / Gini becoming the H level. Further, during the compensation period (b), the control signal / Rst is at the L level, so the on-state of the switch Rsw is maintained, and the control signal Enb is at the L level, so the selection of the potential VL by the selection circuits 510 to 519 is maintained.

[0129] Further, during the compensation period (b) of the i-th row, the scan signal / Gwr(i) becomes the L level, and in this state of the L level, the control signal / Gcmp(i) becomes the L level. Therefore, in the pixel circuit 110 of the i-th row, the transistor 122 is in the on-state and the transistor 123 is in the on-state. Therefore, the transistor 121 becomes in the diode-connected state, so the voltage between the gate node and the source node in this transistor 121 converges to a voltage equivalent to the threshold of the transistor 121 (threshold-equivalent voltage).

[0130] During the compensation period (b) of the i-th row, the transistors 122 and 123 in the pixel circuit 110 are in the on-state, so the other ends of the capacitor element Cser and the other ends of the capacitor elements C5 to C9 also converge to the threshold-equivalent voltage of the transistor 121 via the data line 14.

[0131] In addition, during the compensation period (b), one ends of the capacitor elements C0 to C9 are maintained at the potential VL by the selection circuits 510 to 519, and one end of the capacitor element Cser and the other ends of the capacitor elements C0 to C4 are maintained at the potential Vrst by the on-state of the switch Rsw. Further, during the compensation period (b) of the i-th row, in the pixel circuit 110 of the i-th row, the cut-off state of the transistor 124 and the on-state of the transistor 125 continue from the initialization period (a).

[0132] The potential Vrst is set to the average threshold-equivalent voltage of the transistors 121 in each column. Therefore, at the end of the compensation period (b), the voltages applied across the capacitor elements C0 to C4 are substantially the same as the voltages applied across the capacitor elements C5 to C9. Therefore, it can be considered that during the compensation period (b), charges corresponding to the capacitance values are accumulated in the capacitor elements C0 to C9.

[0133] After the compensation period (b) ends, it becomes the writing period (c). The writing period (c) is a period in which a voltage corresponding to the luminance is applied to the gate nodes g of the respective transistors 121 in the pixel circuit 110 at the n-th column in the i-th row.

[0134] Figure 9 It is a diagram for explaining the operations of the pixel circuit 110 at the i-th row and j-th column and the DA conversion circuit 500 corresponding to the data line 14 of the j-th column during the writing period (c) of the i-th row.

[0135] During the writing period (c), the control signal / Rst becomes the H level, so the switch Rsw becomes the off state. Also, during the writing period (c), after the control signal Enb0 becomes the H level as shown in Figure 6 , the control signals Enb1 to Enb9 become the H level in sequence with a delay time Δt. Also, when the control signal Enb0 changes from the H level to the L level, the control signals Enb1 to Enb9 become the L level in sequence with a delay time Δt. Also, at the timing before all of the control signals Enb0 to Enb9 are the H level and the control signal Enb0 is about to change from the H level to the L level, the writing period (c) ends.

[0136] The period in which the bit D0 in the video data output from the second latch circuit L2 of the j-th column is input to the level shifter Ls of the selection circuit 510 is limited by the AND circuit Ds to the period in which the control signal Enb0 is the H level. Similarly, the periods in which the bits D1 to D9 are sequentially input to the level shifters Ls in the selection circuits 511 to 519 are sequentially limited by the AND circuit Ds to the periods in which the control signals Enb1 to Enb9 are the H level. Therefore, the bits D0 to D9 are taken into the selection circuits 510 to 519 not simultaneously but with a delay time Δt in sequence.

[0137] In the selection circuits 510 to 514, the selection circuits in which the bit input to the level shifter Ls is "1" select the potential VPL, and the selection circuits in which the bit is "0" select the potential VL. In addition, in the selection circuits 515 to 519, the selection circuits in which the bit input to the level shifter Ls is "1" select the potential VPH, and the selection circuits in which the bit is "0" select the potential VL.

[0138] During the writing period (c), one end of the capacitor elements C0 to C9 corresponding to the bit of "0" input to the level shifter Ls does not change in voltage since the compensation period (b), so it does not contribute to the voltage rise of the data line 14.

[0139] Among the capacitor elements C5 to C9 corresponding to the high-order 5 bits, one end of the capacitor element corresponding to the bit of "1" input to the level shifter Ls changes from the potential VL to the potential VPH during the writing period (c). Therefore, the capacitor elements among the capacitor elements C5 to C9 corresponding to the bit of "1" cause the data line 14 to rise from the threshold equivalent voltage during the compensation period (b) by an amount corresponding to the weight of the capacitance value.

[0140] Among the capacitor elements C0 to C4 corresponding to the low-order 5 bits, one end of the capacitor element corresponding to the bit of "1" input to the level shifter Ls changes from the potential VL to the potential VPL during the writing period (c). However, the other end of the capacitor elements C0 to C4 is different from the other end of the capacitor elements C5 to C9, and there is a capacitor element Cser between it and the data line 14. Therefore, the change amount of one end of the capacitor element corresponding to the bit of "1" among the capacitor elements C0 to C4 from the potential VL to the potential VPL is compressed by the compression ratio k, causing the voltage of the data line 14 to rise.

[0141] In this way, during the writing period (c), the DA conversion circuit 500 of the j-th column causes the data line 14 of the j-th column to rise from the threshold equivalent voltage by an amount corresponding to the bits D0 to D9 of the image data Vdata of the i-th row and j-th column, that is, the amount of voltage that specifies the brightness of the OLED of the i-th row and j-th column.

[0142] In the present embodiment, during the writing period (c), the control signals Enb0 to Enb9 are sequentially delayed by the time Δt during the period when they become the H level. The reason is that if the control signals Enb0 to Enb9 are set to the H level all at once, the switching from the potential VL to VPL or VPH occurs simultaneously, and the peak variation accompanying the voltage switching increases and propagates to various parts, especially to the data line 14, thereby reducing the DA conversion accuracy. Therefore, in the present embodiment, the phases of the control signals Enb0 to Enb9 are sequentially staggered to avoid the simultaneous switching from the potential VL to VPL or VPH.

[0143] According to the present embodiment, the influence of the voltage variation caused by the peak accompanying the voltage switching is reduced, so the reduction of the DA conversion accuracy can be suppressed. In addition, the order in which the control signals Enb0 to Enb9 become the H level does not need to be the order of the control signals Enb0 to Enb9.

[0144] During the writing period (c) of the i-th row, in the pixel circuit 110 of the i-th row and j-th column, the transistor 122 remains in the conducting state and the transistor 123 becomes in the cut-off state. Therefore, the potential Vd(j) output from the DA conversion circuit 500 of the j-th column is supplied to the gate node g of the transistor 121 via the data line 14.

[0145] In addition, during the writing period (c) of the i-th row, in the pixel circuit 110 of the i-th row, the off state of the transistor 124 and the on state of the transistor 125 continue.

[0146] When the scan signal / Gwr(i) changes to the H level, the writing period (c) of the i-th row ends. If the scan signal / Gwr(i) becomes the H level, the transistor 122 becomes off in the pixel circuit 110 at the i-th row and j-th column, but the voltage of the difference between the potential Vd(j) of the gate node g and the potential Vel is held in the capacitor element 140. In addition, in Figure 9 the voltage of the difference between the potential Vd(j) of the gate node g and the potential Vel is described as Vgs. In addition, this figure shows the case where all of the bits D0 to D9 of the video data output from the second latch circuit L2 are "1".

[0147] After the writing period (c) ends, the light-emitting period (d) begins. The light-emitting period (d) is a period for causing a current corresponding to the voltage Vgs held during the writing period (c) to flow through the OLED 130 to cause it to emit light.

[0148] Figure 10 is a diagram for explaining the operation of the pixel circuit 110 at the i-th row and j-th column during the light-emitting period (d) of the i-th row.

[0149] Before the light-emitting period (d) of the i-th row, the control signal / Gorst(i) becomes the H level, so the transistor 125 becomes off. In addition, when the light-emitting period (d) of the i-th row is reached, the control signal / Gel(i) is inverted to the L level, so the transistor 124 becomes on. Therefore, in the OLED 130, a current Ids corresponding to the voltage Vgs held by the capacitor element 140 flows through the transistor 121. Therefore, the OLED 130 becomes an optical state corresponding to this current Ids, that is, a state of emitting light with a brightness corresponding to the current Ids.

[0150] In addition, Figure 10 is an example where there are consecutive light-emitting periods (d) after the selection of the scan line 12 of the i-th row ends, but the period during which the control signal / Gel(i) becomes the L level can also be intermittent and can also be adjusted according to the brightness adjustment. In addition, the level of the control signal / Gel(i) during the light-emitting period (d) can be made higher than the L level during the compensation period (b). That is, for the level of the control signal / Gel(i) during the light-emitting period (d), an intermediate level between the H level and the L level can also be used.

[0151] In addition, during the light-emitting period (d) of the i-th row, the DA conversion circuit 500 corresponding to the j-th column sometimes performs the operation during the horizontal scan period (H) for other rows than the i-th row. Therefore, in Figure 10The DA conversion circuit 500 is omitted.

[0152] In Figures 7 to 9 during the horizontal scan (H) of the i-th row, focusing on the DA conversion circuit 500 corresponding to the j-th column and the pixel circuit 110 at the i-th row and j-th column, the same operations are performed on the DA conversion circuits 500 and pixel circuits 110 corresponding to columns other than the j-th column.

[0153] In addition, in Figures 7 to 9 during the horizontal scan (H) of the i-th row, the operations during this horizontal scan (H) are described, but the same operations are sequentially performed during the horizontal scans (H) of the 1st, 2nd, 3rd, ……, m-th rows.

[0154] In the pixel circuit 110, the voltage Vgs during the writing period (c) and the light-emitting period (d) is a voltage that changes from the threshold voltage during the compensation period (b) according to the gray level of this pixel circuit 110. Since the same operations are also performed in other pixel circuits 110, in the first embodiment, with the thresholds of the transistors 121 compensated for all the m×n pixel circuits 110, a current corresponding to the gray level flows through the OLED 130. Therefore, in this embodiment, the deviation of the luminance is reduced, and as a result, high-quality display can be achieved.

[0155] However, in the actual electro-optical device 10, capacitances are parasitic in each part. For example, as Figure 4 or Figure 5 shown by the dotted line in, a capacitance Cp is parasitic in the relay line 14b. If the capacitance Cp is parasitic in the relay line 14b, when the potential at one end of the capacitor elements C0 to C4 changes from the potential VL to the potential VPL, a part of the charge discharged from the other end of the capacitor elements C0 to C4 is used for charging the capacitance Cp. That is, not all of the charge discharged from the other end of the capacitor elements C0 to C4 goes toward the capacitor element Cser, and a part of the charge leaks to the capacitance Cp.

[0156] Therefore, in this state, the second DA conversion circuit section Lwb does not change the potential of the relay line 14b from the potential Vrst to the potential corresponding to the weights of the bits D0 to D4. Therefore, the characteristic of changing the voltage of the data line 14 by compressing the voltage change of the relay line 14b at the compression ratio k (=1 / 32) does not match the characteristic of changing the voltage of the data line 14 by the first DA conversion circuit section Upb according to the weights of the bits D5 to D9.

[0157] Specifically, when the decimal value of the gray level indicated by the 10 bits of the bits D0 to D9 is taken as the horizontal axis and the amount of increase in the voltage of the data line 14 from the end of the reset period in the DA conversion circuit 500 is taken as the vertical axis, the voltage characteristic is as Figure 11The characteristic Vcr_b shown by a solid line in the figure. Specifically, when the gray level is represented in decimal, every 2 to the 5th power (=32), there is a linear disorder in the characteristic of the output voltage, and a rising part occurs.

[0158] In addition, the characteristic Vcr_b is an example in the case where the capacitance value of the capacitor element Cser is the same as that of the capacitor element C5 (C0) and VPL = VPH = 4.0V.

[0159] In Figure 11 For example, in the intervals of gray levels "0" to "31", "33" to "63", "65" to "95", "97" to "127",..., the linearity of the voltage characteristics is based on the result of compressing the output voltage from the second DA conversion circuit section Lwb by a compression ratio k. In addition, in Figure 11 For the discrete points of gray levels "32", "64", "96", "128",..., the voltages are the voltages output from the first DA conversion circuit section Upb. Therefore, as Figure 11 shown, the reason for the linear disorder of the voltage characteristics output from the DA conversion circuit 500 is that the slope of the voltage characteristic obtained by compressing the output voltage from the second DA conversion circuit section Lwb by the compression ratio k is reduced due to the influence of the capacitance Cp parasitic on the relay line 14b, and is inconsistent with the slope of the voltage characteristic output from the first DA conversion circuit section Upb that is not affected by the capacitance Cp.

[0160] Therefore, in the first embodiment, it is configured to set the potential VPL higher than the potential VPH, so as to compensate for the reduction of the slope of the characteristic obtained by compressing the output voltage from the second DA conversion circuit section Lwb by the compression ratio k due to the influence of the capacitance Cp parasitic on the relay line 14b.

[0161] Specifically, the potential VPL is set to 4.5V, and the potential VPH is set to 4.0V. The characteristic of the output voltage from the DA conversion circuit 500 based on this setting is like the characteristic Vcr_a shown by the solid line in Figure 12 In addition, the characteristic Vcr_b shown by the dotted line in Figure 12 is the characteristic Vcr_b shown by the solid line in Figure 11 and is described for comparison.

[0162] As Figure 12 shown, it can be seen that in the characteristic Vcr_a shown by the solid line, the linearity is improved compared with the characteristic Vcr_b shown by the dotted line.

[0163] If VPL and VPH are appropriately decreased while maintaining the relationship VPL > VPH, the slope of the voltage characteristic decreases in a state where the linearity of the characteristics in the output voltage is improved. On the contrary, if VPL and VPH are appropriately increased while maintaining the relationship VPL > VPH, the slope of the voltage characteristic increases in a state where the linearity of the voltage characteristic is improved. In Figure 12 In the example shown by the solid line in FIG. Figure 12 , the characteristic Vcr_c is an example where the potential VPL is set to 4.0 V and the potential VPH is set to 3.7 V, and is an example where the slope is smaller than that of the characteristic Vcr_a. In addition, if the slope of the output voltage characteristic increases, the voltage difference per bit increases, and it is easy to ensure the required voltage amplitude.

[0164] When the capacitor Cp is parasitic on the relay line 14b, if VPL = VPH, the linearity in the characteristic of the output voltage from the DA conversion circuit 500 is impaired, and the display quality of the electro-optical device 10 is deteriorated. On the other hand, according to the first embodiment, when the capacitor Cp is parasitic on the relay line 14b, VPL > VPH is set, so that the linearity in the characteristic of the output voltage from the DA conversion circuit 500 can be ensured, and the deterioration of the display quality of the electro-optical device 10 can be suppressed.

[0165] In addition, the potential VL is an example of the first potential, the potential VPH is an example of the second potential, and the potential VPL is an example of the third potential. That is, in the first embodiment, it is an example of a structure in which the potential VPL as the third potential is higher than the potential VPH as the second potential.

[0166] In addition, as a cause of the impairment of the linearity of the voltage characteristic in the DA conversion circuit 500, in addition to the capacitor Cp being parasitic on the relay line 14b, when MOS capacitors are used as the capacitor elements C0 to C4, the voltage dependence of the capacitance value can also be cited. Specifically, in a MOS capacitor, there is a property that the charge density in the depletion layer of the semiconductor layer used as an electrode changes according to the applied voltage, and thus the capacitance value varies. Even if there is such a voltage dependence of the capacitance value, in the present embodiment, the linearity of the voltage characteristic in the DA conversion circuit 500 can be ensured.

[0167] [Second Embodiment]

[0168] Next, the DA conversion circuit 500 of the second embodiment will be described. In addition, hereinafter, the same reference numerals are given to the same elements as those in the already described embodiments, and the detailed description thereof is omitted.

[0169] In the above-described first embodiment, the ratio of the capacitance value in the capacitor element Cser is set to "1", which is the same as the ratio of the capacitance value of the capacitor element C5 (C0), but it may also be set to a ratio other than "1". Specifically, the ratio of the capacitance value of the capacitor element Cser may be made greater than the ratio of the capacitance value of the capacitor element C5 (C0). However, if the capacitance value of the capacitor element Cser is greater than the capacitance value of the capacitor element C5 (C0), from Equation (1), the compression ratio k is greater than 1 / 32.

[0170] Therefore, in a structure in which only the ratio of the capacitance value in the capacitor element Cser is greater than "1", the linearity of the voltage characteristics output by the DA conversion circuit 500 is impaired.

[0171] Specifically, when the decimal values of 10 of the bits D0 to D9 are set as the horizontal axis and the amount of increase from the voltage of the data line 14 at the end of the reset period in the DA conversion circuit 500 is set as the vertical axis, the voltage characteristics are as Figure 13 shown by the dashed line Vcr_d in. That is, the output voltage drops every fifth power (=32) of the gray level of 2. In addition, the characteristics shown by the dashed line Vcr_d are an example in the case where VPL = VPH = 4.0V and the capacitance value of the capacitor element Cser is set to twice the capacitance value of the capacitor element C5 (C0).

[0172] If the output voltage drops like this, for example, in the case of the gray level of "31", the brightness of the display element should be darker than that of the display element in the case of the gray level of "32", but in reality, there will be an inversion phenomenon where the brightness of the display element with the gray level of "31" is brighter than that of the display element with the gray level of "32". Such an inversion phenomenon causes the light / dark corresponding to the gray level to be inverted in the display element and emit light with a dark / bright brightness, so it is sometimes also called gray level inversion. If an inversion phenomenon (gray level inversion) occurs, the display quality is greatly impaired.

[0173] Therefore, in the second embodiment, the capacitance value of the capacitive element Cser is set to, for example, twice the capacitance value of the capacitive element C5 (C0), and the potential VPL is set to be lower than the potential VPH, contrary to the first embodiment. If the capacitance value of the capacitive element Cser is twice the capacitance value of the capacitive element C5 (C0), the compression ratio k becomes 2 / 33 (= 1 / (2 + 1 + 2 + 4 + 8 + 16)). At this time, if the potential VPL is set to be lower than the potential VPH, among the bits D0 to D9, for example, only when the bits D0 and D5 are "1", the rising amount of the other end of the capacitive element C0 corresponding to the bit D0 is lower than the rising amount of the other end of the capacitive element C5 corresponding to the bit D5. Here, the relationship between the capacitive elements C0 and C5 has been described, but the same applies to other capacitive elements with the same capacitance ratio (specifically, between the capacitive elements C1 and C6, between the capacitive elements C2 and C7, between the capacitive elements C3 and C8, and between the capacitive elements C4 and C9).

[0174] In this way, when the potential VPL is lower than the potential VPH, the rising amount of the other end of the capacitive elements C0 to C4 is lower than the rising amount of the other end of the capacitive elements C5 to C9, and the influence brought about by the increase in the compression ratio k is offset. Therefore, when the potential VPL is appropriately set to be lower than the potential VPH, as shown by the solid line Vcr_e in Figure 13 , the linearity in the characteristics of the output voltage can be ensured, and the degradation of the display quality of the electro-optical device 10 can be suppressed.

[0175] In addition, in Figure 13 , the characteristics shown by the solid line Vcr_e are an example in the case where the capacitance value of the capacitive element Cser is set to twice the capacitance value of the capacitive element C5 (C0), the potential (voltage) VPL is set to 2.2 V, and the potential VPH is set to 4.0 V.

[0176] Based on the case where the potential VPL = the potential VPH, in order to make the potential VPL relatively lower than the potential VPH, a method of maintaining the potential VPL and making the potential VPH higher than the potential VPL is also considered. However, due to the structure of the power supply circuit 15, there are cases where the potential of the potential VPH cannot be increased, so the method of decreasing the potential VPL becomes effective.

[0177] In addition, in the second embodiment, it is an example of a structure in which the potential VPL as the third potential is a lower potential than the potential VPH as the second potential.

[0178] [Third Embodiment]

[0179] Next, the DA conversion circuit 500 of the third embodiment will be described.

[0180] Figure 14 This is a top view showing the arrangement of each element in the electro-optical device 10. Since the electro-optical device 10 is cut out from a wafer-shaped semiconductor substrate, it has a rectangular shape. Therefore, in the rectangular electro-optical device 10, the upper side is labeled Ue, the lower side is labeled De, the left side is labeled Le, and the right side is labeled Re.

[0181] In addition, in the rectangular electro-optical device 10, the upper side Ue and the lower side De are along the X direction which is the extending direction of the scanning line 12, and the left side Le and the right side Re are along the Y direction which is the extending direction of the data line 14. In addition, the top view in this description represents the case of observing the electro-optical device 10 in the direction opposite to the Z direction.

[0182] A scanning line driving circuit 120 is provided in the region between the display area 100 and the left side Le, and a scanning line driving circuit 120 is also provided in the region between the display area 100 and the right side Re. The two scanning line driving circuits 120 have the same structure and drive the scanning lines 12 etc. on the left and right. In the structure where the scanning line driving circuit 120 is only arranged on one side of the left and right, a signal delay occurs on the other side of the left and right. In contrast, in the structure where the scanning line driving circuits 120 are arranged on both the left and right, signal delay can be prevented.

[0183] In the electro-optical device 10, a plurality of terminals 20 for connecting to one end of the FPC substrate 194 are provided along the lower side De. In the region between the display area 100 and the plurality of terminals 20, an initialization circuit 60, circuits Rb, Bb, Gb, and a control circuit 30 are provided in sequence when viewed from the display area 100.

[0184] The circuit Rb is a circuit obtained by integrating the circuits in the data signal output circuit 50 corresponding to the data line 14 of R, including the selection circuit group 52, the first latch circuit group 54, the second latch circuit group 56, and the DA conversion circuit 500. The circuit Bb is a circuit obtained by integrating the output circuits in the data signal output circuit 50 corresponding to the data line 14 of B. The circuit Gb is a circuit obtained by integrating the output circuits in the data signal output circuit 50 corresponding to the data line 14 of G.

[0185] A power supply circuit 15 is provided in the region between the initialization circuit 60, circuits Rb, Bb, Gb, and the control circuit 30 and the left side Le, and a power supply circuit 15 is also provided in the region between the initialization circuit 60, circuits Rb, Bb, Gb, and the control circuit 30 and the right side Re. The two power supply circuits 15 have the same structure and supply various potentials and voltages to the scanning line driving circuit 120, the initialization circuit 60, circuits Rb, Bb, Gb, and the control circuit 30.

[0186] Figure 15 It is a top view showing the configuration of the pixel circuit 110 in the display area 100.

[0187] As shown in this figure, the pixel circuits 110 for R, the pixel circuits 110 for B, and the pixel circuits 110 for G are arranged along the X direction, and the pixel circuits 110 of the same color are arranged along the Y direction. Therefore, if we focus on any one column of data lines 14, they correspond to the pixel circuits 110 of the same color.

[0188] In addition, one color is represented by the additive mixing of the pixel circuits 110 of R, B, and G adjacent in the X direction. Therefore, strictly speaking, the pixel circuit 110 should be called a sub-pixel circuit, but in this description, as mentioned above, it is also possible to display a monochromatic image with only light and dark, so it is described as a pixel circuit without specific distinction.

[0189] In the figure, the width W is the arrangement interval of the data lines 14 when observed in the X direction. The width 3W is three times the width W, that is, it is the interval when taking three columns of data lines 14 required to display one color of color as a unit.

[0190] In addition, in the figure, in order to distinguish the data lines 14 by color, the label of the data line corresponding to the pixel circuit 110 of R is described as R14, the label of the data line corresponding to the pixel circuit 110 of B is described as B14, and the label of the data line corresponding to the pixel circuit 110 of G is described as G14.

[0191] Figure 16 It is a diagram showing the configuration of each element in the 6-column adjacent DA conversion circuits 500 in the circuit Rb, Bb, and Gb of the data signal output circuit 50. In addition, in this figure, the illustration of the selection circuit 520, the first latch circuit L1, and the second latch circuit L2 is omitted.

[0192] As shown in the figure, the DA conversion circuit 500 in the circuit Rb, the DA conversion circuit 500 in the circuit Bb, and the DA conversion circuit 500 in the circuit Gb are arranged in a column in sequence along the Y direction within a range wider than the width W and narrower than the width 3W.

[0193] Specifically, in the DA conversion circuit 500 of the circuit Rb, the first DA conversion circuit section Upb, the capacitor element Cser, and the second DA conversion circuit section Lwb are arranged in sequence along the Y direction. In other words, the capacitor element Cser is arranged between the first DA conversion circuit section Upb and the second DA conversion circuit section Lwb. One end of the capacitor element Cser in the circuit Rb is connected to the relay line R14b of R arranged along the Y direction, and the other end of the capacitor element Cser is connected to the data line R14 of R.

[0194] The potentials VPH_R, VL_R, and VPL_R are supplied to the first DA conversion circuit section Upb and the second DA conversion circuit section Lwb of the circuit Rb via respective power supply lines extending in the X direction. Specifically, in the circuit Rb, the potentials VPH_R and VL_R are supplied to the first DA conversion circuit section Upb, and the potentials VL_R and VPL_R are supplied to the second DA conversion circuit section Lwb. The potential VPH_R is a potential obtained by making the potential VPH, which is described without limiting the color, dedicated to R, and is supplied adjustably by the power supply circuit 15. Similarly, the potential VL_R is a potential obtained by making the potential VL, which is described without limiting the color, dedicated to R, and the potential VPL_R is a potential obtained by making the potential VPL, which is described without limiting the color, dedicated to R, and both are supplied adjustably by the power supply circuit 15.

[0195] In addition, in the first DA conversion circuit section Upb of the circuit Rb, in addition to the potentials VPH_R and VL_R, for example, bits D5 to D9 and control signals Enb5 to Enb9 are supplied from below in the figure via respective wirings provided along the Y direction, but illustration thereof is omitted. Further, in the second DA conversion circuit section Lwb of the circuit Rb, in addition to the potentials VL_R and VPL_R, bits D0 to D4 and control signals Enb0 to Enb4 are supplied, for example, via respective wirings provided along the Y direction in the figure, and the potential Vrst and the control signal / Rst are supplied via respective wirings provided along the X direction, but illustration thereof is omitted.

[0196] In the circuit Bb, the first DA conversion circuit section Upb, the capacitor element Cser, and the second DA conversion circuit section Lwb are arranged in this order along the Y direction. One end of the capacitor element Cser in the circuit Bb is connected to the relay line B14b of B provided along the Y direction, and the other end of the capacitor element Cser is connected to the data line B14 of B.

[0197] The potentials VPH_B, VL_B, and VPL_B are supplied to the first DA conversion circuit section Upb and the second DA conversion circuit section Lwb of the circuit Bb via respective power supply lines extending in the X direction. Specifically, in the circuit Bb, the potentials VPH_B and VL_B are supplied to the first DA conversion circuit section Upb, and the potentials VL_B and VPL_B are supplied to the second DA conversion circuit section Lwb. The potential VPH_B is a potential obtained by making the potential VPH dedicated to B, and is supplied adjustably by the power supply circuit 15. Similarly, the potential VL_B is a potential obtained by making the potential VL dedicated to B, and the potential VPL_B is a potential obtained by making the potential VPL dedicated to B, and both are supplied adjustably by the power supply circuit 15.

[0198] In addition, in the first DA conversion circuit section Upb of the circuit Bb, in addition to the potentials VPH_B and VL_B, for example, bits D5 to D9 and control signals Enb5 to Enb9 are also supplied from below in the figure via respective wirings arranged along the Y direction, but the illustration thereof is omitted. Further, in the second DA conversion circuit section Lwb of the circuit Bb, in addition to the potentials VL_B and VPL_B, bits D0 to D4 and control signals Enb0 to Enb4 are supplied, for example, via respective wirings arranged along the Y direction in the figure, and the potential Vrst and the control signal / Rst are supplied via respective wirings arranged along the X direction, but the illustration thereof is omitted.

[0199] In the circuit Gb, the first DA conversion circuit section Upb, the capacitor element Cser, and the second DA conversion circuit section Lwb are arranged in sequence along the Y direction. One end of the capacitor element Cser in the circuit Gb is connected to the relay line G14b of G arranged along the Y direction, and the other end of the capacitor element Cser is connected to the data line G14 of G.

[0200] The potentials VPH_G, VL_G, and VPL_G are supplied to the first DA conversion circuit section Upb and the second DA conversion circuit section Lwb of the circuit Gb via respective power supply lines extending along the X direction. Specifically, in the circuit Gb, the potential VPH_G and VL_G are supplied to the first DA conversion circuit section Upb, and the potential VL_G and VPL_G are supplied to the second DA conversion circuit section Lwb. The potential VPH_G is a potential dedicated to G for the potential VPH, and is supplied adjustably by the power supply circuit 15. Similarly, the potential VL_G is a potential dedicated to G for the potential VL, and the potential VPL_G is a potential dedicated to G for the potential VPL, and both are supplied adjustably by the power supply circuit 15.

[0201] In addition, in the first DA conversion circuit section Upb of the circuit Gb, in addition to the potentials VPH_G and VL_G, for example, bits D5 to D9 and control signals Enb5 to Enb9 are also supplied from below in the figure via respective wirings arranged along the Y direction, but the illustration thereof is omitted. Further, in the second DA conversion circuit section Lwb of the circuit Gb, in addition to the potentials VL_G and VPL_G, bits D0 to D4 and control signals Enb0 to Enb4 are supplied, for example, via respective wirings arranged along the Y direction in the figure, and the potential Vrst and the control signal / Rst are supplied via respective wirings arranged along the X direction, but the illustration thereof is omitted.

[0202] In such a structure, in the first DA conversion circuit section Upb of the circuit Rb, in addition to the data line R14 corresponding to its own color, it also crosses the data lines B14 and G14 of other colors. Similarly, in the second DA conversion circuit section Lwb of the circuit Rb, in addition to the relay line R14b corresponding to its own color, it also crosses the data lines B14 and G14 of other colors.

[0203] In the first DA conversion circuit section Upb of the circuit Bb, in addition to the data line B14 corresponding to its own color, it also crosses the relay line R14b of other colors and the data line G14. Similarly, in the second DA conversion circuit section Lwb of the circuit Bb, in addition to the relay line B14b corresponding to its own color, it also crosses the relay line R14b of other colors and the data line G14.

[0204] In the first DA conversion circuit section Upb of the circuit Gb, in addition to the data line G14 corresponding to its own color, it also crosses the relay lines R14b and B14b of other colors. Similarly, in the second DA conversion circuit section Lwb of the circuit Gb, in addition to the relay line G14b corresponding to its own color, it also crosses the relay lines R14b and B14b of other colors.

[0205] In the semiconductor substrate, when arranging various elements, wirings, etc., it is effective to modularize a certain range and repeatedly arrange the blocks. In addition, regarding the relay lines R14b, B14b, and G14b, a structure that can preferably be connected to an inspection circuit (not shown) separately provided in the electro-optical device 10 to inspect defects in the manufacturing process is preferred.

[0206] Therefore, regarding the relay lines R14b, B14b, and G14b, as Figure 16 shown by the thick lines, although it is relatively redundant, a structure that preferably extends in the Y direction and is connected to an inspection circuit provided, for example, below in the figure is preferred. In addition, the redundancy mentioned here means that for the relay lines R14b, B14b, G14b, if only for realizing the DA conversion function in the DA conversion circuit 500, the thick line portions are not required.

[0207] In such a structure, regarding the lengths of the relay lines R14b, B14b, and G14b, they are in the order of R14b > B14b > G14b. Therefore, regarding the magnitudes of the capacitance Cp_R parasitic on the relay line R14b, the capacitance Cp_B parasitic on the relay line B14b, and the capacitance Cp_G parasitic on the relay line G14b, they are also in the order of Cp_R > Cp_B > Cp_G.

[0208] Therefore, assuming that VL_R=VL_B=VL_G, the potentials VPL_R, VPL_B, and VPL_G are also set to satisfy VPL_R>VPL_B>VPL_G, and are set to different potentials for each color.

[0209] When the capacitance parasitic on the relay line 14b is different for each color, if the potential VPL is made the same, the voltage characteristics of the second DA conversion circuit unit Lwb are different for each color, and the display quality is reduced. On the other hand, as in the third embodiment, if the potential VPL is made different for each color in accordance with the capacitance parasitic on the relay line 14b, the voltage characteristics of the second DA conversion circuit unit Lwb are consistent, so it is possible to suppress the reduction of display quality.

[0210] In the third embodiment, the potentials VPL_R, VPL_B, and VPL_G are set according to the magnitude of the parasitic capacitance, but the potentials VPH_R, VPH_B, and VPH_G may also be set. In addition, the capacitance value of the capacitor element Cser may be different for each color, that is, for each circuit Rb, Gb, and Bb. However, the capacitance value of the capacitor element Cser is uniquely determined by manufacturing and is difficult to adjust after manufacturing, so a structure that can adjust the potential VPL or the potential VPH afterwards is preferred.

[0211] In addition, R (red) is an example of the first color, B (blue) is an example of the second color, and G (green) is an example of the third color. The potential VPL_R is an example of the third potential of the second DA conversion circuit unit corresponding to the first color, the potential VPL_B is an example of the third potential of the second DA conversion circuit unit corresponding to the second color, and the potential VPL_G is an example of the third potential of the second DA conversion circuit unit corresponding to the third color.

[0212] Description Figure 16 In the structure shown (i.e., in the structure in which the DA conversion circuits 500 of the circuits Rb, Bb, and Gb are arranged along the Y direction within a range narrower than the width 3W), the structure of the capacitor elements C5 to C9 in the first DA conversion circuit unit Upb. The ratios of the capacitance values ​​of the capacitor elements C5 to C9 are "1", "2", "4", "8", and "16" in sequence. Therefore, for example, the capacitor element C5 is used as the basic capacitor element, and for the capacitor elements C6 to C9, a structure in which 2, 4, 8, or 16 basic capacitor elements are connected in parallel is adopted.

[0213] Figures 17 to 21 1 is a top view showing the structure of such a basic capacitor element and its periphery. Figure 22 The Pp line Figures 17 to 21 A partial cross-sectional view of the basic capacitor element in FIG. Figure 23 So Qq line willFigures 17 to 21 Partial cross-sectional view obtained by cutting the basic capacitor element in

[0214] The electro-optical device 10 is formed on the semiconductor substrate as described above. In this semiconductor substrate, the layers serving as the conductive layer or the wiring layer are, in order from the base material, a semiconductor layer 210, a gate electrode layer 220, a first wiring layer 230, a second wiring layer 240, a third wiring layer 250, and a fourth wiring layer 260, a total of six layers. Therefore, if you want to show a plan view of the capacitor element C5 and its periphery in one figure, it will become complicated and difficult to observe. Therefore, in Figures 17 to 21 for the above six layers, two adjacent layers are respectively shown in a plan view.

[0215] More specifically, Figure 17 a wiring pattern composed of the semiconductor layer 210 and the gate electrode layer 220 is shown. Figure 18 a wiring pattern composed of the gate electrode layer 220 and the first wiring layer 230 is shown. Figure 19 a wiring pattern composed of the first wiring layer 230 and the second wiring layer 240 is shown. Figure 20 a wiring pattern composed of the second wiring layer 240 and the third wiring layer 250 is shown. Figure 21 a wiring pattern composed of the third wiring layer 25 and the fourth wiring layer 260 is shown.

[0216] As Figure 17 , Figure 22 and Figure 23 shown, this basic capacitor element has a structure in which an electrode 211 formed of the semiconductor layer 210 and an electrode 221 formed by patterning the gate electrode layer 220 sandwich a gate insulating layer 270.

[0217] In addition, the electrode 211 is formed, for example, by implanting impurity ions into the p-well region Well. The region St is a trench for separating adjacent element regions.

[0218] In addition, in addition to the electrode 211, in the semiconductor layer 210, a wiring 212 is formed along the Y direction. The wiring 212 is used, for example, as a power supply wiring to which the potential VL is supplied.

[0219] In addition to the electrode 221, a wiring 222 is formed along the Y direction by patterning the gate electrode layer 220. The wiring 222 is used, for example, as a power supply wiring for the potential Vddh to which the level shifter Ls is supplied.

[0220] As Figure 17 , Figure 18 and Figure 23As shown, the electrode 211 is connected to the wiring 231 via the contact hole Ct1 that opens through the gate insulating layer 270 and the first interlayer insulating layer 271. The wiring 212 is connected to the wiring 234 via the contact hole Ct11 that opens through the gate insulating layer 270 and the first interlayer insulating layer 271.

[0221] As Figure 17 , Figure 18 and Figure 22 shown, the electrode 221 is connected to the wiring 232 via the contact hole Ct2 that opens through the first interlayer insulating layer 271. The first interlayer insulating layer 271 is an insulating layer provided between the gate electrode layer 220 and the first wiring layer 230. The wirings 231, 232, and 234 are wirings formed by patterning the first wiring layer 230. Among them, the wirings 231 and 232 are relay wirings, and the wiring 234 is a power supply wiring formed along the X direction.

[0222] In addition to the wirings 231, 232, and 234, the wirings 233 and 235 are formed along the X direction by patterning the first wiring layer 230.

[0223] When the illustrated basic capacitor element forms the capacitor element C6, for example, the wiring 233 is used as a power supply wiring for supplying the potential VPH. In addition, when the illustrated basic capacitor element forms any one of the low - level capacitor elements C0 to C4, the wiring 233 is used as a power supply wiring for supplying the potential VPL. The wiring 235 is connected to the wiring 222 for supplying the potential Vddh via the contact hole Ct12.

[0224] As Figure 18 , Figure 19 and Figure 23 shown, the wiring 231 is connected to the wiring 241 via the contact hole Ct3 that opens through the second interlayer insulating layer 272. As Figure 18 , Figure 19 and Figure 22 shown, the wiring 232 is connected to the wiring 242 via the contact hole Ct4 that opens through the second interlayer insulating layer 272. The second interlayer insulating layer 272 is an insulating layer provided between the first wiring layer 230 and the second wiring layer 240.

[0225] The wiring 241 is formed by patterning the second wiring layer 240 and is connected to any one of the selection circuits 515 to 519. For example, when the illustrated basic capacitor element forms the capacitor element C6, the electrode 211, which is one end of the basic capacitor element, is sequentially connected to the selection circuit 516 via the wirings 231 and 241. The wiring 242 is a relay wiring formed by patterning the second wiring layer 240.

[0226] In addition to wirings 241 and 242, wirings 243, 244, 245, 246, and 248 are formed along the Y direction by patterning the second wiring layer 240. Among them, for example, wirings 243 and 246 are used to supply control signals, and wirings 244 and 245 are connected to the wiring 212 that supplies the potential VL via contact holes Ct12 and are used as power supply wirings. Wiring 248 is connected to the wiring 233 that supplies the potential VPH via contact hole Ct13 and is used as a power supply wiring.

[0227] As Figure 19 , Figure 20 and Figure 22 shown, wiring 242 is connected to wiring 252 via contact hole Ct6 that opens the third interlayer insulating layer 273. The third interlayer insulating layer 273 is an insulating layer provided between the second wiring layer 240 and the third wiring layer 250. Wiring 252 is a relay wiring formed by patterning the third wiring layer 250.

[0228] In addition to wiring 252, wiring 253 is formed along the X direction by patterning the third wiring layer 250. Wiring 253 is connected to the wiring 248 that supplies the potential VPH via contact hole Ct14 and is used as a power supply wiring.

[0229] As Figure 20 , Figure 21 and Figure 22 shown, wiring 252 is connected to the data line R14 via contact hole Ct8 that opens the fourth interlayer insulating layer 274. The fourth interlayer insulating layer 274 is an insulating layer provided between the third wiring layer 250 and the fourth wiring layer 260. The data line R14 is formed by patterning the fourth wiring layer 260.

[0230] In addition to the data line R14, data lines B14, G14, and wirings 261, 262, and 263 are formed by patterning the fourth wiring layer 260.

[0231] The data line R14 is commonly connected to the other ends of the capacitor elements C5 - C9 and the other end of the capacitor element Cser of the first DA conversion circuit section Upb in the circuit Rb.

[0232] The data line B14 is Figure 16 commonly connected to the other ends of the capacitor elements C5 - C9 and the other end of the capacitor element Cser of the first DA conversion circuit section Upb in the circuit Bb located below the circuit Rb. The data line G14 is Figure 16 commonly connected to the other ends of the capacitor elements C5 - C9 and the other end of the capacitor element Cser of the first DA conversion circuit section Upb in the circuit Gb located below the circuit Bb.

[0233] In addition, wirings 261, 262, and 263 are used as power supply wirings for supplying the potential Vel, for example.

[0234] Here, in the circuit Rb, the basic capacitor elements of the capacitor elements C5 to C9 constituting the first DA conversion circuit section Upb have been described as an example. However, the basic capacitor elements of the capacitor elements C0 to C4 constituting the second DA conversion circuit section Lwb in the circuit Rb also have the same structure. However, it should be noted that the data line R14 is replaced with the relay line R14b, and the wiring for supplying the potential VPH is replaced with the wiring for supplying the potential VPL.

[0235] In the circuits Bb and Gb, the structure is the same as that of the circuit Rb.

[0236] However, in the case where the Figure 21 shown structure is used as a reference, in the circuit Bb, in the first DA conversion circuit section Upb, the data line R14 is replaced with the relay line R14b, and in the second DA conversion circuit section Lwb, the data line R14 is replaced with the relay line R14b, and the data line B14 is replaced with the relay line B14b.

[0237] Similarly, in the case where the Figure 21 shown structure is used as a reference, in the circuit Gb, in the first DA conversion circuit section Upb, the data line R14 is replaced with the relay line R14b, the data line B14 is replaced with the relay line B14b, and in the second DA conversion circuit section Lwb, the data line R14 is replaced with the relay line R14b, the data line B14 is replaced with the relay line B14b, and the data line G14 is replaced with the relay line G14b.

[0238] In this way, the data line R14 is shielded by the wirings 261 and 262 adjacent to it on the left and right in the figure. Similarly, the data line G14 is shielded by the wirings 262 and 263 adjacent to it on the left and right, and the data line B14 is shielded by the wirings 263 and 261 adjacent to it on the left and right.

[0239] In addition, the relay line R14b is shielded by the wirings 261 and 262 adjacent to it on the left and right in the figure. Similarly, the relay line G14b is shielded by the wirings 262 and 263 adjacent to it on the left and right, and the relay line B14b is shielded by the wirings 263 and 261 adjacent to it on the left and right.

[0240] In addition, for the power supply wirings of the fixed potential, they are formed along the X direction in the first wiring layer 230 and the third wiring layer 250, and are formed along the Y direction in the second wiring layer 240 and the fourth wiring layer 260, and are alternately formed in a grid pattern in plan view in the X direction and the Y direction.

[0241] In this way, the data lines R14, G14, B14, the relay lines R14b, G14b, and B14b are shielded by the power supply wirings adjacent to the left and right. In addition, the basic capacitor elements are also shielded by the power supply wirings that form a mesh when viewed from above. Therefore, the potential fluctuations caused by noise are suppressed to a small level.

[0242] [Application Example, Modification Example]

[0243] In the above-described various embodiments (hereinafter referred to as "embodiments, etc."), various modifications or applications can be made as follows.

[0244] The DA conversion circuit 500 in the above-described various embodiments, etc. is configured to divide 10 bits into the higher-order bits D5 to D9 and the lower-order bits D0 to D4. Among them, the first DA conversion circuit section Upb converts the bits D5 to D9 and directly outputs them to the data line 14, and the second DA conversion circuit section Lwb converts the bits D0 to D4 and outputs them to the data line 14 via the capacitor element Cser. However, the number of bits of the data to be converted may be 2 or more.

[0245] In addition, in the electro-optical device 10 to which the DA conversion circuit 500 of the application embodiment, etc. is applied, as an example of the display element, the OLED 130 has been described, but other display elements can also be used. For example, as the display element, an LED can be used, or a liquid crystal element can also be used. That is, as the display element, any electro-optical element that becomes an optical state corresponding to the voltage of the data signal output from the DA conversion circuit 500 is acceptable.

[0246] In the embodiments, etc., a structure for compensating the threshold voltage of the transistor 121 in the pixel circuit 110 is adopted, but a structure that does not compensate the threshold voltage can also be adopted. Specifically, a structure in which the transistor 123 is omitted can also be adopted.

[0247] The channel types of the transistors 66, 121 to 125 are not limited to the embodiments, etc. In addition, these transistors 66, 121 to 125 can also be appropriately replaced with transmission gates. Conversely, regarding the transmission gates Tg0 to Tg2, they can also be replaced with a single-channel type transistor.

[0248] [Electronic Device]

[0249] Next, an electronic device to which the electro-optical device 10 of the embodiments, etc. is applied will be described. The electro-optical device 10 is suitable for display applications with a small pixel size and high definition. Therefore, as an electronic device, a head-mounted display will be described as an example.

[0250] Figure 24 is a view showing the appearance of the head-mounted display, Figure 25 is a view showing its optical structure.

[0251] First, as Figure 24 shown, the head-mounted display 300 has temple arms 310, a bridge 320, and lenses 301L and 301R in appearance similar to ordinary glasses. Additionally, as Figure 25 shown, the head-mounted display 300 is provided with an electro-optical device 10L for the left eye and an electro-optical device 10R for the right eye near the bridge 320 and inside (the lower side in the figure) of the lenses 301L and 301R.

[0252] The image display surface of the electro-optical device 10L is arranged to be on the left side in Figure 25 . Thus, the display image of the electro-optical device 10L is emitted in the direction of 9 o'clock in the figure via the optical lens 302L. The semi-transmissive semi-reflective mirror 303L reflects the display image of the electro-optical device 10L in the direction of 6 o'clock, and on the other hand, transmits the light incident from the direction of 12 o'clock. The image display surface of the electro-optical device 10R is arranged to be on the right side opposite to the electro-optical device 10L. Thus, the display image of the electro-optical device 10R is emitted in the direction of 3 o'clock in the figure via the optical lens 302R. The semi-transmissive semi-reflective mirror 303R reflects the display image of the electro-optical device 10R in the direction of 6 o'clock, and on the other hand, transmits the light incident from the direction of 12 o'clock.

[0253] In this structure, the wearer of the head-mounted display 300 can observe the display images of the electro-optical devices 10L and 10R in a perspective state that coincides with the external situation.

[0254] Additionally, in this head-mounted display 300, if the electro-optical device 10L displays the left-eye image in the binocular images with parallax and the electro-optical device 10R displays the right-eye image, the wearer can feel that the displayed images have depth and stereoscopic effects.

[0255] Furthermore, regarding the electronic device including the electro-optical device 10, in addition to the head-mounted display 300, it can also be applied to electronic viewfinders in cameras or interchangeable-lens digital cameras, portable information terminals, display units of watches, light valves of projection-type projectors, etc.

[0256] [Annotations]

[0257] A DA conversion circuit of a first method (Method 1) includes: a first DA conversion circuit unit corresponding to high-order bits among a plurality of bits; a second DA conversion circuit unit corresponding to low-order bits among the plurality of bits; and a coupling capacitor provided between the first DA conversion circuit unit and the second DA conversion circuit unit. The first DA conversion circuit unit includes a high-order capacitance element unit and a high-order switch element unit, and the second DA conversion circuit unit includes a low-order capacitance element unit and a low-order switch element unit. The high-order switch element unit supplies either a first potential or a second potential to one end of the high-order capacitance element unit, and the low-order switch element unit supplies either the first potential or a third potential to one end of the low-order capacitance element unit, where the third potential is different from the second potential.

[0258] In Method 1, the output voltage of the second DA conversion circuit unit is compressed by the coupling capacitor and output together with the output voltage of the first DA conversion circuit unit. When the second potential and the third potential are the same, if the output characteristics of the first DA conversion circuit unit and the second DA conversion circuit unit are inconsistent, the linearity of the characteristics of the output voltage obtained by converting the data represented by a plurality of bits is impaired. However, if the second potential and the third potential are made different as in Method 1, the linearity of the characteristics of the output voltage can be improved.

[0259] In the DA conversion circuit of a specific method (Method 2) of Method 1, the first DA conversion circuit unit includes capacitance elements corresponding to the weights of the high-order bits, the second DA conversion circuit unit includes capacitance elements corresponding to the weights of the low-order bits, and the coupling capacitor is provided between the other ends of the capacitance elements corresponding to the high-order bits and the other ends of the capacitance elements corresponding to the low-order bits.

[0260] In the DA conversion circuit of a specific method (Method 3) of Method 2, the capacitance value of the coupling capacitor is the same as the capacitance value of the capacitance element corresponding to the bit with the smallest weight among the high-order bits, and the third potential is a potential higher than the second potential.

[0261] According to Method 3, the linearity of the characteristics of the output voltage obtained by converting the data represented by a plurality of bits can be improved.

[0262] In the DA conversion circuit of another specific method (Method 4) of Method 2, the capacitance value of the coupling capacitor is greater than the capacitance value of the capacitance element corresponding to the bit with the smallest weight among the high-order bits, and the third potential is a potential lower than the second potential.

[0263] According to Method 4, it is possible to suppress the occurrence of an inversion phenomenon in which the voltage obtained by converting data with a smaller decimal value represented by multiple bits is higher than the voltage obtained by converting data with a larger decimal value.

[0264] The DA conversion circuit of another method (Method 5) has at least a group of the following parts corresponding to the first color, the second color, and the third color: a first DA conversion circuit part corresponding to the high-order bits among the multiple bits; a second DA conversion circuit part corresponding to the low-order bits among the multiple bits; and a coupling capacitor provided between the first DA conversion circuit part and the second DA conversion circuit part. The first DA conversion circuit part corresponding to the first color, the second color, and the third color has a high-order capacitor element part and a high-order switch element part. The second DA conversion circuit part corresponding to the first color, the second color, and the third color has a low-order capacitor element part and a low-order switch element part. The high-order switch element part supplies a first potential or a second potential to one end of the high-order capacitor element part. The low-order switch element part supplies either the first potential or a third potential to one end of the low-order capacitor element part. In the first DA conversion circuit part and the second DA conversion circuit part corresponding to the same color, the second potential is different from the third potential. The third potential of the second DA conversion circuit part corresponding to the first color, the third potential of the second DA conversion circuit part corresponding to the second color, and the third potential of the second DA conversion circuit part corresponding to the third color are all different from each other.

[0265] According to Method 5, it is possible to make the output characteristics of the first DA conversion circuit part and the characteristics of the output voltage from the second DA conversion circuit part consistent for each color. In addition, as examples of colors, for example, three colors of R (red), G (green), and B (blue) can be cited, but it can also be four or more colors.

[0266] In the electro-optical device of Method 6, an electro-optical element is included. The electro-optical element converts multiple bits into a data signal through the DA conversion circuit of any one of Methods 1 to 5, and thus becomes an optical state based on the data signal. According to the electro-optical device of Method 7, space saving can be achieved in the electro-optical device.

[0267] In addition, the electronic device of Method 7 includes the electro-optical device of Method 6.

Claims

1. An electro-optical device, characterized in that, The electro-optical device has at least a group of parts corresponding to a first color, a second color, and a third color as follows: An electro-optical element; A first DA conversion circuit section corresponding to high-order bits among a plurality of bits; A second DA conversion circuit section corresponding to low-order bits among the plurality of bits; A coupling capacitor provided between the first DA conversion circuit section and the second DA conversion circuit section; A relay line electrically connected to one end of the coupling capacitor; and A data line electrically connecting the other end of the coupling capacitor to the electro-optical element, The first DA conversion circuit section corresponding to the first color, the second color, and the third color has: A high-order capacitance element section having capacitance elements corresponding to the high-order bits; And A high-order switch element section for supplying either a first potential or a second potential to one end of the capacitance element corresponding to the high-order bits, The second DA conversion circuit section corresponding to the first color, the second color, and the third color has: A low-order capacitance element section having capacitance elements corresponding to the low-order bits; And A low-order switch element section for supplying either the first potential or a third potential to one end of the capacitance element corresponding to the low-order bits, The data line is electrically connected to the other end of the capacitance element corresponding to the high-order bits, The relay line is electrically connected to the other end of the capacitance element corresponding to the low-order bits, In the first DA conversion circuit section and the second DA conversion circuit section corresponding to the same color, The second potential is different from the third potential, The third potential of the second DA conversion circuit section corresponding to the first color, the third potential of the second DA conversion circuit section corresponding to the second color, and the third potential of the second DA conversion circuit section corresponding to the third color are different from each other.

2. An electronic device, wherein, The electronic device has the electro-optical device described in claim 1.

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