Sense amplifier circuit, memory, and electronic device

Abstract

A sense amplifier circuit, a memory, and an electronic device are disclosed. The sense amplifier circuit includes: a first PMOS transistor (501), with its source connected to a power supply terminal, its gate connected to a reference voltage, and its drain connected to an output terminal; a first NMOS transistor (503), with its drain connected to the output terminal, its gate connected to a second node (fb), and its source connected to a first node (N1), the first node being connected to a bit line; a second NMOS transistor (504), with its drain connected to the second node, its gate connected to the first node, and its source connected to a third node (N3); a second PMOS transistor (502), with its source connected to a power supply terminal, its gate connected to a second reference voltage, and its drain connected to the second node; and a third NMOS transistor (505), with its drain connected to the third node, its gate connected to the second node, and its source grounded. By replacing the existing dual-diode connection structure with a third NMOS transistor and reusing the second NMOS transistor, the secondary frequency can be increased to ensure loop stability while saving the footprint of the SA circuit.

Description

Technical Field

[0001] This invention relates to the field of semiconductor storage technology, and in particular to a readout amplifier circuit, a memory, and an electronic device. Background Technology

[0002] Memory devices, implemented as semiconductor integrated circuits, are indispensable in computers and other electronic devices. Many different types of memory exist, such as volatile and non-volatile memory. These different memory types include, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

[0003] Among these, flash memory has evolved into a widely used non-volatile memory for various electronic applications. Flash memory typically uses a single transistor as a storage unit and can achieve high storage density, high reliability, and low power consumption. Common uses of flash memory include personal computers, tablets, digital cameras, and smartphones. Program code and system data used by personal computer systems (such as the Basic Input / Output System (BIOS)) are also typically stored in flash memory.

[0004] As computer system performance improves, flash memory performance also urgently needs to be improved. A key circuit determining flash memory performance is the sense amplifier (SA) and its related circuitry. For example, memory access time depends on the speed of the SA and its corresponding readout scheme. In smartphones, for instance, faster flash memory access times can improve the overall operating speed of the phone, its ability to perform parallel operations, and the amount of data it can process.

[0005] As is well known, SA can be used in verification after read operations or programming / erasing operations to compare the output signal and reference signal of the selected memory cell and make corresponding outputs based on the comparison results. Figure 1 The basic operating principle of SA is shown.

[0006] As shown in the figure, SA can be regarded as a comparator. By comparing the signal obtained from the voltage SENSL on a bit line (hereinafter also referred to as "BL") with the reference signal REF, it can output different SAOUT signals, thereby amplifying and reading out the weak signal on the bit line, and thus determining the current storage state of the selected memory cell, such as whether to store "0" or "1".

[0007] Since a single SA circuit is typically connected to a single bit line, flash memory contains thousands of SA circuits with the same structure. As transistor manufacturing processes shrink further and integration density increases, it is necessary to simplify the structure of the SA circuit as much as possible while ensuring access performance, in order to save area costs. Summary of the Invention

[0008] In view of this, the present invention provides an improved SA structure. This structure can reduce the number of transistors required for SA structures while maintaining circuit stability, thereby further reducing the footprint required for memory chip manufacturing.

[0009] According to a first aspect of the present invention, a sense amplifier circuit is provided, comprising: a first PMOS transistor, the source of which is connected to a power supply terminal, the gate of which is connected to a reference voltage, and the drain of which is connected to an output terminal; a first NMOS transistor, the drain of which is connected to the output terminal, the gate of which is connected to a second node, the source of which is connected to a first node, and the first node is connected to a bit line; a second NMOS transistor, the drain of which is connected to the second node, the gate of which is connected to the first node, and the source of which is connected to a third node; a second PMOS transistor, the source of which is connected to a power supply terminal, the gate of which is connected to a second reference voltage, and the drain of which is connected to the second node; and a third NMOS transistor, the drain of which is connected to the third node, the gate of which is connected to the second node, and the source of which is grounded.

[0010] Optionally, the readout amplifier circuit is used to output the stored data in the memory cell connected to the bit line during a read operation or verification operation.

[0011] Optionally, the first NMOS transistor and the second NMOS transistor form a negative feedback loop for stabilizing the voltage on the bit line.

[0012] Optionally, the bit line is connected to a pre-charge circuit before the read or verification operation and is pre-charged to the clamping voltage by the second reference voltage input to the gate of the second PMOS transistor.

[0013] Optionally, the negative feedback loop stabilizes the clamping voltage on the bit line during a read operation or a verification operation.

[0014] Optionally, the output terminal is connected to an inverter, and the output of the inverter is used to represent the stored data.

[0015] Optionally, the second PMOS transistor provides a stable current to the second and third NMOS transistors connected in series via a second reference voltage connected to its gate, and reduces the impedance of the second node.

[0016] According to a second aspect of the present invention, a memory is provided, comprising: a readout amplifier circuit as described in the first aspect, for reading and amplifying current signals on bit lines to determine the stored content of a selected memory cell.

[0017] According to a third aspect of the invention, an electronic device is provided, including a memory as described in the second aspect.

[0018] Therefore, by replacing the existing dual-diode connection structure with a third NMOS transistor and rationally reusing the second NMOS transistor, this invention can also reduce the impedance of node fb, increase the secondary frequency of node fb, and ensure loop stability. Furthermore, compared to the diode-connected dual-transistor structure, the SA structure provided by this invention saves the footprint of one transistor, thereby further reducing the area consumption of the SA module circuit while maintaining overall SA performance. Attached Figure Description

[0019] The above and other objects, features and advantages of this disclosure will become more apparent from the more detailed description of exemplary embodiments thereof taken in conjunction with the accompanying drawings, wherein like reference numerals generally denote like parts.

[0020] Figure 1 The basic operating principle of SA is shown.

[0021] Figure 2 It is an electronic device that includes a memory according to an embodiment of the present invention.

[0022] Figure 3 This is a schematic diagram illustrating a storage block according to an embodiment of the present invention.

[0023] Figure 4 An example of the composition of an SA circuit structure is shown.

[0024] Figure 5 A schematic diagram of the improved SA circuit structure is shown. Detailed Implementation

[0025] Various embodiments will be described in more detail with reference to the accompanying drawings. However, the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, the same reference numerals denote the same parts in the various drawings and embodiments of the invention.

[0026] It is important to note that the accompanying drawings are simplified schematics and therefore not necessarily drawn to scale. In some cases, portions of the drawings may be exaggerated to more clearly illustrate certain features of the illustrated embodiments.

[0027] It is further noteworthy that specific details are set forth in the following description to facilitate understanding of the invention; however, the invention may be practiced without some of these specific details. Furthermore, well-known structures and / or processes may be described only briefly or not at all to avoid obscuring this disclosure with unnecessary well-known details.

[0028] It should also be noted that in some cases, it will be apparent to those skilled in the art that, unless otherwise specifically stated, an element (also referred to as a feature) associated with one embodiment described may be used alone or in combination with other elements of another embodiment.

[0029] The various embodiments of the present invention will now be described in detail with reference to the accompanying drawings. For ease of understanding, the following will first be combined with... Figure 2 Describe the application environment of this invention.

[0030] Figure 2 It is an electronic device that includes a memory according to an embodiment of the present invention. As shown, the device 10 includes a host 200 and a memory 300.

[0031] Here, host 200 refers to the part that implements the key functions of device 10, that is, the main part of device 10, and host 200 (or device 10) can be any suitable electronic device. In one embodiment, device 10 can be an electronic device, including but not limited to portable electronic devices such as mobile phones, tablets, wearable devices, and laptops, or non-portable electronic devices such as desktop computers, game consoles, televisions, set-top boxes, and projectors. In this case, memory 300 can be a device that provides storage services for standalone electronic devices.

[0032] In other embodiments, device 10 may also be an electronic device with relatively independent functions (these electronic devices are often key components of electronic devices), such as a separately sold smart screen, main control chip, camera assembly, etc. These electronic devices typically need to be assembled; for example, a smart screen is assembled into a mobile phone to provide services to consumers (e.g., users who purchase the mobile phone). In this case, memory 300 may be a device that provides the necessary storage services for the electronic device.

[0033] For example, when device 10 is a smartphone, memory 300 may be a storage chip that provides storage services for the smartphone. When device 10 is a smart screen that makes up a smartphone, memory 300 may be a storage chip that provides storage services for the smart screen to achieve all its functions.

[0034] The memory 300 can respond to requests from the host 200. For example, the memory 300 can store data provided by the host 200 and can also provide the stored data to the host 200. The data stored in the memory 300 can be accessed by the host 200. The memory 300 can be used as the main memory or auxiliary memory of the host 200. Here, the data stored in the memory 300 can include not only data files in a narrow sense (e.g., photographs, written Word documents, etc.), but also other data in a broader sense, such as command data and address data.

[0035] In theory, the memory 300 can be implemented using any of a variety of storage devices, depending on the protocol of the host interface electrically connected to the host 200. In this invention, flash memory is preferably used to implement the memory 300. Flash memory includes NAND flash memory and NOR flash memory. The various components contained within the memory 300 (e.g., components 310-370) can be integrated into a single semiconductor device. For example, the various components contained within the memory 300 can be integrated into a single semiconductor device to form a solid-state drive (SSD). When the memory 300 is used as an SSD, the operating speed of the host 200 electrically connected to the memory 300 can be significantly improved.

[0036] Specifically, in memory 300, memory array 320 can store data accessed by host 300. Controller 310 can control data exchange between memory array 320 and host 200, as well as various operations on memory array 320, such as read operations, programming operations (write operations), and erase operations.

[0037] Specific reference Figure 2 The memory 300 may include a controller 310, a memory array 320, an address register 330, a row decoder 340, a sense amplifier (or sensing circuit) 345, a column decoder 350, a charge pump (or power supply unit) 360, and a buffer unit (or page buffer) 370.

[0038] In memory 300, controller 310 can receive command signals and / or address signals in response to external control signals. Controller 310 can control the execution of an operation corresponding to one of a read command, a program command, and an erase command in response to the command signals. Controller 310 can generate address signals (including row signals and column signals) based on the address signals.

[0039] The charge pump 360 is used to generate various operating voltages required for read, program, and erase operations.

[0040] Address register 330 can store row address information and column address information under the control of controller 310. Row decoder 340 is connected to memory array 320 via word lines (WL) and can select at least one word line in response to a row address. Column decoder 350 is connected to memory array 320 via bit lines and can select at least one bit line (BL) in response to the output of address register 330. According to one embodiment, row decoder 340 can decode the row address of address register 330 and generate a decoded signal for selecting a block of memory array 320.

[0041] Buffer unit 370 can store data to be programmed (or written) into memory array 320 under the control of controller 310. Furthermore, buffer unit 370 can store data read from memory array 320 and output the read data to an external source (e.g., to the host computer via controller 310). Buffer unit 370 is, for example, static random access memory (SRAM). Buffer unit 370 may also be referred to as page buffer 370.

[0042] The storage array 330 may include multiple storage blocks. Depending on the number of bits that can be stored or represented in each storage cell, the multiple storage blocks included in the storage array 330 may be single-level cell (SLC) storage blocks and / or multi-level cell (MLC) storage blocks. SLC means that one bit is stored in one storage cell, while MLC means that multiple bits, such as two or even three bits, can be stored in one storage cell.

[0043] Figure 3 This is a schematic diagram of a NAND flash memory block. See also... Figure 3 The memory block comprises memory cells arranged in multiple rows and columns. Each row of memory cells is connected to the same word line, forming a "page". Each column of memory cells is connected to the same bit line, forming a string (STR). Each string also includes at least one drain-select transistor (DST) and at least one source-select transistor (SST), with multiple memory cells electrically connected in series between the select transistors SST and DST. The memory cells are, for example, transistors including floating gates or charge trapping layers. Each memory cell can be configured by an SLC, each storing 1 bit of data. For reference, in Figure 3 In this context, "GSL" represents the drain selection line, "SSL" represents the source selection line, and "CSL" represents the common source line.

[0044] Figure 3The illustrated storage block comprises 64 pages, connected to WL0 through WL63 respectively. In other embodiments, each block may include more or fewer pages. Figure 3 Each page, as shown, comprises N storage units. Each page may include a data storage area, a redundant storage area, an ECC code storage area, etc. For example, the data storage area of ​​each page includes 1024*8 storage units, which can store 1KB of data.

[0045] In this invention, the memory 300 can be implemented as a two-dimensional or three-dimensional memory device. For example, in the case where the memory is implemented in three dimensions, the plurality of memory blocks it includes can be implemented as a three-dimensional structure by means of a structure extending in a first to a third direction (e.g., the x-axis direction, the y-axis direction, and the z-axis direction).

[0046] During a read operation, a read voltage (e.g., 0.6V) is applied to the word lines of the selected page, while a read pass voltage (e.g., 6V) is applied to the word lines of the unselected pages. This read pass voltage enables memory cells to conduct regardless of whether they are in a programmed state (memory cells storing "0") or an unprogrammed state (memory cells storing "1"). For transistors in an unprogrammed state, the transistor will be in the on state under the read voltage. For transistors in a programmed state, the transistor will be in the off state under the read voltage.

[0047] The sense amplifier 345 can be used in read or verification operations to compare the current flowing through the selected memory cell with a reference current and provide a corresponding output. Specifically, the sense amplifier 345 may include multiple identical SA circuit structures, such as... Figure 3 SA0-SA shown N-1 When a page's data storage area includes 1024*8 storage units and can store 1KB of data, the corresponding storage block usually also needs to be equipped with 1024*8 bit lines and corresponding 1024*8 SA circuit structures.

[0048] Each SA circuit structure can be viewed as... Figure 1 The diagram shows a current comparator. Each SA circuit structure is connected to a BL line; for example, SA0 is connected to BL0, SA1 is connected to BL1, ..., SA N-1 Connecting to BL N-1 Each SA can also be connected to its own reference voltage V. ref Thus, the reference current I is obtained. ref The output is determined by comparing the current on BL with the reference current.

[0049] Specifically, during a read operation, the transistor storing a "1" will be in the on state under the read voltage, resulting in a relatively large current through BL; conversely, the transistor storing a "0" will be in the off state under the read voltage, resulting in a relatively small current through BL. Therefore, the reference current I during the read operation... ref Under the same conditions, SA can output different comparison results for different SENBL inputs, corresponding to high levels (e.g., power supply voltage V). DD A high level (e.g., 0) and a low level indicate the memory content of the selected transistor on the corresponding BL. Erase verification or program verification operations are similar to read operations. The magnitude of the verification voltage applied to the control gate of the selected memory cell in the erase verification operation differs from the magnitude of the read voltage in the read operation; correspondingly, the reference current is different, and the reference voltage V0 is also different. ref They are not the same either.

[0050] The above combination Figure 1-3 The application scenarios in which this invention can be implemented are described, as well as the basic operating principle of SA. The following will combine... Figure 4 The composition and specific operating principle of the SA circuit (also known as the SA unit) are explained.

[0051] Figure 4 An example of the SA circuit structure is shown. As shown in the figure, the SA circuit 400 includes two PMOS transistors 401 and 402, and four NMOS transistors 403-406.

[0052] PMOS transistor 401 and NMOS transistor 403 are connected in series between the power supply terminal and the first node N1. The first node N1 is connected to the bit line BL of memory 300. PMOS transistor 401 is used to provide a reference current I. ref Specifically, the gate of the PMOS transistor 401 is connected to the reference voltage V. ref The source is connected to the power supply terminal, and the drain is connected to the output terminal sain. Here, PMOS transistor 401 can be referred to as the "first PMOS transistor" of the SA circuit. In some cases, the gate of PMOS transistor 401 can be considered as the reference input terminal of the SA circuit, where the reference input of the SA circuit is the reference voltage V. ref In some cases, the drain of the PMOS transistor 401 can also be considered as the reference input of the SA circuit. In this case, the reference input of the SA circuit is based on the reference voltage V. ref The generated reference current I ref .

[0053] Reference voltage V refIt can be obtained from the reference current of the reference cell (refcell) via current mirroring and then through I / V conversion. It should be understood that, under a given operation of a given memory, the SA0-SA of the read amplifier 345... N-1 The reference voltage V obtained by the circuit ref They should be the same, or at least nearly the same. That is, for flash memory operating at a specific power supply voltage, the reference voltage V for each SA during a read operation. ref Similarly, the reference voltage V for each SA should be verified under the same conditions. ref They should be the same. However, the reference voltage V under read and verification operations is different. ref The voltage values ​​can be different. In the following description of the present invention, the principle of the SA circuit will be described in conjunction with the read operation.

[0054] The source of NMOS transistor 403 is connected to the first node N1, the gate is connected to the second node fb, and the drain is connected to the output terminal sain. Here, NMOS transistor 403 can be referred to as the "first NMOS transistor" of the SA circuit.

[0055] The source of NMOS transistor 404 is grounded, the gate is connected to the first node N1, and the drain is connected to the second node fb. Here, NMOS transistor 404 can be referred to as the "second NMOS transistor" of the SA circuit.

[0056] The first node N1 is a node on the bit line BL. The source of NMOS transistor 403 is connected to the bit line BL. The drain of the memory cell is connected to BL, and the source can be grounded through a common source line. Since the current on the gate of NMOS transistor 404 is negligible, the current on BL is equal to the current flowing through NMOS transistor 403. Therefore, the source of NMOS transistor 403 can be considered as the input terminal of the SA circuit. As will be detailed below, this input terminal receives the current generated by BL, clamped at a fixed voltage (e.g., 0.8V), based on the stored content of the selected memory cell.

[0057] NMOS transistors 403 and 404 form a negative feedback circuit to ensure the stability of the voltage SENBL on BL.

[0058] Transistors 402, 405, and 406 on the left branch do not directly participate in the comparison of the comparator in the SA circuit, but they can be used to stabilize the feedback loop and avoid loop oscillation.

[0059] Specifically, the gate of the PMOS transistor 402 is connected to the second reference voltage V. ref’ The source is connected to the power supply terminal, and the drain is connected to the second node fb. Here, PMOS transistor 402 can be referred to as the "second PMOS transistor" of the SA circuit.

[0060] NMOS transistors 405 and 406 are each diode-connected, meaning their drains and gates are shorted. A drain-gate connected NMOS transistor can be considered as a diode that conducts under forward bias. Figure 4 In this circuit, NMOS transistors 405 and 406, connected in series with diodes, have their drain and gate connected to the second node fb, while the source of NMOS transistor 405 is grounded. For ease of description, NMOS transistor 405 can be referred to as the "third NMOS transistor" of the SA circuit, and NMOS transistor 406 as the "fourth NMOS transistor" of the SA circuit.

[0061] Here, unlike the reference voltage V ref Second reference voltage V ref’ It is not used as a reference input for the comparator in the SA circuit, but rather for pre-charging the BL voltage before the read operation. The diode-connected NMOS transistors 405 and 406 are used to reduce the impedance of the second node fb, ensuring the stability of the feedback loop composed of NMOS transistors 403 and 404. In practical applications, the voltage output by the bandgap circuit, which does not change with temperature, can be used as the second reference voltage V. ref’ .

[0062] In practice, a pre-charge circuit can be used before performing a read operation at a second reference voltage V. ref’ With the participation of [unclear], BL is pre-charged to a predetermined voltage, for example, making SENBL 0.8V, and then the pre-charge circuit is disconnected from BL. Due to the second reference voltage V... ref’ Typically slightly lower than the power supply voltage V DD Furthermore, the NMOS transistors 405 and 406, connected by diodes, have a relatively stable forward voltage drop (e.g., 0.7V), thus the second node fb has a relatively stable voltage value, for example, 1.4V. When there is a certain disturbance on BL, if SENBL increases, the gate-source voltage of NMOS transistor 404, which operates in the saturation region, increases, leading to an increase in drain current and a decrease in the voltage of the second node fb. Since the gate-source voltage of NMOS transistor 403 remains unchanged, the decrease in the voltage of the second node fb will in turn cause SENBL to decrease, thereby forming a negative feedback against the bit line voltage SENBL. Thus, by introducing a negative feedback loop composed of NMOS transistors 403 and 404, the voltage of SENBL can be clamped at the precharge voltage, for example, 0.8V.

[0063] For NAND Flash, during a read operation, since other memory cells on the bit line BL are in the on state, the current on the bit line BL is determined by whether the selected memory cell stores 0 or 1.

[0064] Specifically, when the selected memory cell stores 0 (or the data to be read is 0), the transistor of the selected memory cell tends to be cut off. Therefore, the current on BL is small, that is, the current flowing through NMOS transistor 403 is small. Thus, NMOS transistor 403 operates in the linear region, and the drain-source voltage is small. At this time, the reference current I flowing through PMOS transistor 401... ref The current is greater than the current flowing through the NMOS transistor 403 (i.e., the current on bit line BL), therefore the output is high, for example, close to the supply voltage V. DD The high level.

[0065] When the selected cell stores 1, the transistor containing the selected cell is turned on, so the current in BL is large, that is, the current flowing through NMOS transistor 403 is large. Therefore, NMOS transistor 403 operates in the saturation region, and sain outputs a low level.

[0066] In some implementations, an inverter can be connected after the SA output so that the SA circuit outputs a low level when the selected cell stores 0, and a high level when the selected cell stores 1. In this case, the output of the SA circuit can be equivalent to... Figure 1 The output SAOUT is shown.

[0067] exist Figure 4 In the SA circuit shown, a negative feedback circuit composed of NMOS transistors 403 and 404 is present to clamp the SENBL voltage at a predetermined voltage after pre-charging. Therefore, it is necessary to prevent the feedback loop from oscillating. Since the node frequency of the master node (i.e., the first node N1) is low and difficult to change under relatively fixed resistor and capacitor conditions, diode-connected NMOS transistors 405 and 406 are introduced, along with a suitable second reference voltage V. ref’ With the help of this method, the impedance of the secondary point (i.e., the second node fb) of the negative feedback circuit is reduced, thereby increasing the node frequency of the second node fb. This allows for a significant difference in the node frequencies between the primary and secondary stages, thus ensuring the loop stability of the feedback circuit.

[0068] However, because flash memory contains a large number of SA circuits, i.e. Figure 4 The SA cell is shown. With further miniaturization of transistor manufacturing processes and increased integration density, it is necessary to simplify the SA circuit structure as much as possible while ensuring access performance, in order to save area costs. To this end, this invention further proposes a more streamlined SA circuit structure that can reduce the number of transistors required by the SA circuit while ensuring loop stability and read speed, thereby saving overall area consumption.

[0069] Figure 5A schematic diagram of the improved SA circuit structure is shown. (Compared to...) Figure 4 Similarly, the SA circuit 500 also includes two PMOS transistors 501 and 502, each with its gate connected to a different reference voltage, and two NMOS transistors 503 and 504 forming the negative feedback circuit. However, the difference lies in... Figure 5 In the SA circuit structure, the diode structure formed by two transistors is omitted. Instead, the impedance of the second node fb is reduced by the reasonable connection of a single transistor (NMOS transistor 505), thus ensuring the stability of the loop.

[0070] Specifically, the gate connection reference voltage V of PMOS transistor 501 ref The source is connected to the power supply terminal, and the drain is connected to the output terminal. Here, PMOS transistor 501 can be referred to as the "first PMOS transistor" of the SA circuit. The connection method of PMOS transistor 501 is similar to... Figure 4 The connection method of PMOS transistor 401 shown is exactly the same. The gate of PMOS transistor 501 can be regarded as the reference input terminal of SA circuit, and the input is the reference voltage V. ref .

[0071] NMOS transistors 503 and 504 form a negative feedback circuit to ensure the stability of the voltage SENBL on BL.

[0072] The source of NMOS transistor 503 is connected to the first node N1, the gate is connected to the second node fb, and the drain is connected to the output terminal. Here, NMOS transistor 503 can be referred to as the "first NMOS transistor" of the SA circuit. The connection method of NMOS transistor 503 is similar to... Figure 4 The connection method of the NMOS transistor 403 shown is exactly the same.

[0073] The gate of NMOS transistor 504 is connected to the first node N1, the drain is connected to the second node fb, and the source is connected to the third node N3. Here, NMOS transistor 504 can still be referred to as the "second NMOS transistor" of the SA circuit. Figure 5 In the implementation, the source of NMOS transistor 504 is no longer grounded, but instead connected to the third node N3.

[0074] Specifically, unlike Figure 4 ,exist Figure 5 In the circuit structure, the source of NMOS transistor 504 is changed from ground to be connected to the drain of NMOS transistor 505. Therefore, in addition to forming a negative feedback loop, NMOS transistor 504 is also multiplexed to form a left branch, which is used in conjunction with PMOS transistor 502 and NMOS transistor 505, as detailed below, to stabilize the feedback loop and prevent loop oscillation.

[0075] Specifically, the gate of the PMOS transistor 502 is connected to the second reference voltage V. ref’ The source is connected to the power supply terminal, and the drain is connected to the second node fb. Here, PMOS transistor 502 can still be referred to as the "second PMOS transistor" of the SA circuit.

[0076] The drain of NMOS transistor 505 is connected to the third node N3, which is the same as the source of NMOS transistor 504. The gate is connected to the second node fb, and the source is grounded. Here, although the connection method is similar to... Figure 4 Although different from the standard NMOS transistor, for convenience, the NMOS transistor 505 can still be referred to as the "third NMOS transistor" of the SA circuit.

[0077] Here, the second reference voltage V ref’ It can still be used for voltage pre-charging of BL, and can be used in the path composed of NMOS transistors 504 and 505 to reduce the impedance of the second node fb, so as to ensure the stability of the feedback loop composed of NMOS transistors 503 and 504.

[0078] In practice, a pre-charge circuit can also be used before performing a read operation at the second reference voltage V. ref’ With the participation of [unclear], BL is precharged to a predetermined voltage, for example, SENBL is 0.8V, and then the precharge circuit is disconnected from BL. Since the gate current of the MOS transistor approaches zero, when the left branch is turned on, the current flowing through PMOS transistor 502, NMOS transistors 504 and 505 is equal.

[0079] When there is a certain disturbance on BL, such as an increase in the voltage SENBL, the gate-source voltage of the NMOS transistor 504 operating in the saturation region increases, leading to an increase in drain current. This causes a decrease in the voltage of the second node fb. Since the gate-source voltage of the NMOS transistor 504 remains unchanged, the voltage of SENBL decreases as the voltage of the second node fb decreases. Therefore, by introducing a negative feedback loop composed of NMOS transistors 503 and 504, the voltage of SENBL can be clamped at a predetermined voltage.

[0080] Since the voltages at the first node N1 and the second node fb tend to stabilize, and the second reference voltage V ref’ Since the voltage remains constant, NMOS transistors 504 and 505 have relatively stable drain-source voltage drops, which in turn ensures the stability of the fb voltage.

[0081] Similarly, during a read operation, when the selected memory cell stores 0, the transistor containing the selected memory cell tends to be off. Therefore, the current through BL is small, meaning the current flowing through NMOS transistor 503 is small. Consequently, NMOS transistor 503 operates in the linear region, and the drain-source voltage is small. At this time, the reference current I flowing through PMOS transistor 501... ref The current is greater than the current flowing through the NMOS transistor 503 (i.e., the current on bit line BL), therefore the output is high, for example, close to the supply voltage V. DD The high level.

[0082] When the selected memory cell stores 1, the transistor containing the selected memory cell is turned on, so the current in BL is large, that is, the current flowing through NMOS transistor 503 is large. Therefore, NMOS transistor 503 operates in the saturation region, PMOS transistor 501 is turned off, and sain outputs a low level.

[0083] In some implementations, an inverter can be connected after the SA output so that the SA circuit outputs a low level when the selected cell stores 0, and a high level when the selected cell stores 1. In this case, the output of the SA circuit can be equivalent to... Figure 1 The output SAOUT is shown.

[0084] exist Figure 5 In the SA circuit shown, a negative feedback circuit composed of NMOS transistors 503 and 504 is present to clamp the SENBL voltage at a predetermined voltage after pre-charging. Therefore, it is necessary to prevent the feedback loop from oscillating. Since the node frequency of the main node (i.e., the first node N1) is low and difficult to change under relatively fixed resistance and capacitance conditions, this invention introduces an NMOS transistor 505 that operates in the saturation region, with its gate connected to the secondary node fb, its drain connected to the source of NMOS transistor 504, and its source grounded. This also reduces the impedance of the secondary point of the negative feedback circuit (i.e., the second node fb) and increases the node frequency of the second node fb. Because the node frequencies of the main node and the secondary stage differ significantly, the loop stability of the feedback loop can be ensured.

[0085] Therefore, by using the NMOS transistor 505 connected as above... Figure 4 Replacing the diode-connected NMOS transistors 405 and 406 as shown, and appropriately reusing NMOS transistor 504, can similarly reduce the impedance of node fb, increase the secondary frequency of node fb, and ensure loop stability. Furthermore, compared to the diode-connected dual-transistor structure, Figure 5 The structure shown saves the footprint of a transistor, thereby further reducing the area consumption of the SA module circuit while ensuring the overall SA operating performance.

[0086] Although the SA circuit of the present invention has been described above in conjunction with the memory block structure of NAND flash memory, it should be understood that the SA circuit of the present invention can also be applied to NOR flash memory, etc. Therefore, the present invention can also be implemented as a memory including the SA circuit of the present invention as described above. The memory can be a non-volatile memory, such as NAND flash memory or NOR flash memory. The memory can also be a volatile memory.

[0087] Furthermore, the present invention can also be implemented as an electronic device, including the memory described above.

[0088] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A readout amplifier circuit, comprising: The first PMOS transistor (501) has its source connected to the power supply terminal, its gate connected to the reference voltage, and its drain connected to the output terminal. The first NMOS transistor (503) has its drain connected to the output terminal, its gate connected to the second node (fb), and its source connected to the first node (N1). The first node is connected to the bit line (BL) of the memory. The second NMOS transistor (504) has its drain connected to the second node, its gate connected to the first node, and its source connected to the third node (N3). The second PMOS transistor (502) has its source connected to the power supply terminal, its gate connected to the second reference voltage, and its drain connected to the second node. The third NMOS transistor (505) has its drain connected to the third node, its gate connected to the second node, and its source grounded.

2. The readout amplifier circuit as described in claim 1, wherein, The sense amplifier circuit is used to output the stored data in the memory cell connected to the bit line during a read operation or verification operation.

3. The readout amplifier circuit as described in claim 2, wherein, The first NMOS transistor and the second NMOS transistor form a negative feedback loop for stabilizing the voltage on the bit line.

4. The readout amplifier circuit as described in claim 3, wherein, The bit line is connected to a pre-charge circuit before the read or verification operation and is pre-charged to the clamping voltage by the second reference voltage input to the gate of the second PMOS transistor.

5. The readout amplifier circuit as described in claim 4, wherein, The negative feedback loop stabilizes the clamping voltage on the bit line during read or verification operations.

6. The readout amplifier circuit as described in claim 2, wherein, The output terminal is connected to an inverter, and the output of the inverter is used to represent the stored data.

7. The readout amplifier circuit as described in claim 2, wherein, The second PMOS transistor provides a stable current to the second and third NMOS transistors connected in series via a second reference voltage connected to its gate, and reduces the impedance of the second node.

8. A memory comprising: The readout amplifier circuit as described in any one of claims 1-7 is used to read and amplify the current signal on the bit line to determine the stored content of the selected memory cell.

9. An electronic device comprising the memory as claimed in claim 8.

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