Memory, method of operating memory, and method of operating memory system

Abstract

A memory, a method of operating a memory, and a method of operating a memory system are disclosed. The method of operating a memory includes performing an error checking operation, detecting N bad sections during the error checking operation, where N is an integer equal to or greater than 1, stopping the error checking operation in response to detecting the N bad sections, transferring information about the N bad sections to a memory controller, and resuming the error checking operation in response to the information about the N bad sections being transferred to the memory controller.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0082245, filed on June 24, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of the present invention relate to memories and memory systems. Background Technology

[0004] In the early stages of the semiconductor memory industry, wafers contained many perfectly good bare dies, meaning that memory chips manufactured using semiconductor processes had no defective memory cells. However, as the capacity of memory devices increased, manufacturing memory devices without any defective memory cells became difficult, and it is now arguably virtually impossible. To address this problem, a repair method has been developed that includes redundant memory cells in the memory device and replaces defective memory cells with these redundant cells.

[0005] Another solution to this problem is to use an error correction circuit (ECC) in the memory system to correct errors that occur in the memory cells as well as errors that occur when data is transferred during the read and write processes of the memory system. Summary of the Invention

[0006] Embodiments of the present invention relate to error checking techniques in memory and memory systems.

[0007] According to one embodiment of the present invention, a method for operating a memory includes: performing an error checking operation; detecting N bad sectors during the error checking operation, where N is an integer equal to or greater than 1; stopping the error checking operation in response to detecting the N bad sectors; transmitting information about the N bad sectors to a memory controller; and resuming the error checking operation in response to the transmission of information about the N bad sectors to the memory controller.

[0008] According to another embodiment of the present invention, a method for operating a memory system includes: performing an error checking operation in the memory by the memory; during the error checking operation in the memory, detecting N bad sectors by the memory, where N is an integer equal to or greater than 1; stopping the error checking operation by the memory in response to detecting N bad sectors in the memory; requesting bad sector information from the memory by a memory controller; transmitting information about the N bad sectors to the memory controller by the memory; and resuming the error checking operation by the memory in response to the transmission of information about the N bad sectors.

[0009] According to another embodiment of the present invention, a memory includes: a memory core including a plurality of memory cells; an error correction circuit adapted to: correct errors in data read from the memory core based on an error correction code read from the memory core; an error checking operation control circuit adapted to: check for errors in data stored in the memory core by using the error correction circuit during an error checking operation; a bad segment detection circuit adapted to detect bad segments based on detected errors; and a bad segment storage circuit adapted to store addresses of bad segments detected by the bad segment detection circuit, wherein the error checking operation control circuit is further adapted to: stop the error checking operation when the number of bad segment addresses stored in the bad segment storage circuit during the error checking operation is N, wherein N is an integer equal to or greater than 1.

[0010] According to another embodiment of the present invention, a memory includes: a memory core including segments; and a control circuit configured to: perform an error detection operation on the segments to detect one or more bad segments in the segments, pause the error detection operation when a predetermined number of bad segments are detected, and resume the paused error detection operation after information about the detected bad segments is provided to an external device, wherein at least a predetermined number of errors are detected from data stored in the bad segments by means of the error detection operation. Attached Figure Description

[0011] Figure 1 This is a block diagram illustrating a memory system 100 according to an embodiment of the present invention.

[0012] Figure 2 This describes an embodiment of the present invention. Figure 1 The block diagram of memory 120 is shown.

[0013] Figure 3 This describes an embodiment of the present invention. Figure 1 The flowchart shows the error checking operation of the memory system 100. Detailed Implementation

[0014] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in the various drawings and embodiments of the invention.

[0015] Figure 1 This is a block diagram illustrating a memory system 100 according to an embodiment of the present invention.

[0016] The memory controller 110 can control the operation of the memory 120 according to the request of the host. The host may include a central processing unit (CPU), a graphics processing unit (GPU), and an application processor (AP), etc. The memory controller 110 may include a host interface 111, a control block 113, a command generator 115, and a memory interface 117. The memory controller 110 may be included in the CPU, GPU, and AP, etc. In this case, the host may refer to the structure other than the memory controller 110 in these structures. For example, when the memory controller 110 is included in the CPU, the host in the figure may refer to other components in the CPU besides the memory controller 110.

[0017] The host interface 111 can be an interface used for communication between the host and the memory controller 110.

[0018] Control block 113 can control the overall operation of memory controller 110 and schedule operations to be commanded to memory 120. Control block 113 can change the order in which requests are received from the host and the order in which operations to be commanded to memory 120 are executed to improve the performance of memory 120. For example, even if the host requests a read operation to memory 120 first and then requests a write operation, the order can be adjusted so that the write operation is performed before the read operation.

[0019] Command generator 115 can generate commands to be applied to memory 120 according to the order of operations determined by control block 113.

[0020] Memory interface 117 can be used as an interface between memory controller 110 and memory 120. Commands and addresses (CA) can be transmitted from memory controller 110 to memory 120 through memory interface 117, and data (DATA) can be sent / received. Memory interface 117 can also be referred to as the PHY interface.

[0021] The memory controller 110 can control the memory 120 in an error-checking operation mode. When the control block 113 determines that the memory 120 should operate in an error-checking operation mode, the command generator 115 can generate a command to control the memory 120 in the error-checking operation mode, and the memory interface 117 can transmit the command generated by the command generator 115 to the memory 120. The memory controller 110 can request bad segment information collected by the memory 120 during error-checking operations and receive bad segment information from the memory 120.

[0022] The memory 120 can perform operations commanded by the memory controller 110. (See below for reference.) Figure 2 Detailed description of memory 120.

[0023] Figure 2 This describes an embodiment of the present invention. Figure 1 The block diagram of memory 120 is shown.

[0024] refer to Figure 2 The memory 120 may include a command address receiving circuit 201, a data transceiver circuit 203, a command decoder 210, a row control circuit 230, a column control circuit 240, an address control circuit 250, an error correction circuit 261, an error correction code generation circuit 263, an error checking operation control circuit 271, a bad segment detection circuit 273, a bad segment storage circuit 275, and a memory core 280.

[0025] The command address receiving circuit 201 can receive commands and addresses CA. Depending on the type of memory 120, commands and addresses can be input to the same input terminal, or they can be input to different input terminals. Here, it is shown that commands and addresses are input to the same input terminal. Command and address CA can be multiple bits.

[0026] The data transceiver circuit 203 can receive or transmit data DATA. During a write operation, the data transceiver circuit 203 can receive data DATA to be written to the memory core 280, and during a read operation, it can transmit data DATA read from the memory core 280.

[0027] Command decoder 210 can decode commands and addresses (CA) to determine the type of operation performed by the memory controller on the memory.

[0028] When a row-based operation, such as an activation operation or a precharge operation, is commanded as a result of decoding by the command decoder 210, the row control circuit 230 can control these operations. The activation signal ACT can be a signal that commands the activation operation, and the precharge signal PCG can be a signal that commands the precharge operation.

[0029] When column-based operations such as write and read operations are commanded as the decoding result of command decoder 210, column control circuitry 240 can control these operations. The write signal WR can be a signal commanding a write operation, and the read signal RD can be a signal commanding a read operation.

[0030] When the command decoder 210 triggers the error check operation mode, the memory 120 can operate in the error check operation mode. In the error check operation mode, the memory 120 can operate under the control of the error check operation control circuit 271.

[0031] The address control circuit 250 can determine the address received from the command decoder 210 as either row address R_ADD or column address C_ADD and transmit it to the memory core 280. As the decoding result of the command decoder 210, the address control circuit 250 can determine the received address as row address R_ADD when a command activation operation is initiated, and determine the received address as column address C_ADD when a read operation or write operation is indicated.

[0032] Error correction circuit 261 can correct errors in data DATA' read from memory core 280 based on error correction code (ECC) read from memory core 280 during a read operation. Here, error correction can mean: detecting an error in data DATA', and correcting the error in data DATA' when it is detected. Error correction circuit 261 can detect and correct errors in data DATA' along with the error correction code (ECC). When an error in data DATA' is detected and corrected, the data DATA' input to error correction circuit 261 and the data DATA output from error correction circuit 261 may be different from each other. Error signal ERR can be a signal activated when error correction circuit 261 detects an error.

[0033] Error correction code generation circuit 263 can generate error correction code (ECC) based on data DATA during a write operation. During the write operation, the error correction code (ECC) can be generated based on data DATA, but errors in the data DATA may not be corrected. Therefore, the data DATA input to error correction code generation circuit 263 and the data DATA output from error correction code generation circuit 263 can be the same.

[0034] Error checking operation control circuit 271 can control error checking operations. Error checking operations can also be referred to as Error Check and Scrub (ECS) operations, and can represent the operation of reading data DATA' from memory core 280 and checking for errors in data DATA' using error correction circuit 261 to detect areas with many errors. When the error checking operation mode is set, error checking operation control circuit 271 can control the error checking operation. Since the rows and columns of memory core 280 need to be controlled during error checking operations, error checking operation control circuit 271 can control row control circuit 230 and column control circuit 240 during error checking operations. Error checking operations can be performed while changing addresses. During error checking operations, the row address R_ADD_E and column address C_ADD_E generated from error checking operation control circuit 271 can be used.

[0035] The bad segment detection circuit 273 can detect bad segments based on errors detected during error checking operations. For example, the bad segment detection circuit 273 can count the number of errors for each row, and determine that the row is a bad segment when the number of errors for a row exceeds a threshold. Since the bad segment detection circuit 273 receives addresses R_ADD_E and C_ADD_E as well as the error signal ERR, it can detect which part of the memory core 280 is being checked and whether an error has been detected.

[0036] The bad segment storage circuit 275 can store the addresses of bad segments detected by the bad segment detection circuit 273, namely BAD_ADD. There may be a limit to the number of bad segment addresses that can be stored in the bad segment storage circuit 275. For example, the bad segment storage circuit 275 may only be able to store one bad segment address, or it may be able to store three bad segment addresses. When the bad segment storage circuit 275 is full, the full signal FULL can be activated. When the full signal FULL is activated, the error checking operation control circuit 271 can stop the error checking operation.

[0037] The memory core 280 can execute operations commanded by internal command signals ACT, PCG, WR, and RD. The memory core 280 may include components for activation, precharge, read, and write operations, such as a cell array comprising memory cells arranged in multiple rows and columns, a row decoder for activating / deactivating rows of the cell array, and a column decoder for inputting / outputting data from the cell array. When the activation signal ACT is activated, a row selected based on row address R_ADD within the rows of the memory core 280 can be activated. When the precharge signal PCG is activated, the activated row can be deactivated. When the write signal WR is activated, data DATA' and error correction code ECC can be written to a column selected based on column address C_ADD within the columns of the memory core 280. When the read signal RD is activated, data DATA' and error correction code ECC can be read from a column selected based on column address C_ADD within the columns of the memory core 280. During the error checking operation, the addresses R_ADD_E and C_ADD_E generated by the error checking operation control circuit 271 can be used instead of the addresses R_ADD and C_ADD generated by the address control circuit 250.

[0038] During the activation operation of memory 120, the row selected based on the row address R_ADD in memory core 280 can be activated. In other words, the data in the selected row can be sensed. Read and write operations of memory 120 can be performed in the active state.

[0039] During a read operation of memory 120, data DATA' and error correction code ECC can be read from the memory cell of the column selected based on column address C_ADD in the selected row of memory core 280. Error correction circuit 261 can correct errors in data DATA' based on error correction code ECC, and the erroneously corrected data DATA can be transmitted to memory controller 110 via data transceiver circuit 203.

[0040] During a write operation of memory 120, data transceiver circuit 203 can receive data DATA transmitted from memory controller 110. Error correction code generation circuit 263 can generate error correction code ECC based on data DATA, and write data DATA and error correction code ECC into the memory cell of the selected column in the selected row of memory core 280, based on column address C_ADD.

[0041] Figure 3 This describes an embodiment of the present invention. Figure 1 The flowchart shows the error checking operation of the memory system 100.

[0042] refer to Figure 3 First, in operation S301, memory 120 can enter error checking operation mode. Memory 120 can enter error checking operation mode when memory controller 110 commands memory 120 to enter based on command and address CA.

[0043] Now, in operation S303, memory 120 is able to perform an error checking operation. The error checking operation can be performed by the following steps: reading data DATA' and error correction code ECC from memory core 280 based on addresses R_ADD_E and C_ADD_E generated by error checking operation control circuit 271, and checking whether data DATA' has errors based on error correction circuit 261. Since the error checking operation is used to check for errors in data DATA', data DATA read from memory core 280 and error-corrected by error correction circuit 261 may not be transmitted to memory controller 110. During the error checking operation, bad segment detection circuit 273 can detect bad segments based on errors detected during the error checking operation. For example, bad segment detection circuit 273 can count the number of errors in each row, and determine that the row is a bad segment when the number of errors in a row is equal to or greater than a threshold (e.g., 10). Furthermore, bad segment storage circuit 275 can store the address BAD_ADD of the bad segments determined by bad segment detection circuit 273.

[0044] When the number of bad segment addresses BAD_ADD stored in the bad segment storage circuit 275 is not N (NO in operation S305), that is, when the number of bad segments stored in the bad segment storage circuit 275 is less than N, the error checking operation control circuit 271 can change addresses R_ADD_E and C_ADD_E in operation S307, and can perform the error checking operation again in operation S303. Here, N can represent the maximum storage capacity of the bad segment storage circuit 275. For example, when the bad segment storage circuit can only store one bad segment address, N = 1.

[0045] When the number of bad segments stored in the bad segment storage circuit 275 reaches N (Yes in operation S305), the bad segment storage circuit 275 can activate the full signal FULL, and the error checking operation control circuit 271 can stop the error checking operation in response to the full signal FULL in operation S309. The error checking operation can be an operation for collecting information about bad segments. When the bad segment storage circuit 275 is full and it is no longer possible to store information about bad segments, the error checking operation does not need to be performed. Therefore, the error checking operation can be stopped.

[0046] In operation S311, the memory controller 110 may request bad segment information from the memory 120. When the memory controller 110 requests bad segment information from the memory 120 based on the command and address CA, the command decoder 210 may recognize the request and notify the bad segment storage circuit 275.

[0047] In operation S313, the bad segment storage circuit 275 can transmit the stored bad segment information to the memory controller 110 via the data transceiver circuit 203. After the bad segment information is transmitted to the memory controller 110, the bad segment storage circuit 275 can clear the bad segment information stored therein. That is, the bad segment storage circuit 275 can be initialized or reset. In addition, the full signal FULL can be deactivated.

[0048] After the bad segment information is transmitted to the memory controller 110, the new bad segment information (i.e., the bad segment address) can be stored in the bad segment storage circuit 275. Therefore, the error checking operation can be resumed. That is, the addresses R_ADD_E and C_ADD_E used for the error checking operation can be changed in operation S307, and the error checking operation can be performed again in operation S303.

[0049] Whether error checking is in progress or stopped, the memory controller 110 can terminate the error checking operation mode of the memory 120 and terminate the error checking operation when it commands the error checking operation mode to stop.

[0050] refer to Figure 3 When the bad segment storage circuit 275 is full during an error checking operation, it is impossible to collect new bad segment information. Therefore, unnecessary error checking operations can be stopped. Furthermore, when the bad segment storage circuit 275 is cleared, the error checking operation can be performed again, and the collection of bad segment information can be resumed.

[0051] According to embodiments of the present invention, errors can be checked in memory and memory systems.

[0052] While the invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the claims. Furthermore, embodiments may be combined to form additional embodiments.

Claims

1. A method for operating a memory, comprising: Perform error checking; During the error checking operation, N bad segments are detected, where N is an integer equal to or greater than 1; In response to the detection of the N bad segments, the error checking operation is stopped when the bad segment storage circuit is full. The information about the N bad sectors is transmitted to the memory controller; Clear information about the N bad segments; as well as In response to the transmission of information about the N bad sectors to the memory controller, the error checking operation is resumed.

2. The method according to claim 1, wherein, Performing the error checking operation includes: Read data and error correction codes from the selected memory cell of the memory core; and Errors in the data are detected based on the error correction code.

3. The method according to claim 2, wherein, Performing the error checking operation also includes: Based on the error correction code, the detected errors are corrected to generate data with corrected errors; and The erroneously corrected data is written into the selected memory cell of the memory core.

4. The method according to claim 3, wherein, The error checking operation is repeated by changing the selected memory cell of the memory core.

5. The method according to claim 1, wherein, Detecting the N bad segments includes: When the number of errors detected in a specific region during the error checking operation is equal to or greater than a threshold, the specific region is detected as the bad segment; and Check if the number of detected bad segments is N.

6. A method for operating a memory system, comprising: The error checking operation in the memory is performed by the memory. During the error checking operation in the memory, N bad sectors are detected by the memory, where N is an integer equal to or greater than 1; In response to the detection of the N bad segments in the memory, the error checking operation is stopped by the memory when the bad segment storage circuit of the memory is full. The memory controller requests bad sector information from the memory; The memory transmits information about the N bad sectors to the memory controller. as well as The information about the N bad sectors is cleared from the memory; as well as In response to the transmission of information about the N bad segments, the error checking operation is resumed by the memory.

7. The method according to claim 6, wherein, The error checking operation performed by the memory includes: Read data and error correction codes from the selected memory cell of the memory core; and Errors in the data are detected based on the error correction code.

8. The method according to claim 7, wherein, The error checking operation performed by the memory further includes: Based on the error correction code, the detected errors are corrected to generate data with corrected errors; and The erroneously corrected data is written into the selected memory cell of the memory core.

9. The method according to claim 8, wherein, The error checking operation is repeated by changing the selected memory cell of the memory core.

10. The method of claim 7, wherein, Detecting the N bad segments includes: When the number of errors detected in a specific region during the error checking operation is equal to or greater than a threshold, the specific region is detected as the bad segment; and Check if the number of detected bad segments is N.

11. A memory, comprising: A memory core, which comprises multiple memory cells; An error correction circuit, adapted to: correct errors in data read from the memory core based on an error correction code read from the memory core; An error checking operation control circuit, adapted to check for errors in data stored in the memory core during an error checking operation by using the error correction circuit; A bad section detection circuit, which is suitable for detecting bad sections based on detected errors; as well as A bad segment storage circuit, adapted to store the addresses of bad segments detected by the bad segment detection circuit. The error checking operation control circuit is further adapted to stop the error checking operation when N bad segment addresses are full in the bad segment storage circuit during the error checking operation, where N is an integer equal to or greater than 1.

12. The memory according to claim 11, in, The memory is further adapted to: in response to a request for bad segment information from the memory controller, transmit the bad segment address stored in the bad segment storage circuit to the memory controller, and The error checking operation control circuit is further adapted to resume the stopped error checking operation in response to the bad segment address being transmitted to the memory controller.

13. The memory according to claim 12, wherein, After the bad segment address stored in the bad segment storage circuit is transmitted to the memory controller, the bad segment storage circuit is reset.

14. The memory according to claim 11, wherein, The error checking operation control circuit is further adapted to: during the error checking operation, control the error correction circuit to write the data with corrected errors into the memory core.

15. The memory according to claim 11, wherein, N represents the maximum storage capacity of the bad segment storage circuit.

16. A memory comprising: A memory core, which includes segments; as well as Control circuit, the control circuit: An error detection operation is performed on the segment to detect one or more bad segments within the segment. When a predetermined number of bad segments are detected, the error detection operation is paused when one or more bad segments are full in the bad segment storage circuit of the memory core. Clear the information about the detected bad segments when the information about the bad segments is provided to the external device; Resume the paused error detection operation. Specifically, through the error detection operation, at least a predetermined number of errors are detected from the data stored in the bad segment.

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