Semiconductor Structure and Method of Forming the Same

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a method for forming the same. The method for forming the semiconductor structure includes: providing a wafer having opposite first and second surfaces, with a stepped surface at the edge of the wafer, the distance between the stepped surface and the second surface being less than the distance between the first and second surfaces, and the stepped surface and the first surface being connected by a connecting surface to form a step; forming a protective layer at least in the corner region formed by the stepped surface and the connecting surface; providing a carrier plate and performing a bonding process. In the bonding process step, an adhesive layer is formed between the first surface and the surface of the carrier plate, and the first surface is bonded to the surface of the carrier plate through the adhesive layer; after the bonding process is performed, the protective layer is removed; and the wafer is thinned in a direction from the second surface towards the first surface. Embodiments of the present disclosure are at least beneficial to avoiding the phenomenon of glue overflow at the edge of the wafer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and particularly to semiconductor structures and methods for forming the same. Background Art

[0002] With the development of semiconductor technology, the demand for reducing the size in the wafer manufacturing process is increasing, making the thickness of the wafer thinner and thinner. Currently, there are already processes for thinning the wafer to a relatively thin size, but the stability of the thinner wafer is poor. The thinning process and the metallization process will apply additional stress to the thinned wafer, resulting in warping or breaking of the thinned wafer.

[0003] Therefore, before thinning the wafer, it is necessary to temporarily bond the wafer to a carrier wafer to avoid the impact of the thinning process or the metallization process on the wafer. However, in the current process of bonding the wafer to the carrier wafer, there is a phenomenon that the adhesive layer between the wafer and the carrier wafer overflows to the edge of the wafer, and the adhesive layer at the edge of the wafer will affect the processing of the wafer. Summary of the Invention

[0004] The semiconductor structure and the method for forming the same provided by the embodiments of the present disclosure are at least beneficial to avoiding the phenomenon of glue overflow at the wafer edge.

[0005] An embodiment of the present disclosure provides a method for forming a semiconductor structure, including: providing a wafer, the wafer having opposite first and second surfaces, the edge of the wafer having a stepped surface, the distance between the stepped surface and the second surface being less than the distance between the first surface and the second surface, and the stepped surface and the first surface being connected by a connecting surface to form a step; forming a protective layer, the protective layer being at least located in the corner region formed by the stepped surface and the connecting surface; providing a carrier plate and performing a bonding process, in the bonding process step, forming an adhesive layer between the first surface and the surface of the carrier plate, and bonding the first surface to the surface of the carrier plate through the adhesive layer; after performing the bonding process, removing the protective layer; and thinning the wafer in the direction from the second surface to the first surface.

[0006] In some embodiments, forming the protective layer includes: forming an initial protective layer, the initial protective layer being located on the first surface and the corner region; removing the initial protective layer located on the first surface, and the remaining initial protective layer being used as the protective layer.

[0007] In some embodiments, the material of the initial protective layer is photoresist.

[0008] In some embodiments, the material of the initial protective layer is negative photoresist, and removing the initial protective layer located on the first surface includes: performing an exposure process on the initial protective layer by using a mask covering the first surface and exposing the wafer edge; and removing the initial protective layer located on the first surface by using an etching solution.

[0009] In some embodiments, in a direction parallel to the first surface, the thickness of the protective layer is 0.4 mm to 3 mm.

[0010] In some embodiments, in a direction from the second surface to the first surface, the distance from the end of the protective layer away from the step surface to the second surface is greater than or equal to the distance from the first surface to the second surface.

[0011] In some embodiments, in a direction from the second surface to the first surface, the thickness of the protective layer is 100 μm to 350 μm.

[0012] In some embodiments, in a direction from the second surface to the first surface, the distance from the end of the protective layer away from the step surface to the second surface is less than the distance from the first surface to the second surface, and the distance from the end of the protective layer away from the step surface to the second surface is greater than a preset value.

[0013] In some embodiments, the adhesive layer is also located on the connection surface adjacent to the first surface.

[0014] In some embodiments, in a direction from the second surface to the first surface, the thickness of the adhesive layer is 20 μm to 80 μm.

[0015] In some embodiments, the corner region is disposed around the edge of the wafer in a circle, and the protective layer is located in a part of the corner region.

[0016] In some embodiments, the corner region is disposed around the edge of the wafer in a circle, and the protective layer located in the corner region is disposed around the edge of the wafer in a circle.

[0017] In some embodiments, the thinning process of the wafer includes: in a direction from the second surface to the first surface, grinding the second surface until the step surface is removed.

[0018] In some embodiments, the wafer has a plurality of conductive structures extending from the first surface to the second surface, and the thinning process of the wafer includes: grinding the second surface to expose the conductive structures while removing the step surface.

[0019] In some embodiments, in a direction from the first surface to the second surface, the length of the conductive structure is less than or equal to the length of the protective layer.

[0020] Correspondingly, another aspect of the embodiments of the present disclosure further provides a semiconductor structure, including: a wafer having opposite first and second surfaces, the edge of the wafer having a step surface, the distance between the step surface and the second surface being less than the distance between the first surface and the second surface, and the step surface and the first surface being connected by a connection surface to form a step, wherein the wafer has a plurality of conductive structures extending from the first surface to the second surface; a protective layer at least located in the corner region formed by the step surface and the connection surface.

[0021] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages: The second side of the wafer is the surface to be thinned. Bond the first side opposite to the second side to the surface of the carrier plate to achieve temporary bonding of the wafer and the carrier plate. Wherein, the edge of the wafer includes a corner area formed by a step surface and a connecting surface. Before temporary bonding, form a protective layer in the corner area, and then form an adhesive layer to bond the first side to the surface of the carrier plate. Since the protective layer has been formed in the corner area, the adhesive layer in the bonding process cannot overflow to the corner area of the wafer edge, effectively avoiding the phenomenon of glue overflow at the wafer edge. And after removing the protective layer, thin the wafer without edge glue overflow, further avoiding the influence of edge glue overflow on the thinning process. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are illustrated by way of example in the accompanying drawings, and these exemplary illustrations do not limit the embodiments unless otherwise stated. The figures in the accompanying drawings do not constitute a scale limitation; In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the following-described drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0023] Figures 1 to 2 Schematic diagrams of the steps of a method for forming a semiconductor structure in the prior art;

[0024] Figures 3 to 11 Schematic diagrams of the steps of a method for forming a semiconductor structure provided by the embodiments of the present disclosure;

[0025] Figure 12 Side view of a wafer including a first side in a semiconductor structure provided by the embodiments of the present disclosure;

[0026] Figure 13 Side view of a wafer including a first side in another semiconductor structure provided by the embodiments of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] As can be seen from the background art, in the current process of bonding a wafer and a carrier for the wafer, there is a phenomenon that the adhesive layer between the wafer and the carrier overflows to the edge of the wafer, that is, the phenomenon of glue overflow at the wafer edge. The glue overflow at the wafer edge will affect the subsequent processing of the wafer.

[0028] Figures 1 to 2 Schematic diagrams of the steps of a method for forming a semiconductor structure in the prior art, refer to Figure 1 , Figure 1It is a semiconductor structure formed after the bonding process of wafer 10 and carrier wafer 20. Specifically, an adhesive layer 11 is formed between wafer 10 and carrier wafer 20. The adhesive layer 11 is used to bond wafer 10 and carrier wafer 20 together. During the process of forming the adhesive layer 11 between wafer 10 and carrier wafer 20, the adhesive layer 11 overflows to the edge of wafer 10. Refer to Figure 2 , after bonding wafer 10 and carrier wafer 20, the surface of wafer 10 away from carrier wafer 20 is thinned. During the thinning process, in addition to thinning wafer 10 in the direction pointing from wafer 10 to carrier wafer 20, the adhesive layer 11 at the edge of wafer 10 may fall off under the action of the thinning process. Since the adhesive layer 11 has a certain viscosity, the falling-off adhesive layer 11 with viscosity may adhere to the gears of the thinning equipment, causing the failure of the thinning equipment.

[0029] To solve the above problems, the embodiments of the present disclosure provide a method for forming a semiconductor structure and a semiconductor structure. In the method for forming a semiconductor structure, the second surface of the wafer is the surface to be thinned of the wafer, and the first surface opposite to the second surface is used to bond with the surface of the carrier plate, thereby realizing the temporary bonding of the wafer and the carrier plate. Among them, the edge of the wafer includes a corner area formed by a step surface and a connecting surface. Before the temporary bonding, a protective layer is formed in the corner area, and then an adhesive layer is formed to bond the first surface and the surface of the carrier plate. Since the protective layer has been formed in the corner area, the adhesive layer in the bonding process cannot overflow to the corner area of the wafer edge, effectively avoiding the phenomenon of glue overflow at the wafer edge. In addition, after removing the protective layer, the wafer without edge glue overflow is thinned, which also avoids the influence of edge glue overflow on the thinning process.

[0030] The following will elaborate on each embodiment of the present disclosure in conjunction with the drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present disclosure, many technical details are proposed for the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the embodiments of the present disclosure can still be realized.

[0031] Figures 3 to 11 It is a schematic diagram of each step of a method for forming a semiconductor structure provided by an embodiment of the present disclosure. And, Figures 3 to 11 It is a cross-sectional view of the semiconductor structure of each step in the direction from the first surface to the second surface.

[0032] Refer to Figure 3, A method for forming a semiconductor structure includes: providing a wafer 100 having opposite first and second surfaces 110 and 120, and a stepped surface 130 at the edge of the wafer 100. The distance between the stepped surface 130 and the second surface 120 is less than the distance between the first surface 110 and the second surface 120, and the stepped surface 130 and the first surface 110 are connected by a connecting surface 140 to form a step.

[0033] Wherein, the wafer 100 is the wafer 100 to be thinned. The second surface 120 of the wafer 100 can be the back surface of the wafer 100 to be thinned, and the first surface 110 facing the second surface 120 is the front surface of the wafer 100. A plurality of chips can be formed on the first surface 110 of the wafer 100, and the first surface 110 is also used for bonding the wafer 100 to temporarily bond the wafer 100 to a carrier.

[0034] In some embodiments, the second surface 120 can be the bottom surface of the substrate in the semiconductor structure for forming chips on the wafer. The substrate can be a semiconductor material. In one example, the substrate is a silicon substrate, and the subsequent thinning process of the second surface 120 is mainly the thinning process of the bottom surface of the silicon substrate.

[0035] The edge of the wafer 100 includes a stepped surface 130. In some embodiments, the stepped surface 130 is perpendicular to the direction from the first surface 110 to the second surface 120. One side of the stepped surface 130 adjacent to the edge of the wafer 100 is connected to the second surface 120, and the side of the stepped surface 130 facing the middle of the wafer 100 is connected to the first surface 110 by a connecting surface 140. The connecting surface 140 can be parallel to the direction from the first surface 110 to the second surface 120. Thus, the stepped surface 130 and the connecting surface 140 form a step, and the stepped surface 130 and the connecting surface 140 form a corner area 150 at the edge of the wafer 100. The stepped surface 130 can be used to carry a protective layer formed subsequently at the edge of the wafer 100, preventing the protective layer from falling off the edge of the wafer 100, and thus facilitating the reduction of the difficulty of forming the protective layer at the edge of the wafer 100.

[0036] Reference Figures 4 to 8 , forming a protective layer 103. The protective layer 103 is at least located in the corner area formed by the stepped surface 130 and the connecting surface 140. The protective layer 103 is used to protect the edge of the wafer 100 adjacent to the first surface 110. During the subsequent formation of the adhesive layer, the corner area of the edge of the wafer 100 filled with the protective layer 103 can prevent the adhesive layer 104 from overflowing into the corner area of the edge of the wafer 100, effectively avoiding the phenomenon of glue overflow at the edge of the wafer 100, and thus facilitating the avoidance of the influence of glue overflow at the edge of the wafer 100 on the thinning process of the wafer 100.

[0037] In some embodiments, the step of forming the protective layer 103 may include: reference Figure 4, an initial protective layer 101 is formed, and the initial protective layer 101 is located on the first surface 110 and the corner area; reference Figures 5 to 8 , the initial protective layer 101 located on the first surface 110 is removed, and the remaining initial protective layer 101 in the corner area serves as the protective layer 103. That is, first, the initial protective layer 101 is formed over the entire surface, and then the initial protective layer 101 located on the first surface 110 is selectively removed, so that the protective layer 103 located at the edge of the wafer 100 can be formed. Compared with the method of directly forming the protective layer 103 in the corner area at the narrow edge of the wafer 100, the above solution is beneficial to reducing the difficulty of forming the protective layer 103.

[0038] In some embodiments, the material of the initial protective layer 101 is photoresist. Photoresist is a relatively common masking material. Compared with other masking materials, the corner area can be well filled by spin-coating the photoresist. In this way, it is beneficial to form a protective layer 103 with a better fit to the corner area. In addition, the photoresist is relatively easy to remove. Using the photoresist as the protective layer 103, after removing the protective layer 103, it is possible to avoid the residue of the protective layer 103 on the edge of the wafer 100, and thus it is beneficial to avoid the influence of the residual protective layer 103 on the thinning equipment used for the thinning process. It can be understood that in some other embodiments, the material of the initial protective layer 101 can also be other masking materials that are relatively easy to remove.

[0039] Reference Figure 5 and Figure 6 , in some embodiments, the material of the initial protective layer 101 is negative photoresist. Removing the initial protective layer 101 located on the first surface 110 includes: exposing the initial protective layer 101 using a mask 102 that covers the first surface 110 and exposes the edge of the wafer 100; removing the initial protective layer 101 located on the first surface 110 using an etching solution. Using negative photoresist as the initial protective layer 101, the initial protective layer 101 can be exposed using the mask 102 that covers the first surface 110. If positive photoresist is used as the initial protective layer 101, the initial protective layer 101 needs to be exposed using a mask that covers the edge of the wafer 100. Compared with aligning the mask 102 that covers the first surface 110 with the first surface 110 of the wafer 100, the difficulty of aligning the mask that covers the edge of the wafer 100 with the edge of the wafer 100 is relatively high. Therefore, exposing the initial protective layer 101 using the mask 102 that covers the first surface 110 of the wafer 100 is beneficial to obtaining a more accurate pattern. Compared with using positive photoresist as the initial protective layer 101, using negative photoresist as the initial protective layer 101 is not only beneficial to forming a protective layer 103 with more precise dimensions, but also beneficial to reducing the difficulty of forming the protective layer 103.

[0040] Specifically, the initial protective layer 101 is a negative photoresist. The etchant for removing the initial protective layer 101 located on the first surface 110 can be a developer. After the initial protective layer 101 is exposed, the initial protective layer 101 located on the first surface 110 covered by the mask 102 is not exposed, and the initial protective layer 101 located at the edge of the wafer 100 is exposed. After the initial protective layer 101 is developed, the exposed initial protective layer 101 is insoluble in the developer, and the unexposed initial protective layer 101 is soluble in the developer. The initial protective layer 101 located on the first surface 110 is removed, forming a protective layer 103 at the edge of the wafer 100.

[0041] In some embodiments, referring to Figure 6 , along the direction parallel to the first surface 110, the thickness of the protective layer 103 is 0.4 mm to 3 mm. Define the thickness of the protective layer 103 as the first length L1. The first length L1 can be 0.4 mm to 3 mm. For example, it can be 0.5 mm, 1 mm, 2 mm, 2.5 mm, 2.8 mm, etc. If the thickness of the protective layer 103 is too thin, it cannot completely cover the corner area and is easily damaged during the subsequent formation of the adhesive layer, and thus cannot effectively block the adhesive layer. If the thickness of the protective layer 103 is too thick, a wider step surface 130 needs to be provided in the direction parallel to the first surface 110 to carry the protective layer 103. Generally, the size of the wafer 100 is fixed. Setting a wider step surface 130 will result in a smaller area of the wafer 100 for forming chips, causing waste of the area of the wafer 100 for forming chips. Therefore, setting the first length L1 to 0.4 mm to 3 mm not only helps to effectively block the adhesive layer 104 but also avoids waste of the area of the wafer 100 for forming chips.

[0042] Referring to Figure 6 and Figure 7 , in some embodiments, along the direction from the second surface 120 to the first surface 110, the distance from the end of the protective layer 103 away from the step surface 130 to the second surface 120 is greater than or equal to the distance from the first surface 110 to the second surface 120. That is, along the direction from the second surface 120 to the first surface 110, the protective layer 103 can be flush with the first surface 110, or the protective layer 103 can also extend a certain length out of the corner area. In this way, the protective layer 103 completely covers the connection surface 140 at the edge of the wafer 100, avoiding the contact between the adhesive layer formed on the first surface 110 and the connection surface 140 at the edge of the wafer 100, and effectively preventing the adhesive layer from overflowing to the edge of the wafer 100.

[0043] Referring to Figure 8, in some embodiments, in the direction from the second surface 120 towards the first surface 110, the distance from the end of the protective layer 103 away from the stepped surface 130 to the second surface 120 is less than the distance from the first surface 110 to the second surface 120, and the distance from the end of the protective layer 103 away from the stepped surface 130 to the second surface 120 is greater than a preset value. Herein, the preset value can be the thickness value for subsequent thinning of the second surface 120. When the distance between the side of the protective layer 103 away from the stepped surface 130 and the second surface 120 is greater than the preset value, during the subsequent thinning process of the second surface 120, the edge of the wafer 100 removed by thinning is also the edge of the wafer after removing the protective layer 103, rather than the area with the adhesive layer. Therefore, when the distance between the side of the protective layer 103 away from the stepped surface 130 and the second surface 120 is greater than the preset value, it can also effectively prevent the influence of the adhesive layer 104 overflowing to the edge of the wafer 100 on the thinning equipment.

[0044] In some embodiments, referring to Figure 6 , in the direction from the second surface 120 towards the first surface 110, the thickness of the protective layer 103 is 100um - 350um. Define the thickness of the protective layer 103 as the second length L2. The second length L2 can be 100um - 350um. For example, it can be 150um, 180um, 200um, 250um, 280um, etc. If the second length L2 is too long, during the bonding process, the protective layer 103 may be too close to the surface of the carrier plate, resulting in a smaller opening between the carrier plate and the protective layer 103. The smaller opening increases the difficulty of forming the adhesive layer between the carrier plate and the wafer 100. If the second length L2 is too small, it may cause the influence of the adhesive layer overflowing to the edge of the wafer 100 on the thinning equipment. Therefore, setting the second length L2 to 100um - 350um not only helps to avoid affecting the subsequent formation process of the adhesive layer 104, but also helps to avoid the influence of the adhesive layer 104 overflowing to the edge of the wafer 100 on the thinning equipment.

[0045] Figure 12 is a side view of a wafer including a first surface in a semiconductor structure provided by an embodiment of the present disclosure; Figure 13 is another side view of a wafer including a first surface in a semiconductor structure provided by an embodiment of the present disclosure.

[0046] In some embodiments, referring to Figure 12, the corner area 150 is disposed around the edge of the wafer 100 in a circle, and the protective layer 103 is located in a part of the corner area 150. Compared with the method of forming the adhesive layer without setting the protective layer 103 in the corner area 150, setting the protective layer 103 in a part of the corner area 150 is also beneficial to reducing the overflow of the adhesive on the edge of the wafer 100. If there is a small amount of adhesive layer on the edge of the wafer 100, after the small amount of adhesive layer falls off under the action of the thinning process, the small amount of adhesive layer cannot affect the thinning equipment. Moreover, if each wafer 100 has a small amount of edge overflow of the adhesive, after the thinning equipment for the thinning process processes a certain batch of wafers 100, the thinning equipment can be maintained for the falling-off adhesive layer, so as to avoid the adhesive layer from affecting the thinning equipment. Therefore, only setting the protective layer 103 in a part of the corner area 150 is also beneficial to avoiding the influence of the adhesive layer that overflows to the edge of the wafer 100 subsequently on the thinning equipment.

[0047] In some embodiments, referring to Figure 13 , the corner area 150 is disposed around the edge of the wafer 100 in a circle, and the protective layer 103 located in the corner area 150 is disposed around the edge of the wafer 100 in a circle. Setting the protective layer 103 in the corner area 150 around the edge of the wafer 100 in a circle is beneficial to avoiding the formation of an adhesive layer in the corner areas 150 at different positions on the edge of the wafer 100, more thoroughly preventing the occurrence of the adhesive overflow phenomenon on the edge of the wafer 100, avoiding the maintenance of the thinning equipment for the falling-off adhesive layer, and being beneficial to improving the processing efficiency of the wafer 100.

[0048] Referring to Figure 9 , after forming the protective layer 103, a carrier plate 200 is provided and a bonding process is performed. In the bonding process step, an adhesive layer 104 is formed between the first surface 110 and the surface of the carrier plate 200, and the first surface 110 is bonded to the surface of the carrier plate 200 through the adhesive layer 104.

[0049] In some embodiments, the carrier plate 200 may be a carrier wafer having the same shape and size as the wafer 100. The carrier wafer is used to provide mechanical support and protection for the wafer 100. Thus, it is not only beneficial to avoid the wafer 100 from breaking or deforming under the action of the thinning machine during the thinning process, but also, the wafer 100 bonded to the carrier plate 200 can use the processing equipment for manufacturing the standard wafer 100 to perform the backside processing process. The standard wafer is a wafer that has not been thinned. There is no need to re-modify the processing equipment suitable for the thinned wafer 100, nor to set up special jigs or wafer 100 boxes, which is beneficial to reducing the difficulty of processing the thinned wafer 100.

[0050] The bonding layer 104 is used to bond the wafer 100 to the carrier 200. In some embodiments, in addition to the bonding layer 104, a connection structure for bonding the wafer 100 to the carrier 200 is also formed between the wafer 100 and the carrier 200. Specifically, the step of forming the bonding layer 104 between the carrier 200 and the wafer 100 may include aligning the wafer 100 and the carrier 200, and injecting a bonding layer material between the wafer 100 and the carrier 200 to form the bonding layer 104 between the wafer 100 and the carrier 200.

[0051] In some embodiments, the bonding layer 104 is also located on the connection surface 140 adjacent to the first surface 110. Specifically, in the direction from the first surface 110 to the second surface 120, if the length of the end of the protective layer 103 away from the step surface 130 is smaller than the length from the first surface 110 to the second surface 120, a part of the connection surface 140 adjacent to the first surface 110 is not covered by the protective layer 103. After the bonding layer 104 is formed, the bonding layer 104 is located not only between the first surface 110 and the surface of the carrier 200, but also on the connection surface 140 adjacent to the first surface 110. Moreover, the bonding layer 104 on the connection surface 140 adjacent to the first surface 110 and the bonding layer 104 between the first surface 110 and the surface of the carrier 200 are integrally formed. Compared with the bonding layer 104 only between the first surface 110 and the surface of the carrier 200, the bonding layer 104 on the connection surface 140 adjacent to the first surface 110 increases the contact area between the wafer 100 and the bonding layer 104, thereby increasing the bonding strength between the wafer 100 and the bonding layer 104, which is beneficial to improving the bonding strength between the wafer 100 and the carrier 200.

[0052] In some embodiments, in the direction from the second surface 120 to the first surface 110, the thickness of the bonding layer 104 is 20um - 80um. For example, it can be 25um, 380um, 42um, 50um, 70um, etc. If the thickness of the bonding layer 104 is too thin, the wafer 100 may not be stably bonded to the carrier 200. If the thickness of the bonding layer 104 is too thick, it may cause waste of the bonding layer material. Therefore, setting the thickness of the bonding layer 104 to 20um - 80um is not only beneficial to stably bonding the wafer 100 to the carrier 200 using the bonding layer 104, but also beneficial to avoiding waste of the bonding layer material, and thus beneficial to reducing the processing cost of the bonding process.

[0053] Reference Figure 10, after the bonding process, the protective layer 103 is removed. In some embodiments, the material of the protective layer 103 is photoresist, and the process of removing the protective layer 103 can be an ashing process. The edge of the wafer 100 after removing the protective layer 103 does not have the adhesive layer 104, which avoids the influence on the thinning equipment caused by the peeling off of the adhesive layer 104 at the edge of the wafer 100 during the subsequent thinning process.

[0054] Reference Figure 11 , after removing the protective layer 103, it further includes: thinning the wafer 100 in the direction from the second surface 120 to the first surface 110. The thinning process can reduce the size of the wafer 100, which is beneficial to reducing the size of the chips formed on the wafer 100.

[0055] Reference Figure 11 , in some embodiments, thinning the wafer 100 includes: grinding the second surface 120 in the direction from the second surface 120 to the first surface 110 until the stepped surface is removed. The stepped surface is mainly used to carry the protective layer. After removing the protective layer, the stepped surface can be removed during the thinning process.

[0056] Reference Figures 10 to 11 , in some embodiments, the wafer 100 has a plurality of conductive structures 105 extending from the first surface 110 to the second surface 120. Thinning the wafer 100 includes: grinding the second surface 120 to expose the conductive structures 105 while removing the stepped surface 130.

[0057] The conductive structure 105 can be the lead-out wire of the semiconductor structure formed on the first surface 110. The material of the conductive structure 105 is a conductive material, for example, it can be at least one of copper, titanium nitride or tungsten.

[0058] Thinning the wafer 100 is not only used to reduce the size of the chips, but also to expose the conductive structures 105 on the second surface 120. When other semiconductor structures are stacked on the second surface 120, the conductive structures 105 exposed on the second surface 120 can be used to connect the semiconductor structures formed on the first surface 110 with the semiconductor structures stacked on the second surface 120, thereby realizing the multi-layer stacking between the semiconductor structures formed on different wafers 100.

[0059] In some embodiments, reference Figure 9, in the direction from the first surface 110 towards the second surface 120, the length of the conductive structure 105 is less than or equal to the length of the protective layer 103. In this way, before the thinning process, it can be ensured that in the direction from the first surface 110 towards the second surface 120, the length from one end of the conductive structure 105 away from the first surface 110 to the second surface 120 is greater than the length from one end of the protective layer 103 in contact with the stepped surface 130 to the second surface 120, so that when the conductive structure 105 is exposed by the thinning process, the stepped surface 130 can be removed.

[0060] In some embodiments, in the direction from the first surface 110 towards the second surface 120, the length of the conductive structure 105 can be 35um - 65um, for example, it can be 36um, 38um, 42um, 50um, 55um, etc.

[0061] In some embodiments, the wafer 100 includes a base layer. The first surface 110 of the wafer 100 is the top surface of the semiconductor structure formed on the base layer of the wafer 100, and the second surface 120 of the wafer 100 is the bottom surface of the base layer. After the second surface 120 of the wafer 100 is thinned to expose the conductive structure 105, it further includes: etching away a part of the thickness of the base layer from the second surface 120, in the direction from the first surface 110 towards the second surface 120, making the height on the side of the conductive structure 105 away from the first surface 110 higher than the height of the second surface 120, that is, making the conductive structure 105 extend out of the second surface 120, then forming an insulating layer on the bottom surface of the base layer and the conductive structure 105 extending out of the base layer, and using a chemical mechanical polishing process to remove the conductive structure 105 protruding from the base layer and the insulating layer on the conductive structure 105, thus forming the conductive structure 105 exposed from the insulating layer.

[0062] In the method for forming the semiconductor structure provided in the above embodiments, the second surface 120 of the wafer 100 is the surface to be thinned of the wafer 100. The first surface 110 opposite to the second surface 120 is bonded to the surface of the carrier 200 to achieve the temporary bonding of the wafer 100 and the carrier 200. Among them, the edge of the wafer 100 includes a corner area formed by the stepped surface 130 and the connecting surface 140. Before the temporary bonding, a protective layer 103 is formed in the corner area, and then an adhesive layer 104 is formed to bond the first surface 110 and the surface of the carrier 200. Since the protective layer 103 has been formed in the corner area, the adhesive layer 104 in the bonding process cannot overflow to the corner area of the edge of the wafer 100, effectively avoiding the phenomenon of glue overflow at the edge of the wafer 100. And, after removing the protective layer 103, the wafer 100 without edge glue overflow is thinned, further avoiding the influence of edge glue overflow on the thinning process.

[0063] On the other hand, an embodiment of the present disclosure further provides a semiconductor structure. The semiconductor structure provided by the embodiment of the present disclosure can be prepared by using the formation method of the semiconductor structure provided in the above embodiment. The semiconductor structure provided by the embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those in the foregoing embodiments, reference may be made to the detailed description of the foregoing embodiments, which will not be repeated hereinafter.

[0064] The semiconductor structure includes: a wafer 100 having opposite first and second surfaces 110 and 120, and a stepped surface 130 at the edge of the wafer 100. The distance between the stepped surface 130 and the second surface 120 is less than the distance between the first surface 110 and the second surface 120, and the stepped surface 130 and the first surface 110 are connected by a connecting surface 140 to form a step. A plurality of conductive structures 105 extend from the first surface 110 to the second surface 120 within the wafer 100; a protective layer 103 is at least located in the corner region formed by the stepped surface 130 and the connecting surface 140.

[0065] The stepped surface 130 is used to carry the protective layer 103, and the protective layer 103 is used to cover the edge of the wafer 100, preventing the adhesive layer formed subsequently for bonding the wafer 100 to the carrier from overflowing to the edge of the wafer 100. Furthermore, during the subsequent thinning process of the second surface 120 of the wafer 100, the adhesive layer overflowing to the edge of the wafer 100 is prevented from affecting the thinning equipment. In addition, thinning the second surface 120 of the wafer 100 can be used to expose the conductive structures 105 on the second surface 120.

[0066] For the semiconductor structure provided in the above embodiment, the edge of the wafer 100 is protected by the protective layer 103, preventing the adhesive layer from overflowing to the edge of the wafer 100, which is conducive to preventing the adhesive layer overflowing to the edge of the wafer 100 from affecting the thinning equipment during the subsequent thinning process.

[0067] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure. In actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a wafer, the wafer having opposite first and second surfaces, the edge of the wafer having a stepped surface, the distance between the stepped surface and the second surface being less than the distance between the first surface and the second surface, and the stepped surface and the first surface being connected by a connecting surface to form a step; Forming a protective layer, the protective layer being at least located in the corner area formed by the stepped surface and the connecting surface; Providing a carrier plate and performing a bonding process, in the bonding process step, an adhesive layer is formed between the first surface and the surface of the carrier plate, and the first surface is bonded to the surface of the carrier plate through the adhesive layer; After performing the bonding process, removing the protective layer; Thinning the wafer in the direction from the second surface to the first surface.

2. The method for forming a semiconductor structure according to claim 1, wherein, Forming the protective layer includes: Forming an initial protective layer, the initial protective layer being located on the first surface and in the corner area; Removing the initial protective layer located on the first surface, and the remaining initial protective layer being used as the protective layer.

3. The method for forming a semiconductor structure according to claim 2, wherein, The material of the initial protective layer is photoresist.

4. The method for forming the semiconductor structure according to claim 3, wherein The material of the initial protective layer is negative photoresist, and removing the initial protective layer located on the first surface includes: Exposing the initial protective layer using a mask that covers the first surface and exposes the edge of the wafer; Removing the initial protective layer located on the first surface using an etching solution.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the direction parallel to the first surface, the thickness of the protective layer is 0.4 mm to 3 mm.

6. The method for forming a semiconductor structure as claimed in claim 1, wherein, In the direction from the second surface to the first surface, the distance from the end of the protective layer away from the stepped surface to the second surface is greater than or equal to the distance from the first surface to the second surface.

7. The method for forming a semiconductor structure as described in claim 1, wherein, In the direction from the second surface to the first surface, the thickness of the protective layer is 100 μm to 350 μm.

8. The method for forming the semiconductor structure according to claim 1, wherein, In the direction from the second surface to the first surface, the distance from the end of the protective layer away from the stepped surface to the second surface is less than the distance from the first surface to the second surface, and the distance from the end of the protective layer away from the stepped surface to the second surface is greater than a preset value.

9. The method for forming a semiconductor structure according to claim 8, wherein, The adhesive layer is also located on the connecting surface adjacent to the first surface.

10. The method for forming a semiconductor structure as described in claim 1, wherein, In the direction from the second surface to the first surface, the thickness of the adhesive layer is 20 μm to 80 μm.

11. The method for forming a semiconductor structure according to claim 1, wherein The corner area is provided around the edge of the wafer in a circle, and the protective layer is located in part of the corner area.

12. The method for forming a semiconductor structure according to claim 1, wherein, The corner area is provided around the edge of the wafer in a circle, and the protective layer located in the corner area is provided around the edge of the wafer in a circle.

13. The method for forming the semiconductor structure according to claim 1, wherein Thinning the wafer includes: grinding the second surface in the direction from the second surface to the first surface until the stepped surface is removed.

14. The method for forming a semiconductor structure as described in claim 13, wherein, The wafer has a plurality of conductive structures extending from the first surface to the second surface, and thinning the wafer includes: grinding the second surface, and while removing the stepped surface, also exposing the conductive structures on the second surface.

15. The method for forming a semiconductor structure according to claim 14, wherein In the direction from the first surface to the second surface, the length of the conductive structure is less than or equal to the length of the protective layer.

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