Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, the method comprising: providing a substrate, the substrate having a plurality of discrete mask sidewalls formed on a top portion of the substrate, the substrate comprising an adjacent device region and an isolation region, the isolation region comprising an adjacent first region and a second region, and the first region being between the device region and the second region; removing the mask sidewalls of the first region; after removing the mask sidewalls of the first region, patterning the substrate with the mask sidewalls of the device region and the second region as a mask to form a substrate and a fin standing on the substrate in the device region and the second region; removing the fin of the second region; after removing the fin of the second region, forming an isolation layer on the substrate, the isolation layer covering a portion of sidewalls of the fin of the first device region. By removing the mask sidewalls in the first region close to the device region first, and then removing the fin in the second region away from the device region after forming the substrate and the fin standing on the substrate, the performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, to reduce the impact of short-channel effects, semiconductor processes have gradually transitioned from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. In FinFETs, the gate structure can control the ultrathin body (fin) from at least both sides. Compared with planar MOSFETs, the gate structure has stronger control over the channel and can effectively suppress short-channel effects. Furthermore, FinFETs have better compatibility with existing integrated circuit manufacturing processes compared to other devices.

[0004] In the semiconductor industry, depending on process requirements, it is often necessary to remove parts of the fins (e.g., pseudo-fins). One current approach is to remove these parts using a fin-cutting process. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to further improve the performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a plurality of discrete mask sidewalls are formed on the top of the substrate, the substrate including adjacent device regions and isolation regions, the isolation regions including adjacent first regions and second regions, and the first region being located between the device regions and the second region; removing the mask sidewalls of the first region; after removing the mask sidewalls of the first region, using the mask sidewalls of the device regions and the second region as masks, patterning the substrate to form a substrate and fins protruding from the substrate of the device regions and the second region; removing the fins of the second region; after removing the fins of the second region, forming an isolation layer on the substrate, the isolation layer covering a portion of the sidewalls of the fins of the device regions.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] This invention provides a method for forming a semiconductor structure, comprising: removing mask sidewalls in a first region; after removing the mask sidewalls in the first region, using the mask sidewalls of a device region and a second region as masks, patterning a substrate to form a substrate and fins protruding from the substrates of the device region and the second region; removing the fins in the second region; and after removing the fins in the second region, forming an isolation layer on the substrate, the isolation layer covering part of the sidewalls of the fins in the first device region. Compared with the current approach of forming fins in the device region and the isolation region and then removing the fins in the isolation region, this invention removes the mask sidewalls in the first region close to the device region first, and removes the fins in the second region far from the device region after forming the substrate and the fins protruding from the substrate. Because the mask sidewalls in the first region are removed before patterning the substrate, the distance between the fins in the second region and the fins in the device region increases, thereby reducing the probability of damage to the fins in the device region and the generation of fin residues during the subsequent removal of the fins in the second region, and increasing the efficiency of the process. The process window for removing the fins in the second region is then removed. Simultaneously, removing the fins in the second region after forming them in the device region helps reduce the pattern density difference between the mask sidewalls in the device region and the remaining mask sidewalls in the isolation region, thereby ensuring that the width of the fins formed in the device region meets the process requirements. In summary, this embodiment of the invention splits the fin cutting process into two steps. By first removing the mask sidewalls in the first region close to the device region, and then removing the fins in the second region far from the device region after forming the substrate and the fins protruding from the substrate, the performance of the semiconductor structure can be significantly improved. Attached Figure Description

[0009] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0010] Figures 4 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0011] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure needs further improvement, using a specific semiconductor structure formation method as an example.

[0012] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0013] refer to Figure 1 A substrate 10 is provided, on which a fin mask layer 11 is formed, and on which a plurality of discrete mask sidewalls 12 are formed, the substrate 10 including adjacent device regions 10A and isolation regions 10B.

[0014] refer to Figure 2 Using the mask sidewall 12 as a mask, the fin mask layer 11 is patterned; using the patterned fin mask layer 11 as a mask, the substrate 10 is patterned to form a substrate 16 and a fin 13 protruding from the substrate 16.

[0015] Wherein, after the substrate 16 and the fin portion 13 protruding on the substrate 16 are formed, the remaining portion of the fin mask layer 11 is located on top of the fin portion 13.

[0016] refer to Figure 3 Remove the fin 13 in the isolation area 10B, and the remaining fin 13 is located in the device area 10A.

[0017] The fin 13 in the isolation region 10B is a pseudo-fin. Therefore, by removing the fin 13 in the isolation region 10B, the remaining fin 13 in the device region 10A is used to form a device.

[0018] Research has shown that as the feature size of the device continues to decrease, the spacing between adjacent fins 13 also becomes smaller. Therefore, during the process of removing the fins 13 in the isolation region 10B, the probability of damaging the fins 13 in the device region 10A increases, making the fins 13 formed in the device region 10A unable to meet the process requirements, thereby affecting the performance of the semiconductor structure.

[0019] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a plurality of discrete mask sidewalls are formed on the top of the substrate, the substrate including adjacent device regions and isolation regions, the isolation regions including adjacent first regions and second regions, and the first region being located between the device regions and the second region; removing the mask sidewalls of the first region; after removing the mask sidewalls of the first region, using the mask sidewalls of the device regions and the second region as masks, patterning the substrate to form a substrate and fins protruding from the substrate of the device regions and the second region; removing the fins of the second region; after removing the fins of the second region, forming an isolation layer on the substrate, the isolation layer covering a portion of the sidewalls of the fins of the first device region.

[0020] This invention, in its embodiment, removes the mask sidewalls of a first region; after removing the mask sidewalls of the first region, a substrate is patterned using the mask sidewalls of the device region and the second region as masks to form a substrate and fins protruding from the substrates of the device region and the second region; the fins of the second region are removed; after removing the fins of the second region, an isolation layer is formed on the substrate, the isolation layer covering part of the sidewalls of the fins of the first device region. Compared with the current approach of forming fins in the device region and the isolation region and then removing the fins in the isolation region, this invention, by first removing the mask sidewalls in the first region close to the device region, and then removing the fins in the second region far from the device region after forming the substrate and the fins protruding from the substrate, increases the distance between the fins in the second region and the fins in the device region because the mask sidewalls in the first region are removed before patterning the substrate. This reduces the probability of damage to the fins in the device region and the generation of fin residues during the subsequent removal of the fins in the second region, thus increasing the efficiency of the process. The process window for removing the fins in the second region is then removed. Simultaneously, removing the fins in the second region after forming them in the device region helps reduce the pattern density difference between the mask sidewalls in the device region and the remaining mask sidewalls in the isolation region, thereby ensuring that the width of the fins formed in the device region meets the process requirements. In summary, this embodiment of the invention splits the fin cutting process into two steps. By first removing the mask sidewalls in the first region close to the device region, and then removing the fins in the second region far from the device region after forming the substrate and the fins protruding from the substrate, the performance of the semiconductor structure can be significantly improved.

[0021] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] Figures 4 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0023] refer to Figures 4 to 6 A substrate 100 is provided, on which a plurality of discrete mask sidewalls 103 are formed. The substrate 100 includes adjacent device regions 100A and isolation regions 100B. The isolation region 100B includes adjacent first region a and second region b, and the first region a is located between the device regions 100A and the second region b.

[0024] The substrate is used to provide a process platform for subsequent process manufacturing.

[0025] The substrate 100 includes adjacent device regions 100A and isolation regions 100B. The device region 100A is the working area of ​​a semiconductor device, and the isolation region 100B is used to isolate adjacent semiconductor devices.

[0026] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0027] refer to Figure 4 In this embodiment, before forming a plurality of discrete mask sidewalls 103 on the top of the substrate 100, the method further includes forming a uniformly discrete patterned core layer 102 on the top of the substrate 100, wherein the core layer 102 exposes a portion of the top of the substrate.

[0028] The core layer 102 is used to define the spacing between adjacent fins that are subsequently formed, and also provides a process basis for the subsequent formation of a mask sidewall layer that covers the sidewall of the core layer 102.

[0029] It should be noted that, in order to pattern the substrate 100 subsequently, the core layer 102 needs to be removed first. To facilitate the removal of the core layer 102, an easily removable material is selected. In this embodiment, the material of the core layer 102 includes one or more of amorphous silicon, polycrystalline silicon, silicon oxide, silicon nitride, and silicon oxynitride. As one embodiment, the material of the core layer 102 is amorphous silicon.

[0030] In this embodiment, the step of forming a plurality of discrete mask sidewalls 103 on the top of the substrate 100 includes: forming a mask sidewall material layer (not shown) on the top of the substrate 100, and on the top and sidewalls of the core layer 102; removing the mask sidewall material layer on the top of the substrate 100 and the top of the core layer 102, and using the remaining mask sidewall material layer on the sidewalls of the core layer 102 as the mask sidewall 103.

[0031] The process for forming the mask sidewall material layer includes atomic layer deposition.

[0032] In this embodiment, the material of the mask sidewall 103 includes one or more of silicon nitride, silicon oxide, silicon carbide, silicon nitride carbide, and silicon oxynitride.

[0033] The material of the mask sidewall 103 has a high etching selectivity ratio with the material of the core layer 102, which is beneficial for removing the core layer 103.

[0034] In this embodiment, in the step of providing the substrate 100, the mask sidewall 103 closest to the first region a in the device region 100A serves as the first edge sidewall 300, and the mask sidewall closest to the first region a in the second region b serves as the second edge sidewall 301. The distance D between the first edge sidewall 300 and the second edge sidewall 301 is 100 nanometers to 400 nanometers.

[0035] It should be noted that the distance D between the first edge sidewall 300 and the second edge sidewall 301 should not be too large or too small. If the distance D between the first edge sidewall 300 and the second edge sidewall 301 is too large, during the subsequent etching of the substrate 100 using the first edge sidewall 300 and the second edge sidewall 301 as masks to form fins, the fins formed at the edges of the device region 100A and the second region b are easily affected by the etching loading effect, resulting in a larger fin width at the edges of the device region 100A and the second region b, thus affecting the performance of the semiconductor structure. If the distance D between the first edge sidewall 300 and the second edge sidewall 301 is too small, the process window for removing the fins formed in the second region b becomes smaller. During the subsequent removal of the fins formed in the second region b, the probability of damage to the fins in the device region 100A and the generation of fin residue increases, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the distance D between the first edge sidewall 300 and the second edge sidewall 301 is 100 nanometers to 400 nanometers. For example, the distance D between the first edge sidewall 300 and the second edge sidewall 301 is 60 nanometers, 144 nanometers, or 240 nanometers.

[0036] In this embodiment, the method for forming the semiconductor further includes: forming a fin mask layer 101 on top of the substrate, wherein the fin mask layer 101 is located between the substrate 100 and the core layer 102, and on the substrate 100 where the core layer 102 is exposed.

[0037] It should be noted that the fin mask layer 101 is made of silicon carbide. During the subsequent removal of the fins in the second region b, the fin mask layer 101 can protect the top of the fins in the device region 100A. In other embodiments, the fin mask layer may also be made of silicon nitride.

[0038] refer to Figures 7 to 8 Remove the mask sidewall 103 in the first region a;

[0039] In this embodiment, by first removing the mask sidewall 103 in the first region a near the device region 100A, and then removing the fins in the second region b far from the device region 100A after the substrate and the fins protruding from the substrate are subsequently formed, the distance between the fins in the second region b and the fins in the device region 100A is increased because the mask sidewall 103 in the first region a is removed before the substrate 100 is patterned. This increases the distance between the fins in the second region b and the fins in the device region 100A, thereby reducing the probability of damage to the fins in the device region 100A and the generation of fin residues during the subsequent removal of the fins in the second region b, and increasing the process window for the subsequent removal of the fins in the second region b.

[0040] In this embodiment, the step of removing the mask sidewall 103 of the first region a includes: forming a first mask layer 104 (e.g., a photoresist layer) on top of the substrate 100 of the device region 100A and the second region b, the first mask layer 104 covering the top and sidewalls of the mask sidewall 103 and exposing the mask sidewall 103 of the first region a; and removing the mask sidewall 103 of the first region a using the first mask layer 104 as a mask.

[0041] In this embodiment, the process of removing the mask sidewall 103 of the first region a includes a dry etching process.

[0042] The dry etching process includes anisotropic dry etching. Because of its anisotropic characteristics, the longitudinal etching rate is much higher than the transverse etching rate, thus enabling precise removal of the mask sidewall 103 in the first region a while minimizing damage to other film layers.

[0043] refer to Figure 8 It should be noted that after removing the mask sidewall 103 of the first region a, the process also includes removing the first mask layer 104 in the device region 100A and the second region b.

[0044] Removing the first mask layer 104 from the device region 100A and the second region b provides a process basis for the subsequent patterning of the substrate 100.

[0045] refer to Figure 9 After removing the mask sidewall 103 of the first region a, the substrate 100 is patterned using the mask sidewall 103 of the device region 100A and the second region b as a mask to form a substrate 105 and fins 106 protruding from the substrate 105 of the device region 100A and the second region b.

[0046] In this embodiment, the material of the substrate 100 is silicon, and correspondingly, the substrate 105 is a silicon substrate.

[0047] In this embodiment, the semiconductor structure is a fin field-effect transistor, and the discrete fins 106 on the substrate 105 are used to provide the channel of the fin field-effect transistor.

[0048] Therefore, in this embodiment, the material of the fin 106 is the same as the material of the substrate 105, and the material of the fin 106 is silicon. In other embodiments, the material of the fin can also be a semiconductor material suitable for forming fins, such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, and the material of the fin can also be different from the material of the substrate.

[0049] It should be noted that after the fin 106 and the substrate 105 are formed, the fin mask layer 101 on the top of the fin 106 is retained. The fin mask layer 101 protects the top of the fin 106 in subsequent manufacturing processes.

[0050] It should also be noted that, during the process of forming the substrate 105 and the fins 106 protruding on the substrate 105 of the device region 100A and the second region b, with the direction perpendicular to the extension direction of the fins 106 as the lateral direction, the fins 106 closest to the first region a are easily affected by the etching load effect, resulting in the lateral dimension of the fins 106 closest to the first region a being larger than the lateral dimension of the remaining fins 106 in the device region 100A.

[0051] refer to Figures 10 to 11 In the device region 100A and the second region b, a protective layer 108 is filled between adjacent fins 106, the protective layer 108 covering the top of the substrate 105 and the sidewalls of the fins 106.

[0052] During the subsequent oxidation process of the exposed sidewall of the fin 106 in the first region a, the protective layer 108 protects the sidewall of the fin 106 in the device region 100A and the second region b, reducing the probability of oxidation of the fin 106 in the device region 100A and the second region b, thereby ensuring that the linewidth of the fin 106 in the device region 100A meets the process requirements.

[0053] In this embodiment, the step of filling the protective layer 108 between adjacent fins 106 in the device region 100A and the second region b includes: as follows Figure 10 As shown, a protective material layer 107 is formed on the top of the substrate 105, the top of the fin 106, and the sidewalls, and the protective material layer 107 fills the space between adjacent fins 106 in the device region 100A and the second region b; Figure 11 As shown, the protective material layer 107 on the top of the fin 106 of the device region 100A and the second region b, as well as the protective material layer 107 in the first region a, are removed, and the remaining protective material layer 107 serves as the protective layer 108.

[0054] In this embodiment, the process of forming a protective material layer 107 on the top of the substrate 105, the top of the fin 106, and the sidewall includes an atomic layer deposition process.

[0055] The atomic layer deposition process includes multiple atomic layer deposition cycles, which has good step-fill capability, helps to improve the thickness uniformity of the protective material layer 107, and enables the protective material layer 107 to cover the top and sidewalls of the fin 106. In other embodiments, the protective material layer can also be formed using chemical vapor deposition (CVD).

[0056] In this embodiment, between adjacent fins 106, the protective material layers 107 on the opposite sidewalls of the fins 106 are in contact, thereby filling the space between adjacent fins 106 in the device region 100A and the second region b.

[0057] In this embodiment, in the step of forming a protective material layer 107 on the top of the substrate 105, the top of the fin 106, and the sidewall, with the direction perpendicular to the extension direction of the fin 106 as the lateral direction, the lateral dimension S of the protective material layer 107 formed on the sidewall of the fin 106 closest to the first region a is 5 nanometers to 20 nanometers.

[0058] It should be noted that the lateral dimension of the protective material layer 107 formed on the sidewall of the fin 106 closest to the first region a should not be too large or too small. If the lateral dimension of the protective material layer 107 formed on the sidewall of the fin 106 closest to the first region a is too large, it increases the difficulty of subsequent removal of the protective material layer 107 formed on the sidewall of the fin 106 closest to the first region a; if the lateral dimension of the protective material layer 107 formed on the sidewall of the fin 106 closest to the first region a is too small, in the device region 100A, it is easy to cause a decrease in the protective effect of the protective layer 108 formed on the sidewall of the fin 106 on the fin 106, increasing the probability of damage to the fin 106, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the lateral dimension S of the protective material layer 107 formed on the sidewall of the fin 106 closest to the first region a is 5 nanometers to 20 nanometers.

[0059] Specifically, the protective material layer 107 in the first region a is removed, so that the sidewalls of the fins 106 on both sides of the first region a are exposed, which facilitates the subsequent oxidation treatment of the sidewalls of the fins 106 exposed in the first region a.

[0060] During the subsequent oxidation process of the exposed sidewalls of the fins 106, in order to reduce the oxidation of the fins 106 in the device region 100A and the second region b, the material selected for the protective layer 108 is one or more of silicon oxide, silicon nitride, and silicon oxynitride. As an example, the material of the protective layer 108 filling the spaces between adjacent fins 106 in the device region 100A and the second region b includes silicon oxide.

[0061] refer to Figure 12 After the protective layer 108 is formed, the exposed sidewall of the fin 106 in the first region a is oxidized to form a sacrificial layer 109 for a portion of the width of the sidewall of the fin 106.

[0062] A portion of the width of the sidewall of the fin 106 is oxidized into a sacrificial layer 109, with the direction perpendicular to the extension direction of the fin 106 being the lateral direction, so that the lateral dimensions of the fins 106 in the device region 100A are consistent.

[0063] It should be noted that during the oxidation process of the exposed sidewall of the fin 106, the top surface of the substrate 105 exposed in the first region a will also be oxidized to form a sacrificial layer 109.

[0064] It should be noted that, taking the direction perpendicular to the extension direction of the fin 106 as the lateral direction, the lateral dimension of the sacrificial layer 109 should not be too large or too small. If the lateral dimension of the sacrificial layer 109 is too large, it may easily lead to inconsistent lateral dimensions of the fins 106 in the device region 100A, thus failing to meet the process requirements; if the lateral dimension of the sacrificial layer 109 is too small, it may easily lead to inconsistent lateral dimensions of the fins 106 in the device region 100A, thus failing to meet the process requirements. Therefore, in this embodiment, taking the direction perpendicular to the extension direction of the fin 106 as the lateral direction, the lateral dimension of the sacrificial layer 109 is 5 nanometers to 20 nanometers.

[0065] refer to Figure 13 Remove the protective layer 108 in the device region 100A and the second region b, as well as the sacrificial layer 109 in the first region a.

[0066] To facilitate the subsequent removal of the fin 106 in the second region b, it is necessary to remove the protective layer 108 in the device region 100A and the second region b, as well as the sacrificial layer 109 in the first region a.

[0067] Since the substrate 105 is made of silicon, the sacrificial layer 109 is made of silicon oxide during the oxidation process. As described above, the protective layer 108 is also made of silicon oxide. Therefore, the sacrificial layer 109 and the protective layer 108 are made of the same material, which makes it easier to remove the sacrificial layer 109 and the protective layer 108 in the same step, thereby reducing the number of process steps and saving process costs.

[0068] In this embodiment, the process of removing the protective layer 108 in the device region 100A and the second region b, as well as the sacrificial layer 109 in the first region a, includes a dry etching process.

[0069] The dry etching process includes anisotropic dry etching. Because of its anisotropic nature, the longitudinal etching rate is much higher than the transverse etching rate, thus enabling precise removal of the protective layer 108 and the sacrificial layer 109 while minimizing damage to the sidewalls of the fin 106.

[0070] refer to Figures 14 to 15 Remove the fin 106 from the second region b.

[0071] In this embodiment of the invention, after forming the fin 106 in the device region 100A, the fin 106 in the second region b is then removed. This helps to reduce the difference in pattern density between the mask sidewall 103 in the device region 100A and the remaining mask sidewall 103 in the isolation region 100B, thereby helping to ensure that the width of the fin 106 formed in the device region 100A meets the process requirements.

[0072] In this embodiment, the step of removing the fin 106 in the second region b includes: forming a second mask layer 110 (e.g., a photoresist layer) on the substrate 105 of the device region 100A and the first region a, wherein the second mask layer 110 also covers the fin 106 of the device region 100A; and removing the fin 106 in the second region b using the second mask layer 110 as a mask.

[0073] During the removal of the fin 106 in the second region b, the second mask layer 110, while serving as an etching mask, can also protect the fin 106 in the device region 100A, reducing the probability of damage to the fin 106 in the device region 100A.

[0074] In this embodiment, the process of removing the fin 106 in the second region b includes a dry etching process.

[0075] The dry etching process includes anisotropic dry etching. Because of its anisotropic nature, the longitudinal etching rate is much higher than the transverse etching rate, allowing for precise removal of the fin 106 in the second region b while minimizing damage to other film layers.

[0076] It should be noted that after removing the fin 106 of the second region b, the process further includes removing the second mask layer 110 on the substrate 105 of the device region 100A and the first region a.

[0077] The second mask layer 110 on the substrate 105 of the device region 100A and the first region a is removed to provide space for the subsequent formation of an isolation layer on the substrate 105 exposed by the fin 106.

[0078] refer to Figure 16 After removing the fin 106 in the second region b, an isolation layer 111 is formed on the substrate 105, the isolation layer 111 covering part of the sidewall of the fin 106 in the first device region 100A.

[0079] The isolation layer 111 is used to isolate adjacent devices. The material of the isolation layer 111 can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 111 is silicon oxide.

[0080] In this embodiment, the step of forming the isolation layer 111 includes: forming an isolation material layer (not shown) on the substrate 105 exposed on the fin 106, the isolation material layer also covering the top surface of the fin mask layer 101; planarizing the isolation material layer with the top of the fin mask layer 101 as the stop position; after planarization, etching back a portion of the remaining isolation material layer until a portion of the sidewall of the fin 106 is exposed, the remaining isolation material layer serving as the isolation layer 111.

[0081] In this embodiment, the process for forming the isolation material layer includes fluid chemical vapor deposition.

[0082] The fluid chemical vapor deposition process features good deposition uniformity, high density, and high coverage, making it more suitable for filling gaps with high aspect ratios. In this embodiment, a flowable medium fills the grooves between adjacent fins 106, forming an isolation material layer between adjacent fins 101.

[0083] It should be noted that after the isolation layer 111 is formed on the substrate 105, the process further includes: removing the fin mask layer 101 from the top of the fin 106 in the device region 100A.

[0084] It should also be noted that when removing the fin 106 in the second region b, in order to reduce damage to the substrate 105, a portion of the fin 106 can be retained on the substrate 105 of the second region b. However, the height of the fin 106 remaining in the second region b is relatively small. After the isolation layer 111 is formed, the isolation layer 111 covers the fin 106 remaining in the second region b. Therefore, the impact of the fin 106 remaining in the second region b on the device is still relatively small, and the fin cutting effect is still achieved.

[0085] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, on which a plurality of discrete mask sidewalls are formed. The substrate includes adjacent device regions and isolation regions. The isolation regions include adjacent first regions and second regions, and the first region is located between the device regions and the second region. A fin mask layer is formed on top of the substrate, and the material of the fin mask layer is silicon carbide; Remove the mask sidewalls in the first region; After removing the mask sidewalls of the first region, the substrate is patterned using the mask sidewalls of the device region and the second region as a mask to form a substrate and fins protruding from the substrate of the device region and the second region. After forming the substrate and the fins protruding from the substrate in the device region and the second region, and before removing the fins in the second region, the method further includes: filling a protective layer between adjacent fins in the device region and the second region, the protective layer covering the top of the substrate and the sidewalls of the fins; after forming the protective layer, oxidizing the exposed sidewalls of the fins in the first region to oxidize a portion of the width of the sidewalls of the fins into a sacrificial layer; Remove the fin from the second region; After removing the fin in the second region, an isolation layer is formed on the substrate, the isolation layer covering a portion of the sidewall of the fin in the device region; Before forming a plurality of discrete mask sidewalls on the top of the substrate, the method further includes: forming a fin mask layer on the top of the substrate; forming a uniformly discrete patterned core layer on the top of the fin mask layer, the core layer exposing a portion of the top of the fin mask layer; the mask sidewalls being located on the sidewalls of the core layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of removing the mask sidewall of the first region includes: forming a first mask layer on top of the substrate of the device region and the second region, the first mask layer covering the top and sidewalls of the mask sidewall and exposing the mask sidewall of the first region; removing the mask sidewall of the first region using the first mask layer as a mask; and removing the first mask layer.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of filling a protective layer between adjacent fins in the device region and the second region includes: forming a protective material layer on the top of the substrate, the top of the fin, and the sidewall, and the protective material layer filling the space between adjacent fins in the device region and the second region; removing the protective material layer on the top of the fins in the device region and the second region, as well as the protective material layer in the first region, and the remaining protective material layer serving as the protective layer.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of removing the fin in the second region includes: forming a second mask layer on the substrate of the device region and the first region, the second mask layer further covering the fin in the device region; removing the fin in the second region using the second mask layer as a mask; and removing the second mask layer.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, After oxidizing the sidewalls of the fin portion of its width into a sacrificial layer, and before removing the fin portion in the second region, the process further includes: removing the protective layer in the device region and the second region, as well as the sacrificial layer in the first region.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The protective layer and the sacrificial layer are made of the same material; in the same step, the protective layer and the sacrificial layer are removed.

7. The method for forming a semiconductor structure as described in claim 5 or 6, characterized in that, The process for removing the protective layer in the device region and the second region, as well as the sacrificial layer in the first region, includes a dry etching process.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, With the direction perpendicular to the extension direction of the fin as the lateral direction, the lateral dimension of the sacrificial layer is 5 nanometers to 20 nanometers.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, the mask sidewall closest to the first region in the device region serves as the first edge sidewall, and the mask sidewall closest to the first region in the second region serves as the second edge sidewall. The distance between the first edge sidewall and the second edge sidewall is 100 nanometers to 400 nanometers.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for removing the mask sidewalls in the first region includes a dry etching process.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for removing the fin in the second region includes a dry etching process.

12. The method for forming a semiconductor structure as described in claim 3, characterized in that, The process of forming a protective material layer on the top of the substrate, the top of the fin, and the sidewalls includes an atomic layer deposition process.

13. The method for forming a semiconductor structure as described in claim 3, characterized in that, In the step of forming a protective material layer on the top of the substrate, the top of the fin, and the sidewall, with the direction perpendicular to the extension direction of the fin as the lateral direction, the lateral dimension of the protective material layer formed on the sidewall of the fin closest to the first region is 5 nanometers to 20 nanometers.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the mask sidewall, the material of the mask sidewall includes one or more of silicon nitride, silicon oxide, silicon carbide, silicon nitride carbide, and silicon oxynitride.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the device region and the second region, the material of the protective layer filling between adjacent fins includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

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