Methods for forming semiconductor structures

Abstract

A method for forming a semiconductor structure includes: providing a substrate including a first device region and a second device region; forming a first channel structure on the substrate of the first device region, including one or more stacked first channel layers, including a first sacrificial layer and a first channel layer located on the first sacrificial layer, the first channel structure having a first width, and the first sacrificial layer being made of a germanium-containing material; forming a second channel structure on the substrate of the second device region, including one or more stacked second channel layers, including a second sacrificial layer and a second channel layer located on the second sacrificial layer, the second channel structure having a second width greater than the first width, wherein the second sacrificial layer is made of a germanium-containing material, and the atomic percentage of germanium in the second sacrificial layer is greater than the atomic percentage of germanium in the first sacrificial layer; removing the first sacrificial layer and the second sacrificial layer; and forming a gate structure. This invention makes the removal times of the first sacrificial layer and the second sacrificial layer approximately the same.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, to better adapt to the requirements of proportionally shrinking device dimensions, semiconductor technology has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors. In a gate-all-around transistor, the gate surrounds the area where the channel is located from all sides. Compared with planar transistors, the gate of a gate-all-around transistor has stronger control over the channel and can better suppress short-channel effects. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a method for forming a semiconductor structure, thereby improving the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate including a first device region for forming a first device and a second device region for forming a second device, wherein the channel width of the first device is smaller than the channel width of the second device; forming a first channel structure on the substrate of the first device region, the first channel structure including one or more stacked first channel layers, the first channel layer including a first sacrificial layer and a first channel layer located on the first sacrificial layer, the first channel structure including a first channel region along the extension direction of the first channel structure, the first channel structure having a first width along a direction perpendicular to the extension direction of the first channel structure, and the material of the first sacrificial layer being a germanium-containing material; and forming a second channel structure on the substrate of the second device region, the second channel structure including one or more stacked second channel regions. A channel stack, the second channel stack including a second sacrificial layer and a second channel layer located on the second sacrificial layer, the second channel structure including a second channel region along the extension direction of the second channel structure, the second channel structure having a second width in a direction perpendicular to the extension direction of the second channel structure, the second width being greater than a first width, wherein the material of the second sacrificial layer is a germanium-containing material, and the atomic percentage of germanium in the second sacrificial layer is greater than the atomic percentage of germanium in the first sacrificial layer; removing the first sacrificial layer of the first channel region and the second sacrificial layer of the second channel region; after removing the first sacrificial layer of the first channel region and the second sacrificial layer of the second channel region, forming a gate structure in the first channel region and the second channel region, the gate structure including a gate dielectric layer surrounding and covering the first channel layer and the second channel layer, and a gate electrode layer located on the gate dielectric layer.

[0006] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0007] In the formation method provided by this embodiment of the invention, the first channel structure has a first width along a direction perpendicular to the extension direction of the first channel structure, and the second channel structure has a second width along a direction perpendicular to the extension direction of the second channel structure. The second width is greater than the first width. The atomic percentage of germanium in the second sacrificial layer is greater than the atomic percentage of germanium in the first sacrificial layer. The channel width of the first device is smaller than the channel width of the second device; that is, the channel width of the first channel structure is smaller than the channel width of the second channel structure, and the width of the first sacrificial layer is smaller than the width of the second sacrificial layer. Therefore, the width dimension of the first sacrificial layer is smaller, and the width dimension of the second sacrificial layer is larger. Thus, when removing the first sacrificial layer... In the process of removing the first sacrificial layer and the second sacrificial layer, when only the width dimension is considered, the time to remove the first sacrificial layer is shorter, while the time to remove the second sacrificial layer is longer. In this embodiment of the invention, the atomic percentage of germanium in the second sacrificial layer is greater than that in the first sacrificial layer. The higher the atomic percentage of germanium, the faster the material is removed, which increases the removal rate of the second sacrificial layer. This helps to reduce the impact of the width difference between the first and second channel structures on the removal time of the first and second sacrificial layers, making the removal time of the first and second sacrificial layers tend to be the same. This, in turn, helps to reduce damage to the first channel layer while completely removing the first and second sacrificial layers, and correspondingly helps to improve the performance of the semiconductor structure. Attached Figure Description

[0008] Figures 1 to 2 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0009] Figures 3 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0010] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure needs further improvement, using a specific semiconductor structure formation method as an example.

[0011] Figures 1 to 2 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] refer to Figure 1A substrate 10 is provided, the substrate 10 including a first device region 10A for forming a first device and a second device region 10B for forming a second device, the channel width of the first device being smaller than the channel width of the second device. A first channel structure 30 is formed on the substrate 10 of the first device region 10A, the first channel structure 30 including one or more stacked first channel stacks 31, the first channel stack 31 including a first sacrificial layer 32 and a first channel layer 33 located on the first sacrificial layer 32. A second channel structure 40 is formed on the substrate 10 of the second device region 10B, the second channel structure 40 including one or more stacked second channel stacks 41, the second channel stack 41 including a second sacrificial layer 42 and a second channel layer 43 located on the second sacrificial layer 42.

[0013] The channel width of the first device is smaller than the channel width of the second device, that is, the width w1 of the first channel structure 30 is smaller than the width w2 of the second channel structure 40.

[0014] refer to Figure 2 Remove the first sacrificial layer 32 and the second sacrificial layer 33 to expose the surfaces of the first trench layer 33 and the second trench layer 43.

[0015] The first sacrificial layer 32 and the second sacrificial layer 33 are removed, exposing each surface of the first channel layer 33 and the second channel layer 43. Subsequently, after a gate structure is formed between the first channel layer 33 and the second channel layer 43, the gate structure can surround and cover each surface of the first channel layer 33 and the second channel layer 43.

[0016] Since the width w1 of the first channel structure 30 is smaller than the width w2 of the second channel structure 40, that is, the width of the first sacrificial layer 32 is smaller than the width of the second sacrificial layer 42, when only the width dimension is considered, the time to remove the first sacrificial layer 32 is shorter and the time to remove the second sacrificial layer 42 is longer during the removal of the first sacrificial layer 32 and the second sacrificial layer 33. It is difficult to balance the time to remove the first sacrificial layer 32 and the second sacrificial layer 33. When the first sacrificial layer 32 is completely removed, the second sacrificial layer 42 still remains. If the second sacrificial layer 42 is continued to be completely removed, the first channel layer 33 is easily over-etched, which will damage the first channel layer 33. This will result in a large deviation between the performance of the final device and the expected design, and thus affect the performance of the semiconductor structure.

[0017] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate including a first device region for forming a first device and a second device region for forming a second device, wherein the channel width of the first device is smaller than the channel width of the second device; forming a first channel structure on the substrate of the first device region, the first channel structure including one or more stacked first channel layers, the first channel layer including a first sacrificial layer and a first channel layer located on the first sacrificial layer, the first channel structure including a first channel region along the extension direction of the first channel structure, the first channel structure having a first width along a direction perpendicular to the extension direction of the first channel structure, and the material of the first sacrificial layer being a germanium-containing material; and forming a second channel structure on the substrate of the second device region, the second channel structure including one or more A second channel stack, comprising a second sacrificial layer and a second channel layer on the second sacrificial layer, wherein the second channel structure includes a second channel region along the extension direction of the second channel structure, and the second channel structure has a second width in a direction perpendicular to the extension direction of the second channel structure, the second width being greater than the first width, wherein the material of the second sacrificial layer is a germanium-containing material, and the atomic percentage of germanium in the second sacrificial layer is greater than the atomic percentage of germanium in the first sacrificial layer; removing the first sacrificial layer of the first channel region and the second sacrificial layer of the second channel region; after removing the first sacrificial layer of the first channel region and the second sacrificial layer of the second channel region, forming a gate structure in the first channel region and the second channel region, the gate structure comprising a gate dielectric layer surrounding and covering the channel layer, and a gate electrode layer on the gate dielectric layer.

[0018] The channel width of the first device is smaller than the channel width of the second device. That is, the channel width of the first channel structure is smaller than the channel width of the second channel structure. The width of the first sacrificial layer is smaller than the width of the second sacrificial layer. Therefore, when only the width dimension is considered, the removal time of the first sacrificial layer is shorter and the removal time of the second sacrificial layer is longer during the removal of the first and second sacrificial layers. In this embodiment of the invention, the atomic percentage of germanium in the second sacrificial layer is greater than that in the first sacrificial layer. The higher the atomic percentage of germanium, the faster the material is removed, which increases the removal rate of the second sacrificial layer. This helps to reduce the impact of the width difference between the first and second channel structures on the removal time of the first and second sacrificial layers, making the removal time of the first and second sacrificial layers tend to be the same. This helps to reduce the damage to the first channel layer while completely removing the first and second sacrificial layers, and correspondingly improves the performance of the semiconductor structure.

[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0020] Figures 3 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0021] refer to Figure 3 A substrate 100 is provided, including a first device region 100A for forming a first device and a second device region 100B for forming a second device, wherein the channel width of the first device is smaller than the channel width of the second device.

[0022] The substrate 100 provides the basis for the process operation of forming the semiconductor structure. The semiconductor structure includes gate-all-around (GAA) transistors and forksheet transistors.

[0023] The substrate 100 includes a substrate (not shown).

[0024] In this embodiment, the substrate material is silicon. In other embodiments, the substrate material can also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material can be a material suitable for process requirements or easy to integrate.

[0025] It should be noted that the substrate 100 may also include: fins (not shown) located on the substrate.

[0026] In this embodiment, the substrate 100 further includes an isolation layer (not shown) located in the substrate 100. The isolation layer is used to achieve insulation between different devices. For example, in CMOS manufacturing processes, an isolation layer is usually formed between NMOS transistors and PMOS transistors.

[0027] In this embodiment, the isolation layer is located on the substrate and covers the sidewalls of the fin.

[0028] In this embodiment, taking the semiconductor structure as a fully enclosed gate transistor as an example, the substrate 100 includes a first device region 100A for forming a first device and a second device region 100B for forming a second device, wherein the channel width of the first device is smaller than the channel width of the second device.

[0029] Reference Figures 3 to 10 A first channel structure 300 is formed on the substrate 100 of the first device region 100A. The first channel structure 300 includes one or more stacked first channel layers 310. The first channel layer 310 includes a first sacrificial layer 320 and a first channel layer 330 located on the first sacrificial layer 320. Along the extension direction of the first channel structure 300, the first channel structure 300 includes a first channel region 300c (e.g., ...). Figure 6 As shown), along a direction perpendicular to the extending direction of the first channel structure 300, the first channel structure 300 has a first width w1 (as shown). Figure 5 (as shown), and the material of the first sacrificial layer 320 is a germanium-containing material; a second channel structure 400 is formed on the substrate 100 of the second device region 100B, the second channel structure 400 including one or more stacked second channel layers 410, the second channel layer 410 including a second sacrificial layer 420 and a second channel layer 430 located on the second sacrificial layer 420, and along the extension direction of the second channel structure 400, the second channel structure 400 includes a second channel region 410c (as shown). Figure 10 As shown in Figure 9, the second channel structure 400 has a second width w2 in a direction perpendicular to the extension direction of the second channel structure 400. The second width w2 is greater than the first width w1. The material of the second sacrificial layer 420 is a germanium-containing material, and the atomic percentage of germanium in the second sacrificial layer 420 is greater than the atomic percentage of germanium in the first sacrificial layer 320.

[0030] The channel width of the first device is smaller than the channel width of the second device. That is, the channel width of the first channel structure 300 is smaller than the channel width of the second channel structure 400. The width of the first sacrificial layer 320 is smaller than the width of the second sacrificial layer 420. Therefore, the width of the first sacrificial layer 320 is smaller, and the width of the second sacrificial layer 420 is larger. Consequently, when only considering the influence of width, removing the first sacrificial layer 320 takes less time, while removing the second sacrificial layer 420 takes longer. In this embodiment of the invention, the atomic percentage of germanium in the second sacrificial layer 420 is greater than that in the first sacrificial layer 320. The higher the atomic percentage of germanium, the faster the material is removed, which increases the removal rate of the second sacrificial layer 420. This helps to reduce the impact of the width difference between the first channel structure 300 and the second channel structure 400 on the removal time of the first sacrificial layer 320 and the second sacrificial layer 420, making the removal time of the first sacrificial layer 320 and the second sacrificial layer 420 tend to be the same. This helps to reduce damage to the first channel layer 330 while completely removing the first sacrificial layer 320 and the second sacrificial layer 420, and correspondingly improves the performance of the semiconductor structure.

[0031] The first channel layer 330 in the first channel structure 300 and the second channel layer 430 in the second channel structure 400 are used to provide channels for transistors. The first sacrificial layer 320 and the second sacrificial layer 420 are used to provide a process basis for the subsequent floating arrangement of the first channel layer 330 and the second channel layer 430, and also to occupy space for the gate structure to be formed later. In subsequent processes, the first sacrificial layer 320 and the second sacrificial layer 420 are removed, leaving the first channel layer 330 and the second channel layer 430 floating. Subsequently, a gate structure is formed between the first channel layer 330 and the substrate 100, between the second channel layer 430 and the substrate 100, between adjacent first channel layers 330, and between adjacent second channel layers 430, so that the gate structure surrounds and covers the first channel layer 330 and the second channel layer 430.

[0032] The top and sidewalls of the first channel layer 330 and the second channel layer 430, which are covered by the gate structure, are used as channels. In this embodiment, the top, bottom and sidewalls of the first channel layer 330 and the second channel layer 430 can all be used as channels, which increases the area of ​​the first channel layer 330 and the second channel layer 430 used as channels, thereby increasing the operating current of the semiconductor structure.

[0033] Reference Figure 6 , Figure 6This is a top view of any first channel structure 300. Along the extending direction of the first channel structure 300, the first channel structure 300 includes a first channel region 300c, and a first channel layer 330 of the first channel region 300c is used as a channel for the first device.

[0034] Reference Figure 10 , Figure 10 This is a top view of any of the second channel structures 400. Along the extending direction of the second channel structure 400, the second channel structure 400 includes a second channel region 400c. The second channel layer 430 of the second channel region 400c is used as a channel for a transistor.

[0035] In this embodiment, the material of the first channel layer 330 includes silicon, germanium, or a group III-V semiconductor material, and the material of the second channel layer 430 includes silicon, germanium, or a group III-V semiconductor material. As an example, the material of the first channel layer 330 is silicon, and the material of the second channel layer 430 is silicon. In other embodiments, the materials of the first channel layer and the second channel layer are determined according to the type and performance of the first device and the second device, respectively.

[0036] It should be noted that in this embodiment, the first channel layer 330 and the second channel layer 430 are made of the same material as the substrate 100. In other embodiments, the first channel layer and the second channel layer may be made of different materials than the substrate.

[0037] In this embodiment, the second sacrificial layer 420 and the first sacrificial layer 320 have the same thickness.

[0038] In this embodiment, the atomic percentage of germanium in the second sacrificial layer 420 and the first sacrificial layer 320 is adjusted to regulate the time required to remove the second sacrificial layer 420 and the first sacrificial layer 320. The thickness is also a variable that affects the time required to remove the second sacrificial layer 420 and the first sacrificial layer 320. Therefore, by making the thickness of the second sacrificial layer 420 and the first sacrificial layer 320 the same, when removing the first sacrificial layer 320 and the second sacrificial layer 420, only the influence of the width dimension and the atomic percentage of germanium needs to be considered, which makes it easier to make the time required to remove the first sacrificial layer 320 and the second sacrificial layer 420 tend to be the same.

[0039] It should be noted that, in this embodiment, the atomic percentage of germanium in the first sacrificial layer 320 and the atomic percentage of germanium in the second sacrificial layer 420 need to be reasonably adjusted according to the width difference between the first channel structure 300 and the second channel structure 400, and they need to work together to achieve a balance between etching rate and etching time, so that the time to remove the first sacrificial layer 320 and the second sacrificial layer 420 tends to be the same.

[0040] In this embodiment, the material of the first sacrificial layer 320 includes silicon germanide; the material of the second sacrificial layer 420 includes silicon germanide.

[0041] In this embodiment, the first channel layer 330 and the second channel layer 430 are made of silicon. Therefore, the first sacrificial layer 320 and the second sacrificial layer 420 are both made of silicon germanide.

[0042] The silicon germanide and silicon can form a large etching selectivity, which is beneficial for the subsequent removal of the first sacrificial layer 320 and the second sacrificial layer 420, and reduces damage to the first channel layer 330 and the second channel layer 430.

[0043] Moreover, since the first sacrificial layer 320 and the second sacrificial layer 420 are made of the same material, only the atomic percentage of germanium in the first sacrificial layer 320 and the second sacrificial layer 420 needs to be adjusted. This reduces the variables that affect the time required to remove the first sacrificial layer 320 and the second sacrificial layer 420. It is easy to make the time to remove the first sacrificial layer 320 and the second sacrificial layer 420 similar by simply adjusting the atomic percentage of germanium, thus reducing the complexity of the process.

[0044] In other embodiments, a material with an etch selectivity ratio suitable for the first and second trench layers can be selected based on the materials of the first and second trench layers, so as to reduce damage to the first and second trench layers when removing them subsequently.

[0045] The following is for reference only. Figures 3 to 9 The steps for forming the first channel structure 300 and the second channel structure 400 are described in detail.

[0046] Reference Figure 3 and Figure 4 A first mask layer 200 is formed on the substrate 100 of the second device region 100B. The first mask layer 200 also covers a portion of the substrate 100 at the junction of the first device region 100A and the second device region 100B.

[0047] Subsequently, a first material layer is formed on the substrate 100 exposed by the first mask layer 200. When the first mask layer 200 is located in the second device region 100B, the first material layer is the first channel structure 300. When the first mask layer 200 is located in the first device region 100A, the first material layer is the second channel structure 400. The first mask layer 200 serves as a mask for the subsequent formation of the first material layer.

[0048] In this embodiment, taking the first material layer as the first channel structure 300 as an example, the first mask layer 200 allows the first channel structure 300 to grow longitudinally. Furthermore, compared to the scheme of first forming the first channel structure on the substrate of the first device region and the second device region, and then removing the first channel structure located in the second device region, this scheme eliminates the need for etching to form the first channel structure 300, resulting in higher sidewall quality of the formed first channel structure 300. Simultaneously, the first mask layer 200 exposes the substrate 100 of the first device region 100A or the second device region 100B, preparing for the subsequent formation of the second material layer. Wherein, when the first material layer is the first channel structure 300, the second material layer is the second channel structure 400; when the first material layer is the second channel structure 400, the second material layer is the first channel structure 300.

[0049] In this embodiment, the material of the first mask layer 200 includes a dielectric material, which includes one or both of silicon oxide and silicon nitride.

[0050] The first mask layer 200 also needs to isolate the first material layer and the subsequently formed second material layer. Therefore, the material of the first mask layer 200 includes dielectric material. At the same time, the silicon oxide and silicon nitride have good isolation effect.

[0051] Specifically, refer to Figure 3 The step of forming the first mask layer 200 includes: forming a mask material layer 110 on the substrate 100, the mask material layer 110 covering the substrate 100 of the first device region 100A and the second device region 100B.

[0052] The mask material layer 110 is used to form the first mask layer 200. In this embodiment, the material of the mask material layer 110 includes a dielectric material, which includes one or both of silicon oxide and silicon nitride, and is used to directly form the first mask layer 200.

[0053] refer to Figure 4 A portion of the mask material layer 110 of the first device region 100A is removed, while the mask material layer 110 located in the second device region 100B and a portion of the mask material layer 110 at the junction of the second device region 100B and the first device region 100A are retained, forming a first mask layer 200 that exposes the substrate 100 of the first device region 100A.

[0054] refer to Figure 5 A first material layer (not shown) is formed on the substrate 100 exposed by the first mask layer 200, and the first material layer is the first channel structure 300.

[0055] In this embodiment, the first channel structure 300 is formed by epitaxial growth process.

[0056] The epitaxial growth process allows for better control of process parameters, resulting in high process controllability and easy acquisition of precise film thickness dimensions. Furthermore, the epitaxial growth process facilitates the formation of films with fewer impurities, leading to higher quality of the first channel structure 300.

[0057] Furthermore, by selecting an epitaxial process, it is beneficial to improve the uniformity of the atomic percentage of germanium in the first sacrificial layer 320, thereby improving the uniformity of the etching rate of the first sacrificial layer 320, so that the removal time of the first sacrificial layer 320 and the second sacrificial layer 420 tends to be the same.

[0058] refer to Figure 7 A second mask layer 210 is formed covering the first material layer and the first mask layer 200.

[0059] The second mask layer 210 is used to protect the top of the first material layer.

[0060] In this embodiment, the material of the second mask layer 210 includes a dielectric material, which includes one or both of silicon oxide and silicon nitride.

[0061] The second mask layer 210 is also used to enhance the isolation effect of the first channel structure 300 and the second channel structure 400. Therefore, the material of the second mask layer 210 includes a dielectric material, and the silicon oxide has a good isolation effect.

[0062] In this embodiment, the second mask layer 210 is made of the same material as the first mask layer 200, which helps to simplify the subsequent process of removing the first mask layer 210 and the second mask layer 210 and save process costs.

[0063] refer to Figure 8 Remove a portion of the second mask layer 210 on the side of the first material layer, and retain the remaining second mask layer 210 located at the junction of the second device region 100B and the first device region 100A, and covering the top of the first material layer.

[0064] After removing a portion of the second mask layer 210 on the side of the first material layer, the remaining second mask layer 210 serves as an isolation structure between the first material layer and the subsequently formed second material layer. The remaining second mask layer 210 also protects the top of the first material layer, reduces contamination of the first material layer during the subsequent formation of the second material layer, and prevents subsequent epitaxial growth on the first material layer. Furthermore, the remaining second mask layer 210 exposes the first mask layer 200 on the substrate 100 of the second device region 100B or the first device region 100A, preparing for the formation of the second material layer.

[0065] Continue to refer to Figure 8 Remove the first mask layer 200 exposed by the remaining second mask layer 210, and retain the remaining first mask layer 200 located at the junction of the second device region 100B and the first device region 100A.

[0066] Remove the remaining second mask layer 210 to expose the first mask layer 200, exposing the substrate 100 of the second device region 100B in preparation for the formation of the second material layer. Meanwhile, retain the remaining first mask layer 200 located at the junction of the second device region 100B and the first device region 100A to isolate the first material layer from the subsequently formed second material layer.

[0067] refer to Figure 9 A second material layer (not shown) is formed on the remaining substrate 100 exposed by the remaining first mask layer 200. The second material layer is a second channel structure 400.

[0068] In this embodiment, by forming a first mask layer 200 and a second mask layer 210, only epitaxial processes are used in the formation of the first channel structure 300 and the second channel structure 400, without additional etching steps, which helps to improve the quality of the first channel structure 300 and the second channel structure 400. Furthermore, the first mask layer 200 blocks the lateral growth of the first channel structure 300 and the second channel structure 400, allowing the first channel structure 300 and the second channel structure 400 to grow longitudinally, thus exhibiting better directionality.

[0069] In this embodiment, the second channel structure 400 is formed by epitaxial growth process.

[0070] The epitaxial growth process allows for better control of process parameters, resulting in high process controllability and easy acquisition of precise film thickness dimensions. Furthermore, the epitaxial growth process facilitates the formation of films with fewer impurities, leading to higher quality of the second channel structure 400.

[0071] Furthermore, by selecting an epitaxial process, it is beneficial to improve the uniformity of the atomic percentage of germanium in the second sacrificial layer 420, thereby improving the uniformity of the etching rate of the second sacrificial layer 420, so that the removal time of the first sacrificial layer 320 and the second sacrificial layer 420 tends to be the same.

[0072] In this embodiment, the formation of the first channel structure 300 followed by the formation of the second channel structure 400 is taken as an example. In other embodiments, the second channel structure may be formed first, followed by the formation of the first channel structure. Correspondingly, a first mask layer is formed on the substrate of the first device region; the first material layer is the second channel structure, and the second material layer is the first channel structure.

[0073] Accordingly, in the step of forming the first mask layer, a portion of the mask material layer of the second device region is removed, while the mask material layer located in the first device region and a portion of the mask material layer at the junction of the second device region and the first device region are retained, thereby forming a first mask layer that exposes the substrate of the second device region.

[0074] refer to Figure 11 After forming the first channel structure 300 and the second channel structure 400, the method further includes: removing the remaining second mask layer 210 and the remaining first mask layer 200 located at the junction of the second device region 100B and the first device region 100A.

[0075] The remaining second mask layer 210 and the remaining first mask layer 200 located at the junction of the second device region 100B and the first device region 100A are removed to provide space for the subsequent formation of the gate structure.

[0076] In this embodiment, the remaining second mask layer 210 and the remaining first mask layer 200 located at the junction of the second device region 100B and the first device region 100A are removed in the same step, simplifying the process flow and saving process costs. Moreover, in this embodiment, the second mask layer 210 and the first mask layer 200 are made of the same material, which is beneficial to remove the remaining second mask layer 210 and the remaining first mask layer 200 located at the junction of the second device region 100B and the first device region 100A together.

[0077] In this embodiment, a wet etching process is used to remove the remaining second mask layer 210 and the remaining first mask layer 200 located at the junction of the second device region 100B and the first device region 100A.

[0078] The wet etching process has the characteristic of isotropic etching, which is beneficial to completely remove the second mask layer 210 and the first mask layer 200. In addition, the wet etching process can have good etching selectivity, thus reducing the damage to the first channel structure 300 and the second channel structure 400 during the removal of the second mask layer 210 and the first mask layer 200.

[0079] refer to Figure 12 After the formation of the first channel structure 300 and the second channel structure 400, and before the subsequent removal of the first sacrificial layer 320 of the first channel region 300c and the second sacrificial layer 420 of the second channel region 400c, the method further includes: forming a pseudo-gate structure 500 on the substrate 100 that spans the first channel structure 300 and the second channel structure 400, wherein the pseudo-gate structure 500 covers the top and sidewalls of the first channel structure 300 in the first channel region 300c and the top and sidewalls of the second channel structure 400 in the second channel region 400c.

[0080] The pseudo-gate structure 500 is used to occupy space for the subsequent formation of the gate structure.

[0081] Specifically, the pseudo-gate structure 500 is a stacked structure, including a pseudo-gate oxide layer (not shown) and a pseudo-gate layer (not shown) covering the pseudo-gate oxide layer.

[0082] The dummy gate layer can be a single-layer structure or a stacked structure, and the material of the dummy gate layer includes one or both of amorphous silicon and polycrystalline silicon. In other embodiments, the material of the dummy gate layer may also include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon nitride, silicon carbonitride, and amorphous carbon.

[0083] In this embodiment, the dummy gate layer is a single-layer structure, and the material of the dummy gate layer is amorphous silicon. Amorphous silicon does not have a crystal orientation; therefore, the etching rate and etching effect of amorphous silicon are more uniform, thereby improving the subsequent removal effect of the dummy gate layer.

[0084] As an example, the material of the pseudo-gate oxide layer is silicon oxide.

[0085] In this embodiment, after the pseudo-gate structure 500 is formed and before the interlayer dielectric layer is subsequently formed, the method further includes: removing the first channel structure 300 on both sides of the pseudo-gate structure 500 in the first device region 100A and the second channel structure 400 on both sides of the pseudo-gate structure 500 in the second device region 100B to form source / drain grooves (not shown).

[0086] The source / drain grooves provide space for the subsequent formation of source / drain doped layers.

[0087] In this embodiment, a source / drain doped layer (not shown) is formed in the source / drain groove, and the source / drain doped layer is in contact with the first channel layer 320 and the second channel layer 420 below the pseudo-gate structure 500.

[0088] The source / drain doped layers serve as the source or drain regions of the formed transistor. Specifically, the doping type of the source / drain doped layers is the same as the channel conductivity type of the corresponding transistor.

[0089] In this embodiment, after the pseudo-gate structure 500 is formed, an interlayer dielectric layer 120 is formed on the substrate 100 on the side of the pseudo-gate structure 500. The interlayer dielectric layer 120 also covers the sidewall of the pseudo-gate structure 500 and exposes the top of the pseudo-gate structure 500.

[0090] The interlayer dielectric layer 120 serves to isolate adjacent devices and also provides a process basis for the subsequent removal of the dummy gate structure 500 to form a gate opening.

[0091] The material of the interlayer dielectric layer 120 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0092] In this embodiment, the dummy gate structure 500 is removed, and a gate opening (not shown) is formed in the interlayer dielectric layer 120. The gate opening exposes the first channel structure 300 of the first channel region 300c and the second channel structure 400 of the second channel region 400c.

[0093] The gate opening provides space for the subsequent formation of the gate structure, and the gate opening exposes the first channel structure 300 of the first channel region 300c and the second channel structure 400 of the second channel region 400c, in preparation for the subsequent removal of the first sacrificial layer 320 and the second sacrificial layer 420.

[0094] refer to Figure 13 Remove the first sacrificial layer 320 of the first channel region 300c and the second sacrificial layer 420 of the second channel region 400c.

[0095] The first sacrificial layer 320 of the first channel region 300c and the second sacrificial layer 420 of the second channel region 400c are removed to achieve the floating arrangement of the first channel layer 330 and the second channel layer 430, which also provides space for the subsequent formation of the gate structure.

[0096] In this embodiment, the first sacrificial layer 320 of the first channel region 300c and the second sacrificial layer 420 of the second channel region 400c are removed through the gate opening.

[0097] In this embodiment, the first sacrificial layer 320 and the second sacrificial layer 420 are removed in the same process, which simplifies the process flow and improves process efficiency.

[0098] In this embodiment, an isotropic etching process is used to remove the first sacrificial layer 320 and the second sacrificial layer 420.

[0099] The isotropic etching process facilitates the complete removal of the first sacrificial layer 320 and the second sacrificial layer 420.

[0100] In this embodiment, the isotropic etching process includes the Certas etching process or the SiCoNi etching process.

[0101] The Certas etching process or SiCoNi etching process has good isotropic characteristics, which is beneficial for removing the first sacrificial layer 320 and the second sacrificial layer 420 cleanly. In addition, the Certas etching process or SiCoNi etching process has a good etching selectivity ratio for the first sacrificial layer 320 and the second sacrificial layer 420 and the first channel layer 330 and the second channel layer 430.

[0102] In this embodiment, the isotropic etching process is the Certas etching process, and the etching gas in the Certas etching process includes HF gas.

[0103] In other embodiments, a wet etching process can also be used to remove the first and second sacrificial layers.

[0104] In this embodiment, since the atomic percentage of germanium in the second sacrificial layer 420 is greater than that in the first sacrificial layer 320, it is beneficial to remove the second sacrificial layer 420 and the first sacrificial layer 320 at the same time.

[0105] refer to Figure 14 After removing the first sacrificial layer 320 of the first channel region 300c and the second sacrificial layer 420 of the second channel region 400c, a gate structure 600 is formed in the first channel region 300c and the second channel region 400c. The gate structure 600 includes a gate dielectric layer 610 surrounding and covering the first channel layer 320 and the second channel layer 420, and a gate electrode layer 620 located on the gate dielectric layer 610.

[0106] In this embodiment, in the step of forming the gate structure 600, the gate structure 600 includes a gate dielectric layer 610 surrounding and covering the first channel layer 320 and the second channel layer 420, so that the gate structure 600 surrounds and covers the first channel layer 320 and the second channel layer 420.

[0107] The gate structure 600 surrounds and covers the first channel layer 320 and the second channel layer 420. Therefore, the top, bottom and sidewalls of the first channel layer 320 and the second channel layer 420 can all serve as channels, increasing the area of ​​the first channel layer 320 and the second channel layer 420 used as channels, thereby increasing the operating current of the semiconductor structure.

[0108] The gate structure 600 is used to control the opening and closing of the transistor's channel.

[0109] The gate dielectric layer 620 is used to isolate the gate structure 600 from the first channel layer 320 and the second channel layer 420.

[0110] The gate dielectric layer 620 is made of one or more of the following materials: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer 620 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. A high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0111] It should be noted that the gate dielectric layer 620 may further include a gate oxide layer, which is located between the high-k gate dielectric layer and the first channel layer 320, and between the high-k gate dielectric layer and the second channel layer 420. Specifically, the material of the gate oxide layer may be silicon oxide.

[0112] In this embodiment, the gate electrode layer is made of one or more of the following materials: TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0113] In this embodiment, the gate structure 600 is a metal gate structure.

[0114] Therefore, the gate dielectric layer 610 includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to bring out the electrical properties of the metal gate structure.

[0115] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0116] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a first device region for forming a first device and a second device region for forming a second device, wherein the channel width of the first device is smaller than the channel width of the second device; A first channel structure is formed on the substrate of the first device region. The first channel structure includes one or more stacked first channel layers. The first channel layer includes a first sacrificial layer and a first channel layer located on the first sacrificial layer. Along the extension direction of the first channel structure, the first channel structure includes a first channel region. Along a direction perpendicular to the extension direction of the first channel structure, the first channel structure has a first width, and the material of the first sacrificial layer is a germanium-containing material. A second channel structure is formed on the substrate of the second device region. The second channel structure includes one or more stacked second channel layers. The second channel layer includes a second sacrificial layer and a second channel layer located on the second sacrificial layer. Along the extension direction of the second channel structure, the second channel structure includes a second channel region. Along a direction perpendicular to the extension direction of the second channel structure, the second channel structure has a second width, which is greater than the first width. The material of the second sacrificial layer is a germanium-containing material. The atomic percentage of germanium in the second sacrificial layer is greater than the atomic percentage of germanium in the first sacrificial layer. The thickness of the second sacrificial layer and the first sacrificial layer are the same. Remove the first sacrificial layer in the first trench region and the second sacrificial layer in the second trench region; After removing the first sacrificial layer in the first channel region and the second sacrificial layer in the second channel region, a gate structure is formed in the first channel region and the second channel region. The gate structure includes a gate dielectric layer surrounding and covering the first channel layer and the second channel layer, and a gate electrode layer located on the gate dielectric layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps of forming the first channel structure and the second channel structure include: forming a first mask layer on the substrate of the first device region or the second device region, wherein the first mask layer also covers a portion of the substrate at the junction of the first device region and the second device region. A first material layer is formed on the substrate exposed by the first mask layer, wherein when the first mask layer is located in the second device region, the first material layer is the first channel structure, and when the first mask layer is located in the first device region, the first material layer is the second channel structure. A second mask layer is formed that covers the first material layer and the first mask layer; Remove a portion of the second mask layer on the side of the first material layer, leaving the remaining second mask layer located at the junction of the second device region and the first device region, and covering the top of the first material layer; Remove the first mask layer exposed by the remaining second mask layer, and retain the remaining first mask layer located at the junction of the second device region and the first device region; A second material layer is formed on the remaining substrate exposed by the remaining first mask layer, and when the first material layer is the first channel structure, the second material layer is the second channel structure, and when the first material layer is the second channel structure, the second material layer is the first channel structure. After forming the first channel structure and the second channel structure, the method further includes: removing the remaining second mask layer and the remaining first mask layer located at the junction of the second device region and the first device region.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The step of forming the first mask layer includes: forming a mask material layer on the substrate, the mask material layer covering the substrate of the first device region and the second device region; A portion of the mask material layer in the first device region is removed, while the mask material layer in the second device region and the portion of the mask material layer at the boundary between the second device region and the first device region are retained, forming a first mask layer that exposes the substrate of the first device region; or, a portion of the mask material layer in the second device region is removed, while the mask material layer in the first device region and the portion of the mask material layer at the boundary between the second device region and the first device region are retained, forming a first mask layer that exposes the substrate of the second device region.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, In the same step, the remaining second mask layer and the remaining first mask layer located at the junction of the second device region and the first device region are removed.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first channel structure is formed by epitaxial growth; the second channel structure is formed by epitaxial growth.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the same process, the first sacrificial layer and the second sacrificial layer are removed.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first and second sacrificial layers are removed using an isotropic etching process.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The isotropic etching process includes the Certas etching process or the SiCoNi etching process.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first sacrificial layer includes silicon germanide; the material of the second sacrificial layer includes silicon germanide.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first channel layer includes silicon, germanium, or a group III-V semiconductor material; the material of the second channel layer includes silicon, germanium, or a group III-V semiconductor material.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the first channel structure and the second channel structure, and before removing the first sacrificial layer in the first channel region and the second sacrificial layer in the second channel region, the method further includes: forming a pseudo-gate structure across the first channel structure and the second channel structure on the substrate, the pseudo-gate structure covering the top and sidewalls of the first channel structure in the first channel region and the top and sidewalls of the second channel structure in the second channel region. After forming the pseudo-gate structure, an interlayer dielectric layer is formed on the substrate on the side of the pseudo-gate structure, and the interlayer dielectric layer is exposed at the top of the pseudo-gate structure. Remove the pseudo-gate structure and form a gate opening in the interlayer dielectric layer, the gate opening exposing the first channel structure of the first channel region and the second channel structure of the second channel region; The first sacrificial layer of the first channel region and the second sacrificial layer of the second channel region are removed through the gate opening.

12. The method for forming a semiconductor structure as described in claim 2, characterized in that, In the step of forming the first mask layer, the material of the first mask layer includes a dielectric material, which includes one or both of silicon oxide and silicon nitride.

13. The method for forming a semiconductor structure as described in claim 2, characterized in that, In the step of forming the second mask layer, the material of the second mask layer includes a dielectric material, which includes one or both of silicon oxide and silicon nitride.

14. The method for forming a semiconductor structure as described in claim 2, characterized in that, The first mask layer and the second mask layer are made of the same material.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the gate dielectric layer, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the gate electrode layer, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

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