Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present disclosure provide a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate, a bit line including a contact portion extending into the substrate and a main body portion on top of the contact portion, the main body portion extending along a first direction, a bottom of the contact portion being planar and having a first dimension along a second direction, a top of the contact portion having a second dimension along the second direction, the first dimension being greater than the second dimension, the first direction, the second direction and a plane where the bottom of the contact portion are parallel to a plane where the substrate is, and the first direction and the second direction intersecting, and a first isolation structure covering sidewalls of the contact portion, a bottom of the first isolation structure being planar and substantially flush with the bottom of the contact portion.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for fabricating the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory in computers and other electronic devices. DRAM memory cells typically include transistors and capacitors. The gate of the transistor is electrically connected to the word line, the source to the bit line, and the drain to the capacitor. By controlling the word line voltage, the transistor can be turned on and off, thereby allowing data to be read from or written to the capacitor via the bit line. In DRAM, reducing the contact resistance between the bit line and the source, and reducing the mutual interference between the bit line and the capacitor contact plug, are important means to improve the device's electrical performance. Summary of the Invention

[0003] According to a first aspect of this disclosure, a semiconductor device is provided, comprising:

[0004] Substrate;

[0005] The bit line includes a contact portion extending into the substrate and a main body portion located on the top surface of the contact portion. The main body portion extends along a first direction. The bottom surface of the contact portion is parallel to the plane of the substrate. The bottom of the contact portion has a first dimension along a second direction. The top of the contact portion has a second dimension along the second direction. The first dimension is larger than the second dimension. The first direction and the second direction intersect and are both parallel to the plane of the substrate.

[0006] A first isolation structure is located on the upper surface of the substrate and covers the sidewall of the contact portion. The bottom surface of the first isolation structure is parallel to the plane of the substrate, and the bottom surface of the first isolation structure is substantially flush with the bottom surface of the contact portion.

[0007] In some embodiments, the size of the contact portion gradually decreases along the second direction from the bottom to the top of the contact portion.

[0008] In some embodiments, the dimension of the bottom of the main body portion along the second direction is substantially equal to the dimension of the top of the main body portion along the second direction.

[0009] In some embodiments, the first isolation structure includes:

[0010] The first isolation layer includes a first side portion, a second side portion disposed opposite to the first side portion along the second direction, and a first bottom portion connecting the first side portion and the second side portion. The first side portion is in contact with the sidewall of the contact portion, and the bottom surface of the first bottom portion is substantially flush with the bottom surface of the contact portion.

[0011] A second isolation layer covers the side of the first isolation layer that is relatively far from the substrate;

[0012] A third isolation layer covers the side of the second isolation layer that is relatively far from the first isolation layer.

[0013] In some embodiments, the main body includes a first sub-polysilicon layer, a metal nitride layer, and a metal layer stacked sequentially along the thickness direction of the substrate, and the contact portion includes a second sub-polysilicon layer.

[0014] In some embodiments, the difference between the first size and the second size satisfies the condition that it is greater than or equal to 3 nm and less than or equal to 6 nm.

[0015] In some embodiments, the substrate includes a plurality of active regions arranged in an array, the active regions including a first doped region and a second doped region;

[0016] The bit line includes a plurality of contact portions arranged side by side along the first direction, and the bottom surface of each contact portion is in contact with the first doped region;

[0017] A capacitive contact plug is located on the substrate, and the bottom surface of the capacitive contact plug is in contact with the second doped region;

[0018] The second isolation structure is located between the main body and the capacitor contact plug.

[0019] According to a second aspect of this disclosure, a method for fabricating a semiconductor device is provided, comprising:

[0020] Provide substrate;

[0021] A contact hole is formed extending into the substrate; wherein the bottom surface of the contact hole is parallel to the plane of the substrate;

[0022] A bit line is formed; wherein the bit line includes a contact portion located within the contact hole and a main body portion located on the top surface of the contact portion, the main body portion extending along a first direction, the bottom of the contact portion having a first dimension along a second direction, the top of the contact portion having a second dimension along the second direction, and the bottom of the contact hole having a third dimension along the second direction, wherein the first dimension satisfies: greater than the second dimension and less than the third dimension; the first direction and the second direction intersect and are both parallel to the plane of the substrate.

[0023] In some embodiments, forming a contact hole extending into the substrate includes:

[0024] The first etching gas and the cleaning gas are alternately introduced into the substrate surface to form the contact hole; wherein the first etching gas is used to etch the substrate, and the cleaning gas is used to remove byproducts generated in the contact hole during the etching process.

[0025] In some embodiments, the alternating introduction of a first etching gas and a cleaning gas into the substrate surface to form the contact hole includes:

[0026] A first etching gas and a cleaning gas are alternately introduced into the substrate surface. Each time the first etching gas is introduced, it has the same carbon / fluorine ratio, and the etching parameters of the first etching gas remain unchanged.

[0027] In some embodiments, forming a bit line includes:

[0028] A bit line material layer is formed that covers the substrate surface and fills the contact holes;

[0029] The bit line material layer is etched in the first step using a second etching gas to form the main body and the contact portion; wherein the carbon / fluorine ratio of the second etching gas is greater than or equal to 0.5.

[0030] In some embodiments, forming a bit line further includes:

[0031] The main body is etched in a second step using a third etching gas, such that the bottom dimension of the main body along the second direction is substantially equal to the top dimension of the main body along the second direction; wherein the carbon / fluorine ratio of the third etching gas is less than the carbon / fluorine ratio of the second etching gas.

[0032] In some embodiments, the bit line material layer forming the substrate surface and filling the contact hole includes:

[0033] A first sub-polysilicon layer is formed to cover the surface of the substrate, and a second sub-polysilicon layer is formed to fill the contact holes;

[0034] A metal nitride layer covering the first sub-polysilicon layer and the second sub-polysilicon layer, a metal layer covering the metal nitride layer, and an insulating layer covering the metal layer are formed sequentially.

[0035] The first step of etching the bit line material layer using a second etching gas to form the main body and the contact portion includes:

[0036] The second etching gas sequentially etches portions of the insulating layer, the metal layer, the metal nitride layer, the first sub-polysilicon layer, and the second sub-polysilicon layer. The remaining second sub-polysilicon layer forms the contact portion, and the remaining first sub-polysilicon layer, the metal nitride layer, and the metal layer form the main body portion.

[0037] In some embodiments, the difference between the first size and the second size satisfies the condition that it is greater than or equal to 3 nm and less than or equal to 6 nm.

[0038] In some embodiments, the preparation method further includes:

[0039] A first isolation layer is formed covering the sidewall of the contact portion, the remaining area of ​​the bottom surface of the contact hole, and the sidewall of the contact hole;

[0040] A second isolation layer is formed that covers the first isolation layer;

[0041] A third isolation layer is formed to cover the second isolation layer; wherein the first isolation layer, the second isolation layer and the third isolation layer fill the contact hole.

[0042] The semiconductor device provided in this disclosure has a first dimension at the bottom of the contact portion along the second direction that is larger than the second dimension at the top of the contact portion along the second direction. This increases the contact area between the bottom of the contact portion and the active region, thereby reducing the contact resistance between the bit line and the active region and increasing the current I between the bit line and the active region. DS This improves the performance of the device.

[0043] Furthermore, the bottom surface of the first isolation structure is basically flush with the bottom surface of the contact portion. The first isolation structure can completely cover the sidewall of the contact portion in the substrate. After the capacitor contact plug is formed subsequently, it can completely isolate the bit line contact portion and the capacitor contact plug, avoiding short circuit between the two, thereby further improving the device performance.

[0044] Furthermore, during the contact fabrication process, contact holes are formed first, with the bottom surface of the contact holes being planar and parallel to the plane of the substrate. This increases the bottom size of the contact holes, reducing the difficulty of forming the first isolation structure and thus increasing the process window for the first isolation structure. On the other hand, after forming the bit lines, the angle between the sidewalls of the contact portion and the bottom surface of the contact holes is not less than 90°. This improves the filling effect of the first isolation structure at this angle, facilitates a more solid filling, reduces the parasitic capacitance between the bit lines and the capacitor contact plug, and further increases the process window for the first isolation structure. Attached Figure Description

[0045] Figure 1 A top view schematic diagram of a DRAM provided in an embodiment of this disclosure;

[0046] Figures 2a to 2d for Figure 1 The diagram shows a cross-sectional view of the DRAM along line AA during the fabrication process.

[0047] Figure 3 for Figure 2b The cross-sectional topography of the DRAM is shown below;

[0048] Figure 4 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure;

[0049] Figures 5a to 5g This is a schematic diagram of the structure of a semiconductor device during the fabrication process, provided by an embodiment of this disclosure;

[0050] Figure 6 for Figure 5b The diagram shows the topographic features of the semiconductor device.

[0051] Figures 7a to 7e This is a schematic diagram of the structure of a contact hole during the fabrication process, provided by an embodiment of this disclosure;

[0052] Figure 8 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Detailed Implementation

[0053] The technical solution of this disclosure will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0054] In the description of this disclosure, it should be understood that the terms “length,” “width,” “depth,” “upper,” “lower,” “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0055] Figure 1 This is a top view schematic diagram of a DRAM provided in an embodiment of the present disclosure, as shown below. Figure 1As shown, the DRAM includes a substrate 100, within which a shallow trench isolation structure 120 is disposed. The shallow trench isolation structure 120 isolates multiple active regions 110 within the substrate 100, and the multiple active regions 110 are arranged in an array. Each active region 110 includes a source 111 and a drain 112. For example, the source 111 and drain 112 are disposed along the extension direction of the active region 110 and are independent of each other. The substrate 100 also includes multiple word lines arranged along a first direction (X direction), each word line extending along a second direction (Y direction). Each word line includes a gate structure located in the active region 110. In the extension direction of the active region 110, the source 111 and drain 112 are distributed on both sides of the gate structure.

[0056] The DRAM also includes multiple bit lines 20 located on the surface of the substrate 100. Each bit line 20 extends along a first direction (X direction) and contacts the source 111 of multiple active regions 110 arranged in parallel along the first direction. The multiple bit lines 20 are arranged in parallel along a second direction (Y direction).

[0057] Figures 2a to 2d for Figure 1 The diagram shown is a cross-sectional view of the DRAM along line AA during the fabrication process. Figure 3 for Figure 2b The image shows a cross-sectional topographic view of the DRAM. See also... Figure 2a A substrate 100 is provided, which includes a plurality of active regions 110 arranged in an array. Bit line contact holes 30 are formed extending into the substrate 100, and the orthographic projection of the contact holes 30 on the surface of the substrate 100 and the orthographic projection of the active regions 110 on the surface of the substrate 100 partially overlap, that is, the bottom of the bit line contact holes 30 exposes the active regions 110.

[0058] See Figure 2b A bit line material layer 40 is formed to fill the bit line contact hole 30 and cover the surface of the substrate 100.

[0059] See Figure 2c The bit line material layer 40 is etched to form a bit line 20, wherein the bottom of the bit line 20 is in contact with the active region 110 at the bottom of the bit line contact hole 30.

[0060] See Figure 2d A first silicon nitride layer 51 is formed inside the bit line contact hole 30, covering the sidewall of the bit line 20, the bottom remaining area of ​​the bit line contact hole 30, and the sidewall of the bit line contact hole 30. A silicon oxide layer 52 is formed covering the first silicon nitride layer 51, and a second silicon nitride layer 53 is formed covering the silicon oxide layer 52. The first silicon nitride layer 51, the silicon oxide layer 52, and the second silicon nitride layer 53 constitute a NON structure 50 with an isolation function.

[0061] like Figures 2a to 2d ,as well as Figure 3As shown, the cross-section of the bit line contact hole is roughly U-shaped, with a downward-concave arc surface at the bottom, resulting in a smaller process window for the NON structure. For example, after the bit line is formed, the width of the remaining space at the bottom of the bit line contact hole is small, and the bottom of the bit line contact hole may be filled after the first silicon nitride layer is formed, making it impossible to form a NON structure at the bottom. Furthermore, if the angle α between the sidewall of the bit line and the bottom surface of the bit line contact hole is acute, insufficient filling may occur at the bottom of the bit line contact hole, such as voids. This could lead to a short circuit between the capacitor contact plug and the bit line when forming the capacitor contact plug. One feasible method is to reduce the width of the bit line along the second direction (Y direction) and keep the sidewall of the bit line basically vertical (parallel to the Z direction) or make the sidewall of the bit line at an acute angle to the bottom wall of the bit line contact hole, thus leaving sufficient space for the sidewall to form a complete NON structure. However, this will reduce the contact area between the bottom of the bit line and the active region, resulting in an increase in the contact resistance of the bit line and the current (I) between the bit line and the active region. DS The decrease in [something] affects the performance of the device.

[0062] Therefore, this disclosure provides a method for fabricating a semiconductor device. Figure 4 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure. Figure 4 As shown, the method for fabricating this semiconductor device includes:

[0063] S100: Provides a substrate;

[0064] S200: Forming a contact hole extending into the substrate, with the bottom surface of the contact hole parallel to the plane of the substrate;

[0065] S300: Form a bit line, the bit line includes a contact portion located in the contact hole and a main body portion located on the top surface of the contact portion, the main body portion extends along a first direction, the bottom of the contact portion has a first dimension along a second direction, the top of the contact portion has a second dimension along a second direction, and the bottom of the contact hole has a third dimension along a second direction, the first dimension being greater than the second dimension and less than the third dimension.

[0066] Figures 5a to 5g This is a schematic diagram of the structure of a semiconductor device during the fabrication process, provided by an embodiment of this disclosure. Figure 6 for Figure 5b The diagram shows the topographic features of the semiconductor device. The following will combine... Figures 5a to 5e ,as well as Figure 6 The method for fabricating a semiconductor device provided in the embodiments of this disclosure is described.

[0067] See Figure 5aA substrate 100 is provided, on which a first dielectric layer 210, a second dielectric layer 220, a first sub-polysilicon layer 311 and a mask layer 400 are formed in sequence; and a contact hole 500 is formed that penetrates the mask layer 400, the first sub-polysilicon layer 311, the second dielectric layer 220 and the first dielectric layer 210 and extends into the substrate 100.

[0068] In some embodiments, the substrate 100 includes a shallow trench isolation structure 120 and a plurality of active regions 110 arranged in an array. The shallow trench isolation structure 120 isolates the plurality of active regions 110. Each active region 110 includes a first doped region and a second doped region, one of which is a source and the other is a drain. For example, the first doped region and the second doped region are disposed along the extending direction of the active regions 110 and are isolated from each other.

[0069] In some embodiments, the first dielectric layer 210 is made of silicon oxide, and the second dielectric layer 220 is made of silicon nitride. The first dielectric layer 210 and the second dielectric layer 220 are used to isolate the bit line body portion and the substrate 100.

[0070] The orthographic projection of the contact hole 500 onto the surface of the substrate 100 and the orthographic projection of the active region 110 onto the surface of the substrate 100 partially overlap, meaning the contact hole 500 extends into the active region 110. The depth of the contact hole 500 along the Z direction is less than the thickness of the active region 110, such that the bottom of the contact hole 500 exposes the active region 110. For example, the bottom of the contact hole 500 exposes a first doped region of the active region 110.

[0071] like Figure 5a As shown, the bottom surface of the contact hole 500 is planar, and the plane containing the bottom surface is parallel to the plane containing the substrate 100. In some embodiments, to form as shown... Figure 5a The contact hole 500 shown, the step of forming the contact hole 500 includes:

[0072] A first etching gas and a cleaning gas are alternately introduced into the substrate surface to form a contact hole; wherein, the first etching gas is used to etch the substrate 100, and the cleaning gas is used to remove the by-products generated in the contact hole during the etching process.

[0073] Figures 7a to 7e This is a schematic diagram of the structure of a contact hole during the preparation process provided in an embodiment of the present disclosure. Table 1 shows the composition of the first gas and the cleaning gas used in the process of forming the contact hole.

[0074] Table 1. Composition of etching and cleaning gases during contact hole fabrication.

[0075] step gas Etching <![CDATA[Cl2、CH2F2、CF4、He]]> Cleaning Ar Etching <![CDATA[Cl2、CH2F2、CF4、He]]> Cleaning Ar Etching <![CDATA[Cl2、CH2F2、CF4、Ar]]>

[0076] like Figure 7aAs shown, a patterned mask layer 400 is used as a mask to introduce a first etching gas into the surface of the substrate 100. The first etching gas sequentially etches the first sub-polysilicon layer 311 and the second dielectric layer 220 from top to bottom, forming a first via 510. During the etching process, byproducts 610 are deposited at the bottom and sidewalls of the first via 510.

[0077] For example, as shown in Table 1, the composition of the first etching gas used in the etching process may include: Cl2 (chlorine), CH2F2 (difluoromethane), CF4 (tetrafluoromethane), and He (helium). The byproduct 610 is primarily polymers, which can prevent etching from proceeding.

[0078] like Figure 7b As shown, a cleaning gas is introduced into the first orifice section 510, and the flowing cleaning gas carries away the byproducts at the bottom of the first orifice section 510, thus cleaning the bottom of the first orifice section 510. For example, the cleaning gas may include Ar (argon).

[0079] like Figure 7c As shown, the first etching gas is introduced into the first hole segment 510 again, and the first dielectric layer 210 and the substrate 100 are etched downwards to form the second hole segment 520. The by-product 620 generated during this etching process is partially deposited on the bottom and sidewalls of the second hole segment 520.

[0080] For example, the composition of the first etching gas used in this etching process may include: Cl2, CH2F2, CF4, and He. The byproduct 620 is primarily a polymer.

[0081] In this step, since the byproducts in the first hole section are removed, the first etching gas can uniformly etch the substrate 100 downwards in the first hole section, making the bottom surface of the second hole section 520 a plane.

[0082] like Figure 7d As shown, a cleaning gas is introduced into the first orifice section 510 and the second orifice section 520 to carry away the byproducts at the bottom of the second orifice section 520, thus keeping the bottom of the second orifice section 520 clean. For example, the cleaning gas may include Ar.

[0083] like Figure 7e As shown, the first etching gas is introduced again into the first and second aperture sections to continue etching the substrate 100 downwards along the second aperture section, forming... Figure 5a The contact hole 500 is shown. For example, the composition of the first etching gas used in this etching process may include: Cl2, CH2F2, CF4, and Ar. The byproduct 620 is primarily a polymer.

[0084] Here, Ar (argon gas) has a cleaning function. The etching gas used in the final etching step includes argon, enabling simultaneous etching and cleaning. This ensures that the contact hole 500 remains clean after the final etching step, thereby reducing one cleaning step and shortening the process cycle. It should be understood that in some embodiments, a cleaning step may be added after the final etching step to keep the contact hole 500 clean. In this case, the etching gas used in the final etching step may not include a gas with a cleaning function.

[0085] Understandably, if a one-step etching method is used to form the contact hole, the byproducts generated during the initial etching will remain at the bottom. This will cause the areas covered by the byproducts to be etched slowly or not at all during subsequent etching, resulting in the bottom of the contact hole not being a plane. In this embodiment, etching and cleaning steps are performed alternately multiple times to remove the byproducts generated in each etching step. When performing the next etching step, the etching gas can uniformly etch the substrate downwards, so that the bottom surface of the contact hole always remains flat after each etching step, thus ensuring that the bottom surface of the contact hole 500 that finally reaches the specified depth is also flat.

[0086] In some embodiments, when the first etching gas and the cleaning gas are alternately introduced to the substrate surface, the first etching gas introduced each time has the same carbon / fluorine ratio. For example, as shown in Table 1, the first etching gas introduced the second time is the same as the first etching gas introduced the first time, and the first etching gas introduced the third time is different from the second time, except that He is replaced with Ar, while still containing the same proportions of CH2F2 and CF4. That is, the first etching gas introduced in all three times has the same proportions of CH2F2 and CF4, and the first etching gas introduced in all three times has the same carbon / fluorine ratio.

[0087] In some embodiments, the first etching gas introduced each time can be exactly the same.

[0088] In some embodiments, when the first etching gas and the cleaning gas are alternately introduced to the substrate surface, the etching parameters of the first etching gas remain unchanged each time.

[0089] For example, etching parameters include gas flow rate, gas inlet angle, power supply, power supply frequency, etching time, etc.

[0090] Figures 5b to 5d The process of forming bit lines is illustrated. Among them, Figure 5b and 5c The process of forming a bit line material layer is shown, which covers the surface of substrate 100 and fills contact holes 500.

[0091] like Figure 5bAs shown, the mask layer 400 is removed to form a second sub-polysilicon layer 312 that fills the contact holes 500. The top of the second sub-polysilicon layer 312 is substantially flush with the top of the first sub-polysilicon layer 311. The first sub-polysilicon layer 311 and the second sub-polysilicon layer 312 constitute the polysilicon layer 310 of the bit line material layer.

[0092] It should be understood that in some embodiments, the first sub-polysilicon layer may not be deposited before the contact hole is formed, but after the contact hole is formed, a polysilicon layer 310 covering the surface of the substrate 100 and filling the contact hole 500 may be formed in a process step.

[0093] See Figure 5c A metal nitride layer 320 covering the polysilicon layer 310, a metal layer 330 covering the metal nitride layer 320, and an insulating layer 340 covering the metal layer 330 are sequentially formed. The polysilicon layer, the metal nitride layer 320, and the metal layer 330 constitute the bit line material layer 300.

[0094] For example, the metal nitride layer 320 may be made of materials including, but not limited to, titanium nitride, tantalum nitride, and tungsten nitride. The metal layer 330 may be made of materials including, but not limited to, tungsten, titanium, tantalum, copper, aluminum, gold, and cobalt. The insulating layer 340 may be made of materials including, but not limited to, silicon oxide, silicon nitride, and silicon oxynitride.

[0095] See Figure 5d The bit line material layer 300 is etched in the first step to form the main body 301 and the contact part 302 of the bit line.

[0096] For example, a bit line mask layer is formed above the insulating layer 340, the bit line mask layer is patterned, and a second etching gas is introduced into the exposed surface of the insulating layer 340. The second etching gas etches the insulating layer 340, the metal layer 330, the metal nitride layer 320, the first sub-polysilicon layer 311, and the second sub-polysilicon layer 312 sequentially from top to bottom. The remaining second sub-polysilicon layer 312 located inside the contact hole 500 forms a contact portion 302, and the remaining first sub-polysilicon layer 311, the metal nitride layer 320, and the metal layer 330 located outside the contact hole 500 form a main body portion 301.

[0097] like Figure 5d The contact portion 302 has a first dimension L1 at its bottom along the second direction, a second dimension L2 at its top along the second direction, and a third dimension L3 at its bottom along the second direction. The first dimension L1 satisfies: L2 < L1 < L3.

[0098] For example, such as Figure 5d and Figure 6As shown, the cross-section of the contact portion 302 of the bit line is approximately conical with a smaller top and a larger bottom. In other words, the size of the contact portion 302 gradually decreases along the second direction from bottom to top.

[0099] In some embodiments, the carbon / fluorine ratio of the second etching gas is greater than or equal to 0.5. For example, the carbon / fluorine ratio of the second etching gas is greater than or equal to 1 and less than or equal to 4. A higher carbon / fluorine ratio in the etching gas facilitates polymer formation. In this embodiment, using a gas with a high carbon / fluorine ratio promotes polymer formation and adhesion to the sidewalls of the formed bit lines and the bottom of the trenches between adjacent formed bit lines. The polymer acts as a protective layer, reducing or preventing the second etching gas from etching the polymer-covered area, thereby forming a bit line morphology that is smaller at the top and larger at the bottom.

[0100] For example, the composition of the second etching gas may include HBr (hydrogen bromide) and C2F4 (tetrafluoroethylene). In other embodiments, the second etching gas may also include CH2F2, ClF3 (chlorine trifluoride), and CHF3 (trifluoromethane).

[0101] In some embodiments, during the etching of the bit line material layer 300 using a second etching gas, the cleaning step can be reduced or eliminated, which is more conducive to forming bit lines that are smaller at the top and larger at the bottom.

[0102] Here, as Figure 5d As shown, after the first etching step, the bottom dimension of the entire bit line along the second direction is greater than the top dimension of the bit line along the second direction. That is, the bottom dimension L5 of the main body 301 of the bit line along the second direction is greater than the top dimension L6 along the second direction.

[0103] In some embodiments, such as Figure 5e As shown, the steps for forming bit lines also include:

[0104] The main body 301 is etched in a second step using a third etching gas so that the dimension L5 of the bottom of the main body 301 along the second direction is substantially equal to the dimension L6 of the top of the main body 301 along the second direction.

[0105] In this step, by reducing the bottom dimension L5 of the main body 301 above the shallow trench isolation structure 120, the distance between adjacent bit lines is increased, which facilitates the accurate fabrication of subsequent capacitor contact plugs on the active region 110. Furthermore, the increased distance between adjacent bit lines also reduces the parasitic capacitance between them, improving device performance.

[0106] In some embodiments, the composition of the third etching gas may differ from that of the second etching gas. The carbon / fluorine ratio of the third etching gas is lower than that of the second etching gas, thereby reducing the amount of polymer generated during the etching process. The height of the main body 301 is higher than that of the contact portion 302, making it easier for the main body 301 to react with the third etching gas. This allows for a more efficient reduction of the bottom dimension L5 of the main body 301 to be equal to its top dimension L6.

[0107] For example, the composition of the third etching gas may include HBr, CH2F2, CF4 and He, and the introduction time of the third etching gas is less than half the introduction time of the second etching gas.

[0108] See Figure 5f A first isolation layer 710 is formed covering the sidewall of the contact portion 302, the remaining area of ​​the bottom surface of the contact hole 500, and the sidewall of the contact hole 500; a second isolation layer 720 is formed covering the first isolation layer 710; and a third isolation layer 730 is formed covering the second isolation layer 720; wherein the first isolation layer 710, the second isolation layer 720, and the third isolation layer 730 fill the contact hole.

[0109] For example, the first isolation layer 710 is made of silicon nitride, the second isolation layer 720 is made of silicon oxide, and the third isolation layer 730 is made of silicon nitride, forming a first isolation structure 700 with a NON structure.

[0110] In this embodiment, the bottom surface of the contact hole 500 is planar and the plane containing the bottom surface is parallel to the plane containing the substrate. This results in a larger bottom dimension L3 of the contact hole 500 when the top dimensions of the contact hole 500 and the contact hole 30 are equal, reducing the process difficulty of forming the first isolation structure and thus increasing the process window of the first isolation structure. On the other hand, after the bit line is formed, the included angle between the sidewall of the contact portion 302 and the bottom surface of the contact hole 500 is not less than 90°, which can improve the filling effect of the first isolation structure at this angle, making it easier to form a more solid filling, reducing the parasitic capacitance between the bit line and the capacitor contact plug, and further increasing the process window of the first isolation structure. Furthermore, with the increased process window of the first isolation structure, the dimension of the bottom of the contact portion along the second direction can be increased, thereby reducing the contact resistance between the bit line and the active region and increasing the current I between the bit line and the active region. DS This improves the performance of the device.

[0111] In some embodiments, the difference between the first dimension L1 and the second dimension L2 satisfies: 3nm ≤ L1 - L2 ≤ 6nm. Here, if the first dimension is too small, the contact resistance between the bit line and the active region will be large; if the first dimension is too large, the space within the contact hole for forming the first isolation structure will be too small, resulting in poor filling of the first isolation structure and a tendency for short circuits between the bit line contact and the subsequently formed capacitor contact plug. In this embodiment, when the first dimension is within the above range, the filling of the first isolation structure is more compact, and the contact resistance between the bit line and the active region is reduced, which is beneficial for improving device performance.

[0112] In some embodiments, such as Figure 5a As shown, the top of the contact hole 500 has a fourth dimension L4 along the second direction, and the third dimension is smaller than the fourth dimension. That is, the cross-section of the contact hole 500 is roughly larger at the top and smaller at the bottom, which is conducive to the deposition of the first isolation structure.

[0113] For example, the difference between the fourth and third dimensions satisfies: 5nm ≤ L4 - L3 ≤ 9nm. This allows the sidewalls of the contact hole 500 to have a suitable inclination, which improves the deposition effect of the first isolation structure.

[0114] In some embodiments, such as Figure 5a As shown, the distance L7 between the sidewall of the contact hole 500 extending to one active region 110 and the sidewall of another adjacent active region 110 along the second direction satisfies: 2nm ≤ L7 ≤ 4nm. Here, the sidewall of the contact hole 500 is the sidewall relatively close to the other active region 110, and the sidewall of the other active region 110 is the sidewall relatively close to the contact hole 500. This arrangement reduces the probability of the contact hole 500 damaging adjacent active regions 110 due to overlay accuracy (OVL).

[0115] In some embodiments, such as Figure 5f As shown, the preparation method further includes:

[0116] A fourth isolation layer 810 is formed covering the sidewall of the main body 301 and the area of ​​the first dielectric layer 210 not covered by the bit line, a fifth isolation layer 820 covering the fourth isolation layer 810, and a sixth isolation layer 830 covering the fifth isolation layer 820.

[0117] For example, the fourth isolation layer 810 is made of silicon nitride, the fifth isolation layer 820 is made of silicon oxide, and the sixth isolation layer 830 is made of silicon nitride. The fourth isolation layer 810, the fifth isolation layer 820 and the sixth isolation layer 830 constitute a second isolation structure 800 with a NON structure.

[0118] For example, the fourth isolation layer 810 and the first isolation layer 710 can be formed simultaneously.

[0119] In some embodiments, such as Figure 5g As shown, the preparation method further includes:

[0120] A capacitor contact plug 900 is formed; wherein the capacitor contact plug 900 extends along the thickness direction (Z direction) of the substrate 100 and extends into the second doped region of the active region.

[0121] In this embodiment, the first isolation structure 700 has a good filling effect. When the capacitor contact plug 900 extends into the substrate 100, the first isolation structure 700 can effectively isolate the capacitor contact plug 900 and the bit line contact portion 302, avoiding short circuit between the two and giving the device better performance.

[0122] This disclosure also provides a semiconductor device. Figure 8 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure, such as... Figure 8 As shown, the semiconductor device includes a substrate 100. For example, the substrate 100 includes a shallow trench isolation structure 120 and a plurality of active regions 110 arranged in an array. The shallow trench isolation structure 120 isolates the plurality of active regions 110. The active regions 110 include a first doped region and a second doped region. One of the first doped region and the second doped region is a source and the other is a drain.

[0123] For example, the first doped region and the second doped region are arranged along the extension direction of the active region 100 and are isolated from each other.

[0124] The semiconductor device also includes a bit line, which includes a contact portion 302 extending into the substrate 100 and a body portion 301 located on the top surface of the contact portion 302. The body portion 301 is located on the surface of the substrate 100 and extends along a first direction (X direction). The bottom surface of the contact portion 302 contacts the first doped region of the active region 110.

[0125] like Figure 8 As shown, the bottom surface of the contact portion 302 is planar, and the plane containing the bottom surface is parallel to the plane containing the substrate 100. The bottom of the contact portion 302 has a first dimension L1 along the second direction (Y direction), and the top of the contact portion 302 has a second dimension L2 along the second direction, wherein the first dimension is larger than the second dimension;

[0126] The first isolation structure 700 is located inside the substrate 100. The first isolation structure 700 covers the sidewall of the contact portion 302. The bottom surface of the first isolation structure 700 is parallel to the plane of the substrate 100, and the bottom surface of the first isolation structure 700 is basically flush with the bottom surface of the contact portion 302.

[0127] In this embodiment, the first dimension of the bottom of the contact portion along the second direction is larger than the second dimension of its top along the second direction, which increases the contact area between the bottom of the contact portion and the active region, thereby reducing the contact resistance between the bit line and the active region and increasing the current I between the bit line and the active region. DS This improves device performance. Furthermore, the bottom surface of the first isolation structure is essentially flush with the bottom surface of the contact portion. The first isolation structure can completely cover the sidewall of the contact portion located within the substrate. After the capacitor contact plug is subsequently formed, it can completely isolate the bit line contact portion and the capacitor contact plug, preventing short circuits and further improving device performance.

[0128] In some embodiments, such as Figure 8 As shown, along the direction from the bottom to the top of the contact portion 302 (i.e.) Figure 8 From bottom to top, the size of the contact portion 302 gradually decreases along the second direction. The cross-section of the contact portion 302 is roughly a tapered structure with a smaller top and a larger bottom, which facilitates improving the filling effect of the first isolation structure during the manufacturing process.

[0129] In some embodiments, the bottom of the contact portion 302 has a first dimension L1 along the second direction, and its top has a second dimension L2 along the second direction. The difference between the first dimension L1 and the second dimension L2 satisfies: 3nm ≤ L1 - L2 ≤ 6nm. In this embodiment, when the first dimension is within the above range, the filling of the first isolation structure can be made more compact, and the contact resistance between the bit line and the active region 110 can be reduced, which is beneficial to improving the performance of the device.

[0130] In some embodiments, such as Figure 8 As shown, the bottom dimension L5 of the main body 301 along the second direction is basically equal to the top dimension L6 along the second direction. This allows for a larger distance between adjacent bit lines, thereby reducing the parasitic capacitance between adjacent bit lines.

[0131] In some embodiments, such as Figure 8 As shown, the first isolation structure 700 includes:

[0132] The first isolation layer 710 includes a first side portion, a second side portion disposed opposite to the first side portion along a second direction, and a first bottom portion connecting the first side portion and the second side portion. The first side portion covers the side wall of the contact portion 302, and the bottom surface of the first bottom portion is substantially flush with the bottom surface of the contact portion 302.

[0133] The second isolation layer 720 covers the side of the first isolation layer 710 that is relatively far away from the substrate 100;

[0134] The third isolation layer 730 covers the side of the second isolation layer 720 that is relatively far away from the first isolation layer 710.

[0135] Here, the side of the first isolation layer 710 that is relatively far from the substrate 100 is the interior of the space enclosed by the first side, the second side, and the first bottom of the first isolation layer 710. The second isolation layer 720 covers the sidewall of the first side that is relatively far from the contact portion 302, the top surface of the first bottom, and the sidewall of the second side that is relatively close to the first side.

[0136] For example, the top surfaces of the first isolation layer 710, the second isolation layer 720, and the third isolation layer 730 are substantially flush.

[0137] In this embodiment, the first isolation layer 710, the second isolation layer 720 and the third isolation layer 730 form a first isolation structure 700 with a non-non structure, which has a better isolation effect.

[0138] In some embodiments, the main body portion 301 of the bit line includes a first sub-polysilicon layer 311, a metal nitride layer 320 and a metal layer 330 stacked sequentially from bottom to top, and the contact portion 302 includes a second sub-polysilicon layer.

[0139] In some embodiments, the bit line includes a plurality of contact portions 302 arranged side by side along a first direction, the top surface of each contact portion 302 being in contact with the main body portion 301, and the bottom surface of each contact portion 302 being in contact with a first doped region of an active region 110.

[0140] In some embodiments, the semiconductor device further includes a second isolation structure 800 and a capacitor contact plug 900, the capacitor contact plug 900 extending into the substrate 100 and the bottom surface of the capacitor contact plug 900 contacting the second doped region, the second isolation structure 800 covering the sidewall of the main body portion 301 of the bit line and located between the capacitor contact plug 900 and the main body portion 301.

[0141] For example, the second isolation structure 800 includes a fourth isolation layer 810, a fifth isolation layer 820, and a sixth isolation layer 830 stacked sequentially along a second direction. The fourth isolation layer 810 is made of silicon nitride, the fifth isolation layer 820 is made of silicon oxide, and the sixth isolation layer 830 is made of silicon nitride, forming a NON structure.

[0142] The above embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this disclosure. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this disclosure should still be covered by the claims of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Substrate; The bit line includes a contact portion extending into a contact hole in the substrate and a main body portion located on the top surface of the contact portion. The main body portion extends along a first direction, the bottom surface of the contact portion is parallel to the plane of the substrate, the bottom of the contact portion has a first dimension along a second direction, the top of the contact portion has a second dimension along the second direction, the first dimension is larger than the second dimension, and the first direction and the second direction intersect and are both parallel to the plane of the substrate. A first isolation structure is located on the upper surface of the substrate and covers the sidewall of the contact portion. The bottom surface of the first isolation structure is parallel to the plane of the substrate, and the bottom surface of the first isolation structure and the bottom surface of the contact portion are substantially flush. The contact hole is formed by alternately introducing a first etching gas and a cleaning gas into the substrate surface. The first etching gas is used to etch the substrate, and the cleaning gas is used to remove byproducts generated in the contact hole during the etching process.

2. The semiconductor device according to claim 1, characterized in that, Along the direction from the bottom to the top of the contact portion, the size of the contact portion gradually decreases in the second direction.

3. The semiconductor device according to claim 1, characterized in that, The dimension of the bottom of the main body along the second direction is substantially equal to the dimension of the top of the main body along the second direction.

4. The semiconductor device according to claim 1, characterized in that, The first isolation structure includes: The first isolation layer includes a first side portion, a second side portion disposed opposite to the first side portion along the second direction, and a first bottom portion connecting the first side portion and the second side portion. The first side portion is in contact with the sidewall of the contact portion, and the bottom surface of the first bottom portion is substantially flush with the bottom surface of the contact portion. A second isolation layer covers the side of the first isolation layer that is relatively far from the substrate; A third isolation layer covers the side of the second isolation layer that is relatively far from the first isolation layer.

5. The semiconductor device according to claim 1, characterized in that, The main body includes a first sub-polysilicon layer, a metal nitride layer and a metal layer stacked sequentially along the thickness direction of the substrate, and the contact portion includes a second sub-polysilicon layer.

6. The semiconductor device according to claim 1, characterized in that, The difference between the first size and the second size satisfies the condition that it is greater than or equal to 3nm and less than or equal to 6nm.

7. The semiconductor device according to claim 1, characterized in that, The substrate includes a plurality of active regions arranged in an array, the active regions including a first doped region and a second doped region; The bit line includes a plurality of contact portions arranged side by side along the first direction, and the bottom surface of each contact portion is in contact with the first doped region; A capacitive contact plug is located on the substrate, and the bottom surface of the capacitive contact plug is in contact with the second doped region; The second isolation structure is located between the main body and the capacitor contact plug.

8. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A contact hole extending into the substrate is formed; wherein the bottom surface of the contact hole is parallel to the plane of the substrate; the formation of the contact hole extending into the substrate includes: alternately introducing a first etching gas and a cleaning gas into the substrate surface to form the contact hole; wherein the first etching gas is used to etch the substrate, and the cleaning gas is used to remove byproducts generated in the contact hole during the etching process; A bit line is formed; wherein the bit line includes a contact portion located within the contact hole and a main body portion located on the top surface of the contact portion, the main body portion extending along a first direction, the bottom of the contact portion having a first dimension along a second direction, the top of the contact portion having a second dimension along the second direction, and the bottom of the contact hole having a third dimension along the second direction, wherein the first dimension satisfies: greater than the second dimension and less than the third dimension; the first direction and the second direction intersect and are both parallel to the plane of the substrate.

9. The preparation method according to claim 8, characterized in that, The alternating introduction of a first etching gas and a cleaning gas into the substrate surface to form the contact hole includes: A first etching gas and a cleaning gas are alternately introduced into the substrate surface. Each time the first etching gas is introduced, it has the same carbon / fluorine ratio, and the etching parameters of the first etching gas remain unchanged.

10. The preparation method according to claim 8, characterized in that, The formation of bit lines includes: A bit line material layer is formed that covers the substrate surface and fills the contact holes; The bit line material layer is etched in the first step using a second etching gas to form the main body and the contact portion; wherein the carbon / fluorine ratio of the second etching gas is greater than or equal to 0.

5.

11. The preparation method according to claim 10, characterized in that, The formation of bit lines further includes: The main body is etched in a second step using a third etching gas, such that the bottom dimension of the main body along the second direction is substantially equal to the top dimension of the main body along the second direction; wherein the carbon / fluorine ratio of the third etching gas is less than the carbon / fluorine ratio of the second etching gas.

12. The preparation method according to claim 10, characterized in that, The bit line material layer forming the substrate surface and filling the contact holes includes: A first sub-polysilicon layer is formed to cover the surface of the substrate, and a second sub-polysilicon layer is formed to fill the contact holes; A metal nitride layer covering the first sub-polysilicon layer and the second sub-polysilicon layer, a metal layer covering the metal nitride layer, and an insulating layer covering the metal layer are formed sequentially. The first step of etching the bit line material layer using a second etching gas to form the main body and the contact portion includes: The second etching gas sequentially etches portions of the insulating layer, the metal layer, the metal nitride layer, the first sub-polysilicon layer, and the second sub-polysilicon layer. The remaining second sub-polysilicon layer forms the contact portion, and the remaining first sub-polysilicon layer, the metal nitride layer, and the metal layer form the main body portion.

13. The preparation method according to claim 8, characterized in that, The difference between the first size and the second size satisfies the condition that it is greater than or equal to 3nm and less than or equal to 6nm.

14. The preparation method according to claim 8, characterized in that, The preparation method further includes: A first isolation layer is formed covering the sidewall of the contact portion, the remaining area of ​​the bottom surface of the contact hole, and the sidewall of the contact hole; A second isolation layer is formed that covers the first isolation layer; A third isolation layer is formed to cover the second isolation layer; wherein the first isolation layer, the second isolation layer and the third isolation layer fill the contact hole.

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