Semiconductor devices and their fabrication methods

Abstract

This disclosure discloses a semiconductor device and its fabrication method. The semiconductor device includes: a substrate, a buffer layer, a channel layer, and a barrier layer stacked sequentially; several transition layers disposed on the barrier layer, wherein each transition layer includes a first P-type doped GaN layer disposed on the barrier layer and a first P-type doped layer disposed on the first P-type doped GaN layer; a capping layer disposed on the transition layers; a gate electrode disposed on the capping layer; a source electrode disposed on the barrier layer; and a drain electrode disposed on the barrier layer, respectively disposed on opposite sides of the gate electrode; wherein the doping concentration of the first P-type doped GaN layer is configured to decrease from the side closer to the first P-type doped layer towards the side closer to the substrate. The technical solution disclosed in this disclosure can improve the problem of decreased mobility in the non-gate region.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor technology. More specifically, this disclosure relates to a semiconductor device and a method for fabricating the same. Background Technology

[0002] Heterogeneous structures based on high electron mobility transistors (HEMTs) possess spontaneous polarization and piezoelectric polarization effects, allowing for the generation of high-density two-dimensional electron gases (2DEGs) without the need for doping or other techniques. Their high mobility makes them suitable for high-power and high-frequency electronic devices. Existing HEMT power devices include depletion-mode and enhancement-mode types. The 2DEGs induced by the polarization of the AlGaN / GaN interface, epitaxially grown in group III nitrides, often result in depletion-mode (D-mode) HEMTs. However, enhancement-mode (E-mode) HEMTs offer lower losses, simpler circuitry, and higher security.

[0003] Currently, a P-GaN capping layer technique is widely used in the fabrication of enhancement-mode HEMTs. This technique involves epitaxially growing P-GaN to raise the energy band of the 2DEG channel, depleting the 2DEG in the gate electrode channel and thus forming an enhancement-mode HEMT. This technique avoids the influence of ion etching on channel electrons, resulting in a higher saturation current for the semiconductor device. However, to ensure that the P-GaN capping layer can completely deplete the 2DEG in the channel, a relatively thin barrier layer is usually required in the heterostructure, for example, about 25 nm thick. Undoped Mg atoms in the P-GaN capping layer easily form defects, reducing the crystal quality of the P-GaN capping layer. These defects also readily penetrate into the thinner barrier layer below, increasing internal electron scattering and leading to a decrease in the semiconductor device's mobility.

[0004] In view of this, there is an urgent need to provide a semiconductor device and its fabrication method that can ensure the mobility of the non-gate region. Summary of the Invention

[0005] In order to at least address one or more of the technical problems mentioned above, this disclosure proposes semiconductor devices and methods for fabricating them in several aspects to effectively prevent the decrease in mobility of non-gate regions.

[0006] In a first aspect, this disclosure provides a semiconductor device comprising: a substrate; a buffer layer disposed on the substrate; a channel layer disposed on the buffer layer; a barrier layer disposed on the channel layer; a plurality of transition layers disposed on the barrier layers, wherein each of the transition layers comprises a first P-type doped GaN layer disposed on the barrier layer and a first P-type doped layer disposed on the first P-type doped GaN layer; a capping layer disposed on the transition layers; a gate disposed on the capping layer; a source disposed on the barrier layer; and a drain disposed on the barrier layer, respectively disposed on opposite sides of the gate and the source; wherein the doping concentration of the first P-type doped GaN layer is configured to decrease from the side closer to the first P-type doped layer to the side closer to the substrate.

[0007] In a second aspect, this disclosure provides a method for fabricating a semiconductor device, comprising: providing a semiconductor epitaxial structure, wherein the semiconductor epitaxial structure includes: a substrate, a buffer layer, a channel layer, and a barrier layer stacked sequentially; disposing of a plurality of pre-fabricated transition layers on the semiconductor epitaxial structure, wherein each pre-fabricated transition layer includes an intrinsic u-GaN layer disposed on the barrier layer and a heavily doped P-type layer disposed on the intrinsic u-GaN layer; forming a rudimentary capping layer on the pre-fabricated transition layers; etching the rudimentary capping layer and the pre-fabricated transition layers, and performing high-temperature tempering on the semiconductor device after etching the rudimentary capping layer and the pre-fabricated transition layers to form the pre-fabricated transition layers into transition layers; wherein a first P-type doped layer in the transition layers is formed by the heavily doped P-type layer, and a first P-type doped GaN layer in the transition layers is formed by the intrinsic u-GaN layer; the doping concentration of the first P-type doped GaN layer is configured to decrease from the side closer to the first P-type doped layer to the side closer to the substrate.

[0008] The semiconductor device disclosed herein has several transition layers, each of which includes a first P-type doped GaN layer disposed on a barrier layer and a first P-type doped layer disposed on the first P-type doped GaN layer. The doping concentration of the first P-type doped GaN layer is configured to decrease from the side closer to the first P-type doped layer to the side closer to the substrate. During the fabrication of the semiconductor device, the first P-type doped GaN layer in the transition layer can effectively block and reduce the diffusion of doped impurities in the P-type gate to the barrier layer, thereby improving the problem of decreased mobility in the non-gate region and ultimately reducing the on-resistance of the device and improving the conduction performance of the device. Attached Figure Description

[0009] The above and other objects, features, and advantages of exemplary embodiments of this disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0010] Figure 1 Schematic diagrams of the structure of semiconductor devices according to some embodiments of this disclosure are shown;

[0011] Figure 2 A schematic flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of this disclosure is shown;

[0012] Figure 3 Another schematic flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of this disclosure is shown;

[0013] Figure 4 A schematic flowchart illustrating a method for fabricating a semiconductor epitaxial structure according to some embodiments of this disclosure is shown;

[0014] Figure 5 A schematic diagram of the epitaxial structure of a semiconductor device according to some embodiments of this disclosure is shown. Detailed Implementation

[0015] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0016] It should be understood that the terms “comprising” and “including” used in this disclosure and claims indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0017] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0018] Currently, a P-GaN capping layer technique is widely used in the fabrication of enhanced HEMTs. This technique avoids the impact of ion etching on channel electrons, resulting in higher saturation current for the semiconductor device. However, to ensure that the P-GaN capping layer can completely deplete the 2DEG in the channel, a relatively thin barrier layer is usually required in the heterostructure, for example, the thickness of the barrier layer is about 25 nm. However, the undoped Mg in the P-GaN capping layer is prone to forming defects, which reduces the crystal quality of the P-GaN capping layer. At the same time, these defects can easily penetrate into the thinner barrier layer below, increasing internal electron scattering and leading to a decrease in the mobility of the semiconductor device.

[0019] To address the aforementioned issues, this disclosure provides a semiconductor device.

[0020] The specific embodiments disclosed herein will now be described in detail with reference to the accompanying drawings.

[0021] Figure 1 A schematic diagram of a semiconductor device according to some embodiments of this disclosure is shown.

[0022] Please see Figure 1 The semiconductor device provided in this disclosure embodiment may include:

[0023] Substrate 1;

[0024] Buffer layer 2 is disposed on substrate 1;

[0025] Channel layer 3 is disposed on buffer layer 2;

[0026] Barrier layer 4 is disposed on channel layer 3;

[0027] Several transition layers 5 are disposed on the barrier layer 4.

[0028] The cap layer 6 is disposed on the transition layer 5;

[0029] Gate 10 is disposed on capping layer 6;

[0030] Source 7 is located on barrier layer 4;

[0031] The drain 8 is disposed on the barrier layer 4 and is disposed on both sides of the gate 10, along with the source 7.

[0032] In the semiconductor device of this disclosed embodiment, each transition layer 5 includes a first P-type doped GaN layer 51 disposed on the barrier layer 4 and a first P-type doped layer 52 disposed on the first P-type doped GaN layer 51.

[0033] That is, if the direction of the substrate pointing to the capping layer 6 is defined as upward, then the substrate 1, buffer layer 2, channel layer 3, barrier layer 4, first P-type doped GaN layer 51, first P-type doped layer 52 (the first P-type doped GaN layer 51 and the first P-type doped layer 52 constitute the transition layer 5) and capping layer 6 are arranged sequentially from bottom to top.

[0034] In this disclosed embodiment, the doping concentration of the first P-type doped GaN layer 51 in the transition layer 5 is configured to decrease from the side closer to the first P-type doped layer 52 to the side closer to the substrate 1, that is, the doping concentration of the first P-type doped GaN layer 51 gradually decreases from top to bottom.

[0035] The semiconductor device disclosed herein has several transition layers, each of which includes a first P-type doped GaN layer disposed on a barrier layer and a first P-type doped layer disposed on the first P-type doped GaN layer. The doping concentration of the first P-type doped GaN layer is configured to decrease from the side closer to the first P-type doped layer to the side closer to the substrate. During the fabrication of the semiconductor device, the first P-type doped GaN layer in the transition layer can effectively block and reduce the diffusion of doped impurities in the P-type gate to the barrier layer, thereby ultimately reducing the on-resistance of the device, improving the conduction performance of the device, and thus improving the problem of decreased mobility in the non-gate region.

[0036] In some embodiments, the first P-type doped GaN layer 51 can be formed based on an undoped intrinsic u-GaN layer. A high-temperature tempering process is used to diffuse the dopant impurities in the heavily doped P-type layer disposed on the intrinsic u-GaN layer into the intrinsic u-GaN layer, thereby forming the first P-type doped GaN layer 51. Further, the process parameters of the high-temperature tempering process can be as follows: a tempering temperature of 650°C to 800°C in a nitrogen atmosphere.

[0037] Corresponding to the first semiconductor device provided in the previous embodiment, this disclosure also provides a second semiconductor device, which may include:

[0038] Substrate;

[0039] A buffer layer is disposed on the substrate;

[0040] The channel layer is positioned on top of the buffer layer;

[0041] A barrier layer, which is placed on top of the channel layer;

[0042] Several prefabricated transition layers are set on the barrier layer.

[0043] A capping layer is installed on the prefabricated transition layer;

[0044] The gate is disposed on the capping layer;

[0045] The source electrode is located on the barrier layer;

[0046] The drain is disposed on the barrier layer, and is disposed on both sides of the gate, respectively, as is the source.

[0047] Compared to the first type of semiconductor device described above, the difference lies in the fact that in the second type of semiconductor device, a pre-fabricated transition layer is disposed above the barrier layer. This pre-fabricated transition layer includes an intrinsic u-GaN layer and a heavily doped P-type layer disposed on the intrinsic u-GaN layer. By processing the second type of semiconductor device through a high-temperature tempering process, the dopant impurities in the heavily doped P-type layer can diffuse to the intrinsic u-GaN layer, thereby forming the first type of semiconductor device described above. It should be noted that, corresponding to the two types of semiconductor devices mentioned above, during the fabrication of the semiconductor device, an intrinsic u-GaN layer and a heavily doped P-type layer are sequentially fabricated on the barrier layer 4. After the above-mentioned high-temperature tempering process, the dopant impurities in the heavily doped P-type layer diffuse to the intrinsic u-GaN layer, so that the undoped intrinsic u-GaN layer forms the first P-type doped GaN layer 51, and the heavily doped P-type layer forms the first P-type doped layer 52.

[0048] In some embodiments, the first P-type doped layer 52 of the first semiconductor device is a heavily Mg-doped AlGaN layer or GaN layer, wherein the Mg atom doping concentration is greater than that in the capping layer 6. Specifically, the heavily doped P-type layer 52 can be a P-AlGaN layer or P-GaN layer with a single Mg atom doping concentration formed using Detal doping technology. After a high-temperature tempering process, the Mg atoms doped in the heavily doped P-type layer diffuse into the intrinsic u-GaN layer, so that the intrinsic u-GaN layer forms the first P-type doped GaN layer 51, and the heavily doped P-type layer forms the first P-type doped layer 52, thereby effectively increasing the hole concentration in the gate region of the semiconductor device, thereby increasing the threshold voltage of the semiconductor device having the above-mentioned transition layer.

[0049] It should be noted that the above example of Mg atoms as dopant is used as an illustration. In practical applications, dopant can be any other atom besides Mg atoms, and is not unique. That is, Mg atoms do not constitute the only limitation on dopant in this disclosure.

[0050] Furthermore, the maximum doping concentration of the first P-type doped GaN layer 51 in the first semiconductor device is less than the doping concentration of the first P-type doped layer 52, and this maximum doping concentration is related to the annealing time of the heat treatment process.

[0051] In some embodiments, the doping concentration of the first p-type doped layer 52 of the first semiconductor device is between 5E+19cm⁻¹. -3Up to 6E+19cm -3 between.

[0052] In this disclosed embodiment, the doping concentration of the first P-type doped layer 52 of the first semiconductor device is greater than the doping concentration of the first P-type doped GaN layer 51.

[0053] Furthermore, the doping concentration of the first p-type doped layer 52 of the first semiconductor device is greater than the doping concentration of the capping layer 6. In some embodiments, the doping concentration of the capping layer 6 may be between 3E+18cm⁻¹. -3 Up to 4.5E+19cm -3 between.

[0054] In practical applications, to ensure that the capping layer can completely deplete the 2DEG in the channel, the barrier layer is often relatively thin. For example, to ensure that the capping layer 6 can completely deplete the 2DEG in the channel, the thickness of the barrier layer 4 can be set between 15 nm and 30 nm. However, this can cause undoped Mg atoms in the P-GaN capping layer to easily form defects, which can then penetrate into the thinner barrier layer, increasing internal electron scattering and leading to a decrease in device mobility.

[0055] The semiconductor device provided in some embodiments of this disclosure has several transition layers. Each transition layer includes a first P-type doped GaN layer disposed on a barrier layer and a first P-type doped layer disposed on the first P-type doped GaN layer. The doping concentration of the first P-type doped GaN layer is configured to decrease from the side closer to the first P-type doped layer to the side closer to the substrate. This transition layer and the capping layer form a P-type gate with an effective high hole concentration, thereby improving the threshold voltage of the device. Simultaneously, the first P-type doped GaN layer in the transition layer can effectively block and reduce the diffusion of doped impurities from the P-type gate to the barrier layer during the semiconductor device fabrication process, ultimately reducing the on-resistance of the device and improving its conduction performance. Furthermore, the first P-type doped layer employs heavy Delta doping technology, which avoids the formation of high-density stacking faults during heavy doping epitaxy, preventing a deterioration in the crystal quality of P-GaN and resulting in poor gate voltage. Therefore, the semiconductor device provided in this disclosure addresses both the requirement of increasing the threshold voltage of the gate region and the problem of decreased mobility in the non-gate region.

[0056] In some embodiments, for example, the thickness of the capping layer 6 is less than or equal to 70 nm; the thickness of the first P-type doped layer 52 may be between 5 nm and 10 nm; and the thickness of the first P-type doped GaN layer 51 may be between 3 nm and 6 nm.

[0057] In this disclosed embodiment, the transition layer 5 between the barrier layer 4 and the capping layer 6 can be one or more. When there are multiple transition layers 5 between the barrier layer 4 and the capping layer 6, the first P-type doped GaN layer 51 and the first P-type doped layer 52 can be alternately disposed between the barrier layer and the capping layer, presenting a periodic arrangement.

[0058] In some embodiments, the thicknesses of each first P-type doped GaN layer 51 and each first P-type doped layer 52 in the plurality of transition layers can be set proportionally. In other embodiments, the first P-type doped GaN layer in the transition layer closest to the substrate is the thickest. Thus, by setting the thickness of the first P-type doped GaN layer in the transition layer closest to the substrate to be relatively the thickest, the penetration of undoped Mg atoms into the thinner barrier layer can be reduced, avoiding a decrease in device mobility due to increased internal electron scattering.

[0059] In this disclosed embodiment, the transition layer 5 and the capping layer 6 constitute a P-type gate, the source 7 and the drain 8 are disposed above the barrier layer 4 in a mutually isolated manner, and are respectively disposed on both sides of the P-type gate, and the gate 10 is disposed on the P-type gate.

[0060] Based on the aforementioned gate structure, after the high-temperature annealing process described above, doped impurities diffuse into the transition layer 5 of the P-type gate. In current P-GaN capping layer technology, it is difficult to achieve a high hole concentration using epitaxially grown P-GaN, which leads to a lower threshold voltage of the semiconductor device. However, in the semiconductor device with the aforementioned gate structure, the hole concentration in the gate region is effectively increased after the high-temperature annealing process, improving the threshold voltage of the semiconductor device. At the same time, the first P-type doped GaN layer 51 can effectively prevent undoped impurities from penetrating into the barrier layer 4, further balancing the mobility of the non-gate region, thereby realizing a semiconductor device with low on-resistance and high threshold voltage.

[0061] The epitaxial structure of any of the semiconductor devices mentioned above will be further explained below.

[0062] In some embodiments, the barrier layer 4 may be an AlGaN barrier layer grown using a metal-organic chemical vapor deposition (MOCVD) process, wherein the Al content in the AlGaN is 20% to 30% by mass.

[0063] In some embodiments, the channel layer 3 is a GaN channel layer further grown on the buffer layer using MOCVD process, and its thickness is between 280nm and 320nm. In practical applications, 300nm can be selected.

[0064] In some embodiments, the buffer layer 2 is a semi-insulating GaN high-resistivity buffer layer formed by unintentional doping growth using MOCVD process, with a thickness between 4 μm and 5 μm and a resistivity of 10⁻⁶. 8 ohm or above.

[0065] In some embodiments, the substrate 1 can be made of any of Si, SiC and GaN, and the size of the substrate 1 can be between 2 inches and 8 inches.

[0066] Furthermore, the semiconductor device proposed in any of the above embodiments may further include: a passivation layer 9 disposed on the barrier layer 4;

[0067] The passivation layer 9 is located between the source 7 and the gate 10, and between the drain 8 and the gate 10. It can be understood that the passivation layer 9 fills the gaps between the source 7, the drain 8 and the P-type gate, and is used to protect the surface of the epitaxial structure of the semiconductor device.

[0068] In some embodiments, the passivation layer 9 may be prepared using AlN or SiO2.

[0069] In this embodiment, the semiconductor device covers the previously exposed barrier layer surface by a passivation layer disposed between the source and the gate, and between the drain and the gate, thereby protecting the surface of the epitaxial structure of the semiconductor device and improving the stability and reliability of the semiconductor device performance.

[0070] The following is combined with Figure 2 The fabrication method of the semiconductor device shown in the above embodiments will be described.

[0071] Please combine Figure 1 and Figure 5 , and see Figure 2 The method for fabricating a semiconductor device proposed in the embodiments disclosed herein may include:

[0072] In step 201, a semiconductor epitaxial structure is provided. The semiconductor epitaxial structure includes: a substrate 1, a buffer layer 2 disposed on the substrate 1, a channel layer 3 disposed on the buffer layer 2, and a barrier layer 4 disposed on the channel layer 3.

[0073] In step 202, a plurality of pre-fabricated transition layers 11 are formed on the semiconductor epitaxial structure. Each of the pre-fabricated transition layers 11 includes an intrinsic u-GaN layer 111 formed on the barrier layer 4 and a heavily doped p-type layer 112 formed on the intrinsic u-GaN layer 111.

[0074] For example, step 202 above may include: forming an intrinsic u-GaN layer 111 on the barrier layer 4, and then forming a heavily doped P-type layer 112 on the intrinsic u-GaN layer 111 using heavy Detal doping technology to form the prefabricated transition layer.

[0075] Furthermore, step 202 may also include: repeatedly preparing an intrinsic u-GaN layer 111 and a heavily doped P-type layer 112 on the barrier layer 4 to form a multilayer prefabricated transition layer 11.

[0076] The intrinsic u-GaN111 layer is fabricated using undoped GaN material, with a thickness ranging from 3 nm to 6 nm and a doping concentration of 0. The heavily doped p-type layer 112 can be fabricated using AlGaN or GaN material, with a thickness ranging from 5 nm to 10 nm and a doping concentration ranging from 5.5E+19 cm⁻¹. -3 Up to 8E+19cm -3 In between. It should be added that, taking Mg doping as an example, the heavily doped P-type layer 112 can be an AlGaN layer with a single Mg doping concentration made by using Delta doping technology, or a P-GaN layer with a single Mg doping concentration.

[0077] In step 203, a rudimentary capping layer 61 is formed on the pre-fabricated transition layer 11. The doping concentration of this rudimentary capping layer 61 is lower than the doping concentration of the heavily doped p-type layer 112. For example, the doping concentration of the rudimentary capping layer 61 can be between 3E+18cm⁻¹. -3 Up to 5.5E+19cm -3 between.

[0078] For example, the thickness of the original capping layer 61 prepared in step 203 above is less than or equal to 70 nm.

[0079] In step 204, the original capping layer 61 and the prefabricated transition layer 11 are etched.

[0080] For example, step 204 above may include: etching away the original capping layer 61 and the prefabricated transition layer 11 except for the gate region by inductively coupled plasma (ICP), and stopping the etching at the surface of the barrier layer.

[0081] In step 204, the pre-fabricated transition layer 11 and the original capping layer 61 in a portion of the area above the barrier layer can be etched away, leaving the pre-fabricated transition layer 11 and the original capping layer 61 in the middle region of the barrier layer. The remaining pre-fabricated transition layer 11 and the original capping layer 61 form part of the P-type gate. In the subsequent step 205, when performing high-temperature tempering, the P-type gate can be subjected to high-temperature tempering treatment to allow the dopant impurities in the heavily doped P-type layer 112 to diffuse to the intrinsic u-GaN layer 111, so that the heavily doped P-type layer 112 is configured to form the first P-type doped layer 52 as described in the above embodiment, and the intrinsic u-GaN layer 111 is configured to form the first P-type doped GaN layer 51 as described in the above embodiment. It should be added that, due to the high-temperature tempering, the doping concentration in the original capping layer 61 is also reduced from between 3E+18cm⁻¹. -3 Up to 5.5E+19cm -3 Between these values, the doping concentration becomes between 3E+18cm⁻¹. -3 Up to 5.5E+19cm -3 The capping layer 6 is as described above. Thus, by fabricating the intrinsic u-GaN layer 111 in the pre-fabricated transition layer 11, the doping concentration in the semiconductor layers above the intrinsic u-GaN layer 111 can be reduced. In particular, undoped impurities in the semiconductor layers above the intrinsic u-GaN layer 111 diffuse into the barrier layer 4, improving the problem of decreased mobility in the non-gate region, thereby reducing the on-resistance of the device and improving its conduction performance.

[0082] The specific steps of the etching operation are as follows:

[0083] A mask is photolithographically fabricated in a portion of the original capping layer 61, wherein the mask is made of SiN. X Or SiO2 deposition; using an etching process to remove the prefabricated transition layer 11 and the original capping layer 61 in the area not covered by the mask, the gate region can be defined based on the remaining prefabricated transition layer 11 and the original capping layer 61. This etching process can be carried out by inductively coupled plasma (ICP) etching to remove the transition layer and capping layer other than the gate region, and the etching stops at the surface of the barrier layer 4.

[0084] In step 205, the semiconductor device is subjected to high-temperature tempering after etching the original capping layer 61 and the pre-fabricated transition layer 11. Step 205 allows the doped impurities in the heavily doped P-type layer 111 to diffuse to the intrinsic u-GaN layer 112, thereby forming the pre-fabricated transition layer 11 into the transition layer 5 described in the above embodiment.

[0085] For example, step 205 may include: performing high-temperature tempering after etching the original capping layer 61 and the prefabricated transition layer 11, so that the doped impurities in the heavily doped P-type layer 112 diffuse to the intrinsic u-GaN layer 111, so that the heavily doped P-type layer 112 is formed into the first P-type doped layer 51; and performing high-temperature tempering after etching the original capping layer 61 and the prefabricated transition layer 11, so that the doped impurities in the heavily doped P-type layer 112 diffuse to the intrinsic u-GaN layer 111, so that the intrinsic u-GaN layer 111 is formed into the first P-type doped GaN layer 51.

[0086] The formation process of the first P-type doped layer is as follows:

[0087] After etching the original capping layer 61 and the pre-fabricated transition layer 11, a high-temperature tempering process is performed to reduce the doping concentration of the heavily doped p-type layer 112 from 5.5E+19cm⁻¹. -3 Up to 8E+19cm -3 Reduced to 5E+19cm -3 Up to 6E+19cm -3 To form the first P-type doped layer 51.

[0088] The formation process of the first P-type doped GaN layer 51 is as follows:

[0089] After etching the original capping layer 61 and the pre-fabricated transition layer 11, a high-temperature tempering process is performed to increase the doping concentration of the intrinsic u-GaN layer 111, thereby forming the first P-type doped GaN layer 51.

[0090] In some embodiments, the high-temperature tempering in step 203 refers to tempering in a nitrogen atmosphere at a tempering temperature of 650°C to 800°C.

[0091] After high-temperature tempering, the doping concentration of the intrinsic u-GaN layer 111 increases, forming the first P-type doped GaN layer 51. The doping concentration of the first P-type doped GaN layer 51 gradually decreases from top to bottom, and the maximum doping concentration is related to the tempering time.

[0092] The semiconductor device fabrication method provided in this embodiment can fabricate semiconductor devices with a transition layer. Combined with a high-temperature tempering process, the dopant impurities in the heavily doped P-type layer of the pre-fabricated transition layer diffuse further into the intrinsic u-GaN layer, forming the transition layer. This intrinsic u-GaN layer (which forms the first P-type doped GaN layer after high-temperature tempering) effectively prevents the diffusion of dopant impurities from the capping layer to the barrier layer during epitaxial fabrication, ensuring the device's mobility. Furthermore, this method can be easily implemented through epitaxial fabrication and etching processes, and it exhibits high repeatability and controllability, making it suitable for large-scale production of semiconductor devices.

[0093] Furthermore, the semiconductor device fabricated by the method provided in this embodiment has a transition layer that effectively increases the hole concentration in the gate region, thereby increasing the threshold voltage of the device. Simultaneously, the intrinsic u-GaN layer (formed as a first P-type doped GaN layer after high-temperature tempering) effectively prevents doped impurities in the capping layer from diffusing to the barrier layer during epitaxial fabrication, ensuring the device's mobility. In other words, the semiconductor device fabrication method provided in this embodiment can obtain a semiconductor device that balances threshold voltage and mobility.

[0094] Furthermore, prior to high-temperature tempering, the method for fabricating the semiconductor device may further include the following steps (not shown in the figure):

[0095] A passivation layer is deposited on the exposed surface of the barrier layer;

[0096] The passivation layer is etched to expose the gate region, source region, and drain region to fabricate the gate, source, and drain, respectively.

[0097] In the semiconductor device fabrication method disclosed in this embodiment, after forming the P-type gate and before forming the gate, a passivation layer is deposited on the exposed barrier layer and the surface of the P-type gate. The material of the passivation layer can be AlN or SiO2. After forming the passivation layer, the passivation layer in a portion above the barrier layer and the passivation layer on the upper surface of the P-type gate need to be removed. The area where the passivation layer is removed is used to fabricate the gate, source, and drain. Specifically, the upper surface of the P-type gate is used to fabricate the gate, and the area on the barrier layer where the passivation layer is removed is used to fabricate the source and drain.

[0098] Furthermore, Figure 3 Another schematic flow diagram illustrating a method for fabricating a semiconductor device according to some embodiments of this disclosure is shown. See also Figure 3 One embodiment of this disclosure provides a method for fabricating a semiconductor device, which involves preparing a passivation layer to protect the surface of the epitaxial structure of the semiconductor device, and may include the following steps:

[0099] In step 301, a semiconductor epitaxial structure is provided;

[0100] In step 302, several prefabricated transition layers are formed on the semiconductor epitaxial structure;

[0101] In step 303, an original capping layer is formed on the prefabricated transition layer;

[0102] In step 304, the original capping layer and the prefabricated transition layer are etched;

[0103] In step 305, a passivation layer is deposited on the exposed barrier layer and the surface of the P-type gate by vapor deposition;

[0104] In step 306, the passivation layer in a portion of the area above the barrier layer and the passivation layer on the upper surface of the P-type gate are etched away.

[0105] In step 307, a gate is formed on the upper surface of the P-type gate;

[0106] In step 308, mutually isolated source and drain electrodes are formed on the upper surface of the barrier layer;

[0107] In step 309, the semiconductor device is subjected to high-temperature tempering to allow the doped impurities in the heavily doped P-type layer to diffuse into the intrinsic u-GaN layer, so that the pre-fabricated transition layer is formed as a transition layer.

[0108] It should be noted that this disclosure does not have strict requirements on the fabrication order of the gate, source, and drain. In practical applications, the gate, source, and drain can be formed based on any fabrication order, and no unique limitation is made here.

[0109] For details on the specific operation methods of each step, please refer to the semiconductor device fabrication method described above, which will not be elaborated here.

[0110] The semiconductor device fabrication method provided in this embodiment forms a protective dielectric film on the surface of the semiconductor device by evaporating a passivation layer on the exposed barrier layer and the surface of the P-type gate, thereby improving the impact of surface effects on the device's operational stability and enhancing the reliability of the semiconductor device.

[0111] Figure 4 A schematic flowchart illustrating a method for fabricating semiconductor epitaxial structures according to some embodiments of this disclosure is shown.

[0112] See Figure 4 In some embodiments disclosed herein, the method for preparing the semiconductor epitaxial structure in step 201 or step 301 may include:

[0113] In step 401, a substrate is provided.

[0114] In step 401 above, the substrate material can be any of Si, SiC and GaN, and the size of the substrate can be between 2 inches and 8 inches.

[0115] In step 402, a buffer layer is formed on the substrate.

[0116] For example, step 402 above may include: epitaxially growing an unintentionally doped semi-insulating GaN high-resistivity buffer layer on a substrate using an MOCVD process. Further, the resistivity of the GaN high-resistivity buffer layer is 10⁻⁶. 8 ohm or above.

[0117] The thickness of the buffer layer prepared in step 402 above can be between 4 μm and 5 μm.

[0118] In step 403, a channel layer is formed on the buffer layer.

[0119] For example, step 403 above may include: further growing a GaN channel layer on the GaN high-resistivity buffer layer using an MOCVD process.

[0120] The thickness of the channel layer prepared in step 403 above can be between 280 nm and 320 nm.

[0121] In step 404, a barrier layer is formed on the channel layer.

[0122] For example, step 404 may include: growing an AlGaN barrier layer on the GaN channel layer using an MOCVD process, wherein the mass percentage of Al component in the AlGaN used to prepare the AlGaN barrier layer may be between 20% and 30%.

[0123] The thickness of the barrier layer prepared in step 404 above can be between 15 nm and 30 nm.

[0124] The above-described method for preparing semiconductor epitaxial structures can yield structures such as... Figure 5 The epitaxial structure of the semiconductor device is shown.

[0125] like Figure 5 As shown, the epitaxial structure of a semiconductor device may include:

[0126] Substrate 1;

[0127] A buffer layer 2 is disposed on substrate 1;

[0128] A channel layer 3 is disposed on the buffer layer 2;

[0129] A barrier layer 4 is set on the channel layer 3.

[0130] Furthermore, in some embodiments, the epitaxial structure of the semiconductor device may further include a pre-transition layer 11 disposed on the barrier layer 4, wherein the pre-transition layer 11 includes an intrinsic u-GaN layer 111 and a heavily doped P-type layer 112 disposed on the intrinsic u-GaN layer 111. Corresponding to the epitaxial structure of this semiconductor device, the method for fabricating the semiconductor epitaxial structure may further include: forming an intrinsic u-GaN layer on the barrier layer, and forming a heavily doped P-type layer on the intrinsic u-GaN layer using heavy detal doping technology.

[0131] Furthermore, in some embodiments, the epitaxial structure of the semiconductor device may further include: a primary capping layer 61 disposed on the heavily doped P-type layer 112. Corresponding to the epitaxial structure of the semiconductor device, the method for fabricating the semiconductor epitaxial structure may further include: forming the primary capping layer 61 on the heavily doped P-type layer 112.

[0132] It should be noted that the division of the epitaxial structure of the semiconductor device in the embodiments of this disclosure is merely an example and does not constitute the sole limitation of this disclosure. That is to say, the epitaxial structure of the semiconductor device in this disclosure may include, but is not limited to: substrate 1, buffer layer 2, channel layer 3, and barrier layer 4. Furthermore, the epitaxial structure of the semiconductor device in this disclosure may also include: prefabricated transition layer 11 and original capping layer 61.

[0133] In some embodiments disclosed herein, after the epitaxial structure of the semiconductor device is prepared, a high-temperature tempering process can be performed on the epitaxial structure of the semiconductor device to form the pre-fabricated transition layer 11 as the transition layer 5. That is, in some embodiments, such as Figure 5 As shown, the epitaxial structure of the semiconductor device disclosed herein may include: a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a pre-fabricated transition layer 11, and an original capping layer 6.

[0134] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of the systems and methods according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0135] While numerous embodiments of this disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will occur to those skilled in the art without departing from the spirit and intent of this disclosure. It should be understood that various alternatives to the embodiments of this disclosure described herein may be employed in the practice of this disclosure. The appended claims are intended to define the scope of this disclosure and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate (1); A buffer layer (2) is disposed on the substrate (1); The channel layer (3) is disposed on the buffer layer (2); A barrier layer (4) is disposed on the channel layer (3); A plurality of transition layers (5) are disposed on a barrier layer (4), wherein each of the transition layers (5) includes a first P-type doped GaN layer (51) disposed on the barrier layer (4) and a first P-type doped layer (52) disposed on the first P-type doped GaN layer (51); among the plurality of transition layers, the first P-type doped GaN layer in the transition layer closest to the substrate has the thickest thickness; A capping layer (6) is disposed on the transition layer (5); A gate (10) is disposed on the capping layer (6); The source electrode (7) is located on the barrier layer (4); The drain (8) is disposed on the barrier layer (4) and is disposed on both sides of the gate (10) respectively, along with the source (7); The doping concentration of the first P-type doped GaN layer (51) is configured to decrease from the side closer to the first P-type doped layer (52) to the side closer to the substrate (1).

2. The semiconductor device according to claim 1, characterized in that, The first P-type doped layer (52) has a doping concentration between 5E+19 cm -3 and 6E+19 cm -3 between 5E+19 cm -3 and 6E+19 cm -3 between 5E+19 cm -3 and 6E+19 cm -3 3. The semiconductor device according to claim 1, characterized in that, The doping concentration of the first P-type doped layer (52) is greater than the doping concentration of the first P-type doped GaN layer (51).

4. The semiconductor device according to claim 1, characterized in that, The doping concentration of the first P-type doped layer (52) is greater than that of the capping layer (6).

5. The semiconductor device according to claim 4, characterized in that, The cap layer (6) has a doping concentration between 3E+18 cm -3 and 4.5E+19 cm -3 between 3E+18 cm -3 and 4.5E+19 cm -3 6. The semiconductor device according to claim 1, characterized in that, The thickness of the first P-type doped GaN layer (51) is between 3 nm and 6 nm.

7. The semiconductor device according to claim 1, characterized in that, The thickness of the first P-type doped layer (52) is between 5 nm and 10 nm.

8. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: A passivation layer (9) is disposed on the barrier layer (4), the passivation layer (9) being located between the source (7) and the gate (10), and between the drain (8) and the gate (10).

9. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor epitaxial structure is provided, wherein the semiconductor epitaxial structure includes: a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, and a barrier layer disposed on the channel layer; A plurality of pre-fabricated transition layers are disposed on the semiconductor epitaxial structure, wherein each of the pre-fabricated transition layers includes an intrinsic u-GaN layer disposed on the barrier layer and a heavily doped P-type layer disposed on the intrinsic u-GaN layer; An original capping layer is formed on the prefabricated transition layer; The original capping layer and the pre-fabricated transition layer are etched, and the semiconductor device is subjected to high-temperature tempering after etching the original capping layer and the pre-fabricated transition layer to form the pre-fabricated transition layer as a transition layer; wherein, the first P-type doped layer in the transition layer is formed by the heavily doped P-type layer, and the first P-type doped GaN layer in the transition layer is formed by the intrinsic u-GaN layer; the doping concentration of the first P-type doped GaN layer is configured to decrease from the side closer to the first P-type doped layer to the side closer to the substrate.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, After etching the original capping layer and the pre-fabricated transition layer, the semiconductor device is subjected to high-temperature tempering to allow the pre-fabricated transition layer to form a transition layer. After etching the original capping layer and the pre-fabricated transition layer, a high-temperature tempering process is performed to form the heavily doped P-type layer as the first P-type doped layer. This includes: performing a high-temperature tempering process after etching the original capping layer and the pre-fabricated transition layer to reduce the doping concentration of the heavily doped P-type layer from 5.5E+19cm⁻¹. -3 Up to 8E+19cm -3 Reduced to 5E+19cm -3 Up to 6E+19cm -3 To form the first P-type doped layer; The process of performing high-temperature tempering after etching the original capping layer and the prefabricated transition layer to form the intrinsic u-GaN layer into the first P-type doped GaN layer includes: performing high-temperature tempering after etching the original capping layer and the prefabricated transition layer to increase the doping concentration of the intrinsic u-GaN layer to form the first P-type doped GaN layer.

11. The method for fabricating a semiconductor device according to claim 9, characterized in that, In the provision of several prefabricated transition layers on the semiconductor epitaxial structure, a heavily doped P-type layer is provided on the intrinsic u-GaN layer, including: The heavily doped P-type layer is formed on the intrinsic u-GaN layer using heavy detal doping technology.

12. The method for fabricating a semiconductor device according to claim 9, characterized in that, The etching of the original capping layer and the prefabricated transition layer includes: The original capping layer and the prefabricated transition layer, excluding the gate region, are etched away by inductively coupled plasma etching, and etching is stopped on the surface of the barrier layer.

13. The method for fabricating a semiconductor device according to claim 10, characterized in that, Before performing high-temperature tempering on the semiconductor device, the method further includes: A passivation layer is deposited on the exposed surface of the barrier layer; The passivation layer is etched to expose the gate region, source region, and drain region to fabricate the gate, source, and drain, respectively.

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