Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate includes: a base substrate having a first display area and a second display area, a plurality of second-region light-emitting elements located in the second display area, and a plurality of second-type pixel circuits located in the first display area. The first display area is located at least on one side of the second display area. The plurality of second-type pixel circuits include a plurality of pixel circuits of a first structure and a plurality of pixel circuits of a second structure. At least one pixel circuit among the plurality of pixel circuits of the first structure is connected to at least one light-emitting element among the plurality of second-region light-emitting elements through a first group of conductive lines. At least one pixel circuit among the plurality of pixel circuits of the second structure is connected to at least one light-emitting element among the plurality of second-region light-emitting elements through a second group of conductive lines. The length of the second group of conductive lines is greater than the length of the first group of conductive lines.

Description

Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is an active light-emitting display device with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED as the light-emitting device and thin film transistor (TFT) for signal control have become the mainstream products in the current display field.

[0003] The under-screen camera technology is a new technology proposed to increase the screen-to-body ratio of display devices. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide a display substrate and a method for manufacturing the same, and a display device.

[0006] On the one hand, an embodiment of the present disclosure provides a display substrate, comprising: a base substrate having a first display area and a second display area, a plurality of second-region light-emitting elements located in the second display area, and a plurality of second-type pixel circuits located in the first display area. The first display area is located on at least one side of the second display area. The plurality of second-type pixel circuits include a plurality of pixel circuits of a first structure and a plurality of pixel circuits of a second structure. At least one pixel circuit among the plurality of pixel circuits of the first structure is connected to at least one light-emitting element among the plurality of second-region light-emitting elements through a first group of conductive lines. At least one pixel circuit among the plurality of pixel circuits of the second structure is connected to at least one light-emitting element among the plurality of second-region light-emitting elements through a second group of conductive lines. The length of the second group of conductive lines is greater than the length of the first group of conductive lines.

[0007] In some exemplary embodiments, the pixel circuit of the first structure is connected to a first initial signal line, and the pixel circuit of the second structure is connected to a first initial signal line and a second initial signal line; the first initial signal line and the second initial signal line provide different initial signals.

[0008] In some exemplary embodiments, the display substrate further includes: a plurality of first-region light-emitting elements and a plurality of first-type pixel circuits located in the first display area. At least one of the plurality of first-type pixel circuits is connected to at least one of the plurality of first-region light-emitting elements, and the orthographic projection of the at least one first-type pixel circuit on the substrate at least partially overlaps with the orthographic projection of the at least one first-region light-emitting element on the substrate. The plurality of first-type pixel circuits are all pixel circuits of the first structure.

[0009] In some exemplary embodiments, the pixel circuit of the first structure includes: a driving transistor, a first reset transistor, and a second reset transistor. The gate of the first reset transistor is connected to the first reset control line, the first electrode of the first reset transistor is connected to the gate of the driving transistor, and the second electrode of the first reset transistor is connected to the first initial signal line. The gate of the second reset transistor is connected to the second reset control line, the first electrode of the second reset transistor is connected to the first electrode of the light emitting element, and the second electrode of the second reset transistor is connected to the first initial signal line.

[0010] In some exemplary embodiments, the pixel circuit of the second structure includes: a driving transistor, a first reset transistor, and a second reset transistor. The gate of the first reset transistor is connected to the first reset control line, the first electrode of the first reset transistor is connected to the gate of the driving transistor, and the second electrode of the first reset transistor is connected to the first initial signal line. The gate of the second reset transistor is connected to the second reset control line, the first electrode of the second reset transistor is connected to the first electrode of the light-emitting element, and the second electrode of the second reset transistor is connected to the second initial signal line. The second initial signal provided by the second initial signal line is different from the first initial signal provided by the first initial signal line.

[0011] In some exemplary embodiments, the first initial signal provided by the first initial signal line is a constant voltage signal.

[0012] In some exemplary embodiments, the second initial signal provided by the second initial signal line is a constant voltage signal, and the second initial signal is greater than the first initial signal provided by the first initial signal line.

[0013] In some exemplary embodiments, the magnitude of the second initial signal provided by the second initial signal line connected to the pixel circuit of the second structure is proportional to the length of the second group of conductive lines connected to the pixel circuit of the second structure.

[0014] In some exemplary embodiments, the pixel circuit of the first structure or the pixel circuit of the second structure further includes: a data writing transistor, a threshold compensation transistor, a first light emission control transistor, and a second light emission control transistor. The gate of the data writing transistor is connected to the scan line, the first electrode of the data writing transistor is connected to the data line, and the second electrode of the data writing transistor is connected to the first electrode of the driving transistor. The gate of the threshold compensation transistor is connected to the scan line, the first electrode of the threshold compensation transistor is connected to the gate of the driving transistor, and the second electrode of the threshold compensation transistor is connected to the second electrode of the driving transistor. The gate of the first light emission control transistor is connected to the light emission control line, the first electrode of the first light emission control transistor is connected to the first power line, and the second electrode of the first light emission control transistor is connected to the first electrode of the driving transistor. The gate of the second light emission control transistor is connected to the light emission control line, the first electrode of the second light emission control transistor is connected to the second electrode of the driving transistor, and the second electrode of the second light emission control transistor is connected to the first electrode of the light emitting element.

[0015] In some exemplary embodiments, in a plane perpendicular to the display substrate, the display substrate includes at least: a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer disposed on a base substrate. The semiconductor layer includes at least: an active layer of a plurality of transistors. The first conductive layer includes at least: gate electrodes of a plurality of transistors and a first electrode of a storage capacitor, a scan line, a light emitting control line, a first reset control line, and a second reset control line. The second conductive layer includes at least: a second electrode of a storage capacitor, a first initial signal line, and a second initial signal line. The third conductive layer includes at least: a first electrode and a second electrode of a plurality of transistors, a first power line, and a data line.

[0016] In some exemplary embodiments, the active layers of the first reset transistor and the second reset transistor of the pixel circuit of the first structure are an integrated structure; the second reset transistor of the pixel circuit of the nth row of the first structure and the active layer of the first reset transistor of the pixel circuit of the n+1th row are an integrated structure, and n is a positive integer.

[0017] In some exemplary embodiments, the active layers of the first reset transistor and the second reset transistor of the pixel circuit of the second structure are an integrated structure; the active layer of the second reset transistor of the pixel circuit of the nth row of the second structure is not connected to the active layer of the first reset transistor of the pixel circuit of the n+1th row, and n is a positive integer.

[0018] In some exemplary embodiments, the third conductive layer includes: a second electrode of the second reset transistor of the pixel circuit of the second structure, and a second electrode of the second reset transistor of the pixel circuit of the first structure. The second electrode of the second reset transistor of the pixel circuit of the second structure is connected to the second initial signal line through a via. The second electrode of the second reset transistor of the pixel circuit of the first structure is not connected to the second initial signal line.

[0019] In some exemplary embodiments, the first group of conductive lines and the second group of conductive lines are made of transparent conductive materials.

[0020] In some exemplary embodiments, a plurality of second-type pixel circuits are spaced apart between a plurality of first-type pixel circuits.

[0021] In some exemplary embodiments, among the plurality of first-type pixel circuits and the plurality of second-type pixel circuits, a size of any pixel circuit in the first direction is smaller than a size of the first-region light-emitting element in the first direction.

[0022] In some exemplary embodiments, the plurality of second-region light-emitting elements include a plurality of groups of second-region light-emitting elements, the second-region light-emitting elements in each group are arranged along the first direction, and the plurality of groups of second-region light-emitting elements are arranged along the second direction. The plurality of second-type pixel circuits include a plurality of groups of second-type pixel circuits, the second-type pixel circuits in each group are arranged along the first direction, and the plurality of second-type pixel circuits are arranged along the second direction. The plurality of second-region light-emitting elements at least include: a plurality of first light-emitting elements, a plurality of second light-emitting elements, and a plurality of third light-emitting elements. The plurality of second-type pixel circuits include: a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits; a plurality of first light-emitting elements are connected to a plurality of first pixel circuits, a plurality of second light-emitting elements are connected to a plurality of second pixel circuits, and a plurality of third light-emitting elements are connected to a plurality of third pixel circuits. In at least one group of second-region light-emitting elements and at least one group of second-type pixel circuits, a plurality of first pixel circuits connected to a plurality of first light-emitting elements are closer to the second display area than each of a plurality of second pixel circuits connected to a plurality of second light-emitting elements, and are closer to the second display area than each of a plurality of third pixel circuits connected to a plurality of third light-emitting elements.

[0023] In some exemplary embodiments, the second pixel circuit connected to the second light-emitting element through the second group of conductive lines is a pixel circuit of the second structure, the third pixel circuit connected to the third light-emitting element through the second group of conductive lines is a pixel circuit of the second structure, the first pixel circuit connected to the first light-emitting element through the first group of conductive lines is a pixel circuit of the first structure, and the first pixel circuit connected to the first light-emitting element through the second group of conductive lines is a pixel circuit of the second structure.

[0024] In some exemplary embodiments, the first light emitting element is configured to emit green light, one of the second light emitting element and the third light emitting element is configured to emit red light, and the other of the second light emitting element and the third light emitting element is configured to emit blue light.

[0025] In some exemplary embodiments, the length of the first group of conductive lines is less than a length delimiting value, and the length of the second group of conductive lines is greater than or equal to the length delimiting value. The ratio of the length delimiting value to the maximum length of the second group of conductive lines is about 0.25 to 0.35.

[0026] On the other hand, an embodiment of the present disclosure provides a display device, including the display substrate as described above.

[0027] In some exemplary embodiments, the display device further includes: a photosensor located at one side of the display substrate, wherein an orthographic projection of the photosensor on the display substrate overlaps with the second display area of ​​the display substrate.

[0028] On the other hand, an embodiment of the present disclosure provides a method for preparing a display substrate, comprising: forming a plurality of second-type pixel circuits in a first display area of ​​a base substrate, forming a plurality of second-region light-emitting elements in a second display area, and the first display area is located on at least one side of the second display area. The plurality of second-type pixel circuits include a plurality of pixel circuits of a first structure and a plurality of pixel circuits of a second structure; at least one pixel circuit in the plurality of pixel circuits of the first structure is connected to at least one light-emitting element in the plurality of second-region light-emitting elements through a first group of conductive lines. At least one pixel circuit in the plurality of pixel circuits of the second structure is connected to at least one light-emitting element in the plurality of second-region light-emitting elements through a second group of conductive lines. The length of the second group of conductive lines is greater than the length of the first group of conductive lines.

[0029] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shape and size of one or more components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0031] Figure 1A is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0032] Figure 1B is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0033] Figure 2 is a schematic structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0034] Figure 3 is another structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0035] 4A to 4F is a partial plan view of a display substrate according to at least one embodiment of the present disclosure;

[0036] Figure 5A A partial schematic diagram of a row of light-emitting elements and a second type pixel circuit connected thereto located in a second display area of ​​a display substrate of at least one embodiment of the present disclosure;

[0037] Figure 5B A schematic diagram of the capacitance of light-emitting elements emitting light of different colors in the same row of light-emitting elements in the second display area of ​​a display substrate of at least one embodiment of the present disclosure;

[0038] Fig. 6A is a schematic diagram of a pixel circuit of a first structure according to at least one embodiment of the present disclosure;

[0039] Figure 6B is a schematic diagram of a pixel circuit of a second structure according to at least one embodiment of the present disclosure;

[0040] Figure 6C The working timing diagram of the pixel circuit of the first structure and the pixel circuit of the second structure of at least one embodiment of the present disclosure;

[0041] Fig. 7A A schematic plan view of a pixel circuit of a first structure according to at least one embodiment of the present disclosure;

[0042] Figure 7B for Fig. 7A Schematic diagram of the local section along the PP direction;

[0043] Figure 7C A schematic diagram of a pixel circuit of a first structure after forming a semiconductor layer according to at least one embodiment of the present disclosure;

[0044] Fig.7D A schematic diagram of a pixel circuit of a first structure after forming a first conductive layer according to at least one embodiment of the present disclosure;

[0045] Fig. 7E A schematic diagram of a pixel circuit of a first structure after forming a second conductive layer according to at least one embodiment of the present disclosure;

[0046] Figure 7F A schematic diagram of a pixel circuit of a first structure after forming a fourth insulating layer according to at least one embodiment of the present disclosure;

[0047] Figure 7G A schematic diagram of a pixel circuit of a first structure after forming a third conductive layer according to at least one embodiment of the present disclosure;

[0048] Figure 7H A schematic diagram of a pixel circuit of a first structure after a fifth insulating layer is formed according to at least one embodiment of the present disclosure;

[0049] Fig.7I A schematic diagram of a pixel circuit of a first structure after forming a fourth conductive layer according to at least one embodiment of the present disclosure;

[0050] Fig. 8A A schematic plan view of a pixel circuit of a second structure according to at least one embodiment of the present disclosure;

[0051] Figure 8B for Fig. 8A Schematic diagram of the local section along the QQ direction;

[0052] Figure 8C A schematic diagram of a pixel circuit of a second structure after forming a semiconductor layer according to at least one embodiment of the present disclosure;

[0053] Fig.8D A schematic diagram of a pixel circuit of a second structure after forming a first conductive layer according to at least one embodiment of the present disclosure;

[0054] Fig. 8E A schematic diagram of a pixel circuit of a second structure after forming a second conductive layer according to at least one embodiment of the present disclosure;

[0055] Figure 8F A schematic diagram of a pixel circuit of a second structure after forming a fourth insulating layer according to at least one embodiment of the present disclosure;

[0056] Figure 8G A schematic diagram of a pixel circuit of a second structure after forming a third conductive layer according to at least one embodiment of the present disclosure;

[0057] Figure 8H A schematic diagram of a pixel circuit of a second structure after forming a fifth insulating layer according to at least one embodiment of the present disclosure;

[0058] Fig.8I A schematic diagram of a pixel circuit of a second structure after forming a fourth conductive layer according to at least one embodiment of the present disclosure;

[0059] Fig. 9 Another partial schematic diagram of a row of light-emitting elements and a second type pixel circuit connected thereto located in a second display area of ​​a display substrate of at least one embodiment of the present disclosure;

[0060] Fig.10Another partial schematic diagram of a row of light-emitting elements and a second type pixel circuit connected thereto located in a second display area of ​​a display substrate of at least one embodiment of the present disclosure;

[0061] Fig.11 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0062] Fig.12 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0063] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0064] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of one or more components in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0065] The ordinal numbers such as "first", "second", and "third" in this specification are provided to avoid confusion of constituent elements, and are not intended to limit the quantity. The "plurality" in this disclosure means two or more.

[0066] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the orientation of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the circumstances.

[0067] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this disclosure can be understood according to the circumstances.

[0068] In this specification, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. A transistor has a channel region between a drain (drain electrode terminal, a drain region, or a drain electrode) and a source (source electrode terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source. In this specification, a channel region refers to a region where current mainly flows.

[0069] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0070] In this specification, "connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having multiple functions.

[0071] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0072] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0073] With the development of display technology, the existing notch screen or water drop screen design is gradually unable to meet the user's demand for a high screen-to-body ratio of display devices, and a series of display devices with a light-transmitting display area have emerged. In this type of display device, hardware such as light sensors (such as cameras) can be set in the light-transmitting display area. Since there is no need to punch holes, a true full screen becomes possible while ensuring the practicality of the display device.

[0074] The embodiment of the present disclosure provides a display substrate, comprising: a base substrate having a first display area and a second display area, a plurality of second-region light-emitting elements located in the second display area, and a plurality of second-type pixel circuits located in the first display area. The first display area is located on at least one side of the second display area. The plurality of second-type pixel circuits include a plurality of pixel circuits of a first structure and a plurality of pixel circuits of a second structure. At least one pixel circuit among the plurality of pixel circuits of the first structure is connected to at least one light-emitting element among the plurality of second-region light-emitting elements through a first group of conductive lines. At least one pixel circuit among the plurality of pixel circuits of the second structure is connected to at least one light-emitting element among the plurality of second-region light-emitting elements through a second group of conductive lines. The length of the second group of conductive lines is greater than the length of the first group of conductive lines.

[0075] In some exemplary embodiments, the first display area may be a non-light-transmitting display area, and the second display area may be a light-transmitting display area. The pixel circuit driving the light-emitting element in the second display area is arranged in the first display area instead of in the second display area, so as to ensure a better light transmittance of the second display area.

[0076] The display substrate provided by the embodiment of the present disclosure can reduce or eliminate the display defects caused by the difference in the length of the conductive line by adjusting the structure of the second type pixel circuit. That is, when designing the second type pixel circuit connected to the second area light-emitting element, the length of the conductive line connecting the second area light-emitting element and the second type pixel circuit is considered.

[0077] In some exemplary embodiments, the pixel circuit of the first structure is connected to the first initial signal line, and the pixel circuit of the second structure is connected to the first initial signal line and the second initial signal line. The first initial signal line and the second initial signal line provide different initial signals. In this example, the pixel circuit of the first structure adopts a single initial signal design, and the pixel circuit of the second structure adopts a dual initial signal design.

[0078] In some exemplary embodiments, the display substrate further includes: a plurality of first-region light-emitting elements and a plurality of first-type pixel circuits located in the first display area. At least one of the plurality of first-type pixel circuits is connected to at least one of the plurality of first-region light-emitting elements, and the orthographic projection of the at least one first-region light-emitting element on the substrate at least partially overlaps with the orthographic projection of the at least one first-region light-emitting element on the substrate. The plurality of first-type pixel circuits are all pixel circuits of the first structure.

[0079] In some exemplary embodiments, the pixel circuit of the first structure includes: a driving transistor, a first reset transistor, and a second reset transistor. The gate of the first reset transistor is connected to the first reset control line, the first electrode of the first reset transistor is connected to the gate of the driving transistor, and the second electrode of the first reset transistor is connected to the first initial signal line. The gate of the second reset transistor is connected to the second reset control line, the first electrode of the second reset transistor is connected to the first electrode of the light-emitting element, and the second electrode of the second reset transistor is connected to the first initial signal line. In this example, the pixel circuit of the first structure can adopt a single initial signal design.

[0080] In some exemplary embodiments, the pixel circuit of the second structure includes: a driving transistor, a first reset transistor, and a second reset transistor. The gate of the first reset transistor is connected to the first reset control line, the first electrode of the first reset transistor is connected to the gate of the driving transistor, and the second electrode of the first reset transistor is connected to the first initial signal line. The gate of the second reset transistor is connected to the second reset control line, the first electrode of the second reset transistor is connected to the first electrode of the light-emitting element, and the second electrode of the second reset transistor is connected to the second initial signal line. The second initial signal provided by the second initial signal line is different from the first initial signal provided by the first initial signal line. In this example, the pixel circuit of the second structure can adopt a design of two initial signals.

[0081] In some exemplary embodiments, the first initial signal provided by the first initial signal line is a constant voltage signal. For example, the first initial signal may be approximately -3 V. However, this embodiment is not limited thereto.

[0082] In some exemplary embodiments, the second initial signal provided by the second initial signal line may be a constant voltage signal, and the second initial signal may be greater than the first initial signal provided by the first initial signal line. For example, the first initial signal may be approximately -3.0V, and the second initial signal may be approximately -2.0V, -1.5V, -1.0V, or -0.5V. However, this embodiment is not limited to this.

[0083] In some exemplary embodiments, the size of the second initial signal provided by the second initial signal line connected to the pixel circuit of the second structure is proportional to the length of the second group of conductive lines connected to the pixel circuit of the second structure. In this example, the larger the length of the second group of conductive lines connected to the pixel circuit of the second structure, the larger the second initial signal provided by the second initial signal line connected to the pixel circuit of the second structure. However, this embodiment is not limited to this.

[0084] In some exemplary embodiments, the pixel circuit of the first structure or the pixel circuit of the second structure may further include: a data writing transistor, a threshold compensation transistor, a first light emission control transistor and a second light emission control transistor. The gate of the data writing transistor is connected to the scan line, the first electrode of the data writing transistor is connected to the data line, and the second electrode of the data writing transistor is connected to the first electrode of the driving transistor. The gate of the threshold compensation transistor is connected to the scan line, the first electrode of the threshold compensation transistor is connected to the gate of the driving transistor, and the second electrode of the threshold compensation transistor is connected to the second electrode of the driving transistor. The gate of the first light emission control transistor is connected to the light emission control line, the first electrode of the first light emission control transistor is connected to the first power line, and the second electrode of the first light emission control transistor is connected to the first electrode of the driving transistor. The gate of the second light emission control transistor is connected to the light emission control line, the first electrode of the second light emission control transistor is connected to the second electrode of the driving transistor, and the second electrode of the second light emission control transistor is connected to the first electrode of the light emitting element. In this example, the pixel circuit of the first structure and the pixel circuit of the second structure can both be 7T1C structures, that is, including 7 transistors and 1 capacitor. However, this embodiment is not limited to this. For example, the pixel circuit of the first structure and the pixel circuit of the second structure may include other numbers of transistors and capacitors.

[0085] In some exemplary embodiments, in a plane perpendicular to the display substrate, the display substrate includes at least: a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer disposed on a base substrate. The semiconductor layer includes at least: an active layer of a plurality of transistors. The first conductive layer includes at least: gate electrodes of a plurality of transistors and a first electrode of a storage capacitor, a scan line, a light emitting control line, a first reset control line, and a second reset control line. The second conductive layer includes at least: a second electrode of a storage capacitor, a first initial signal line, and a second initial signal line. The third conductive layer includes at least: a first electrode and a second electrode of a plurality of transistors, a first power line, and a data line.

[0086] In some exemplary embodiments, the active layers of the first reset transistor and the second reset transistor of the pixel circuit of the first structure may be an integrated structure; the active layers of the second reset transistor of the pixel circuit of the nth row of the first structure and the first reset transistor of the pixel circuit of the n+1th row may be an integrated structure, where n is a positive integer.

[0087] In some exemplary embodiments, the active layers of the first reset transistor and the second reset transistor of the pixel circuit of the second structure are an integrated structure; the active layer of the second reset transistor of the pixel circuit of the nth row of the second structure is not connected to the active layer of the first reset transistor of the pixel circuit of the n+1th row, and n is a positive integer.

[0088] In some exemplary embodiments, the third conductive layer includes: a second electrode of the second reset transistor of the pixel circuit of the second structure, and a second electrode of the second reset transistor of the pixel circuit of the first structure. The second electrode of the second reset transistor of the pixel circuit of the second structure is connected to the second initial signal line through a via. The second electrode of the second reset transistor of the pixel circuit of the first structure is not connected to the second initial signal line.

[0089] In some exemplary embodiments, the first group of conductive lines and the second group of conductive lines are made of transparent conductive materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), and the like.

[0090] In some exemplary embodiments, a plurality of second-type pixel circuits are spaced apart between a plurality of first-type pixel circuits.

[0091] In some exemplary embodiments, among the plurality of first-type pixel circuits and the plurality of second-type pixel circuits, the size of any pixel circuit in the first direction is smaller than the size of the first-region light-emitting element in the first direction. For example, the difference between the size of the first-region light-emitting element in the first direction and the size of any pixel circuit in the first direction may be about 4 micrometers. However, this embodiment is not limited to this.

[0092] In some exemplary embodiments, the plurality of second-region light-emitting elements include a plurality of groups of second-region light-emitting elements, the second-region light-emitting elements in each group are arranged along the first direction, and the plurality of second-region light-emitting elements are arranged along the second direction. The plurality of second-type pixel circuits include a plurality of groups of second-type pixel circuits, the second-type pixel circuits in each group are arranged along the first direction, and the plurality of second-type pixel circuits are arranged along the second direction. The plurality of second-region light-emitting elements include at least: a plurality of first light-emitting elements, a plurality of second light-emitting elements, and a plurality of third light-emitting elements. The plurality of second-type pixel circuits include: a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits. The plurality of first light-emitting elements are connected to the plurality of first pixel circuits, the plurality of second light-emitting elements are connected to the plurality of second pixel circuits, and the plurality of third light-emitting elements are connected to the plurality of third pixel circuits. In at least one group of second-region light-emitting elements and at least one group of second-type pixel circuits, the plurality of first pixel circuits connected to the plurality of first light-emitting elements are closer to the second display area than each of the plurality of second pixel circuits connected to the plurality of second light-emitting elements, and are closer to the second display area than each of the plurality of third pixel circuits connected to the plurality of third light-emitting elements.

[0093] In some exemplary embodiments, the second pixel circuit connected to the second light-emitting element through the second group of conductive lines is a pixel circuit of the second structure, the third pixel circuit connected to the third light-emitting element through the second group of conductive lines is a pixel circuit of the second structure, the first pixel circuit connected to the first light-emitting element through the first group of conductive lines is a pixel circuit of the first structure, and the first pixel circuit connected to the first light-emitting element through the second group of conductive lines is a pixel circuit of the second structure. However, this embodiment is not limited to this.

[0094] In some exemplary embodiments, the first light emitting element is configured to emit green light, one of the second light emitting element and the third light emitting element is configured to emit red light, and the other of the second light emitting element and the third light emitting element is configured to emit blue light. However, this embodiment is not limited thereto.

[0095] In some exemplary embodiments, the length of the first group of conductive lines is less than the length demarcation value, and the length of the second group of conductive lines is greater than or equal to the length demarcation value. The ratio of the length demarcation value to the maximum length of the second group of conductive lines is about 0.25 to 0.35. For example, the maximum length of the second group of conductive lines is about 10,000 microns, and the length demarcation value is about 3,000 microns. However, this embodiment is not limited to this. The lengths of the first group of conductive lines and the second group of conductive lines will change with the size of the display substrate.

[0096] The solution of this embodiment is described below by means of some examples.

[0097] Figure 1A is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 1B is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure.

[0098] In some exemplary embodiments, the display substrate includes: a first display area R1 and a second display area R2, and the first display area R1 may be located on at least one side of the second display area R2. In some examples, the first display area R1 partially surrounds the second display area R2. For example, Figure 1A The second display area R2 is shown to be located at the top center of the display substrate, one side of the second display area R2 is adjacent to the peripheral area, and the other three sides are surrounded by the first display area R1. However, this embodiment is not limited to this. For example, the second display area R2 can be located at other positions such as the upper left corner or the upper right corner of the display substrate.

[0099] In some exemplary embodiments, Figure 1B As shown, the first display area R1 may surround the second display area R2. The second display area R2 may be located in the middle of the upper half of the display substrate. However, this embodiment is not limited to this. The location of the second display area R2 may be determined as required.

[0100] In some exemplary embodiments, Figure 1A and Figure 1B As shown, the first display area R1 and the second display area R2 may both be rectangular, such as a rounded rectangle. However, this embodiment is not limited thereto. For example, the first display area R1 may be a circle or an ellipse or other shapes, and the second display area R2 may be a circle, a quadrilateral or a pentagon or other shapes. For example, the shapes of the first display area R1 and the second display area R2 may be the same or different.

[0101] In some exemplary embodiments, the second display area R2 may be a light-transmitting display area. For example, the orthographic projection of hardware such as a light sensor (e.g., a camera) on the display substrate may be located within the second display area R2 of the display substrate. The display substrate of this example does not need to be perforated, and a true full screen may be possible while ensuring the practicality of the display substrate.

[0102] In some exemplary embodiments, the display substrate may include a plurality of sub-pixels disposed on a substrate, at least one of the sub-pixels including a pixel circuit and a light-emitting element. The pixel circuit is configured to drive the light-emitting element. For example, the pixel circuit is configured to provide a driving current to drive the light-emitting element to emit light. For example, the light-emitting element may be an organic light-emitting diode (OLED), and the light-emitting element emits red light, green light, blue light, or white light, etc., when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as required.

[0103] In some exemplary embodiments, in order to improve the light transmittance of the second display area R2, only a light emitting element may be provided in the second display area R2, and a pixel circuit driving the light emitting element of the second display area R2 may be provided in the first display area R1. That is, the light transmittance of the second display area R2 is improved by separately providing the light emitting element and the pixel circuit. In this example, no pixel circuit is provided in the second display area R2.

[0104] Figure 2 FIG. 1 is a schematic diagram of the structure of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, Figure 2As shown, the display substrate includes: a plurality of first-type pixel circuits 10, a plurality of second-type pixel circuits 20 and a plurality of first-region light-emitting elements 30 located in the first display area R1, and a plurality of second-region light-emitting elements 40 located in the second display area R2. The plurality of second-type pixel circuits 20 may be distributed between the plurality of first-type pixel circuits 10 at intervals. At least one first-type pixel circuit 10 among the plurality of first-type pixel circuits 10 may be connected to at least one first-region light-emitting element 30 among the plurality of first-region light-emitting elements 30, and the orthographic projection of at least one first-type pixel circuit 10 on the substrate substrate may at least partially overlap with the orthographic projection of at least one first-region light-emitting element 30 on the substrate substrate. The at least one first-type pixel circuit 10 may be configured to provide a driving signal to the connected first-region light-emitting element 30 to drive the first-region light-emitting element 30 to emit light. At least one second type pixel circuit 20 among the plurality of second type pixel circuits 20 may be connected to at least one second area light emitting element 40 among the plurality of second area light emitting elements 40 through a conductive line L, and the at least one second type pixel circuit 20 may be configured to provide a driving signal to the connected second area light emitting element 40 to drive the second area light emitting element 40 to emit light. Since the second area light emitting element 40 and the second type pixel circuit 20 are located in different areas, there is no overlapping portion between the orthographic projection of the at least one second type pixel circuit 20 on the substrate and the orthographic projection of the at least one second area light emitting element 40 on the substrate.

[0105] In this exemplary embodiment, the first display area R1 can be set as a non-light-transmitting display area, and the second display area R2 can be set as a light-transmitting display area. That is, the first display area R1 of this exemplary embodiment is not light-transmitting, and the second display area R2 is light-transmitting. In this way, there is no need to dig holes on the display substrate, and the required hardware structures such as the photosensitive sensor can be directly set in the second display area R2, laying a solid foundation for the realization of a true full screen. In addition, since the second display area R2 only includes light-emitting elements but not pixel circuits, it can also ensure that the transmittance of the second display area R2 is good.

[0106] In the present exemplary embodiment, the first region light emitting element 30 may be referred to as an in-situ light emitting element, the first type pixel circuit 10 may be referred to as an in-situ pixel circuit, and the second type pixel circuit 20 may be referred to as a non-in-situ pixel circuit.

[0107] In some exemplary embodiments, Figure 2 As shown, the second region light emitting element 40 and the second type pixel circuit 20 connected to the second region light emitting element 40 are located in the same row. That is, the light emitting signal of the second region light emitting element 40 comes from the second type pixel circuit 20 in the same row. For example, the pixel circuits of the sub-pixels in the same row are connected to the same gate line.

[0108] In some exemplary embodiments, Figure 2 As shown, the second type pixel circuit 20 is connected to the second area light emitting element 40 through a conductive line L. For example, the conductive line L can be made of a transparent conductive material. For example, the conductive line L can be made of a conductive oxide material. For example, the conductive oxide material can include indium tin oxide (ITO), but is not limited thereto. One end of the conductive line L is connected to the second type pixel circuit 20, and the other end of the conductive line L is connected to the second area light emitting element 40. Figure 2 As shown, the conductive line L extends from the first display area R1 to the second display area R2.

[0109] Figure 3 FIG. 1 is another schematic diagram of the structure of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, Figure 3 As shown, the first display area R1 includes not only a plurality of pixel units, but also a plurality of columns of second type pixel circuits, and the second display area R2 includes only a plurality of second region light-emitting elements. In this example, at least one pixel unit may include: a red sub-pixel R, two green sub-pixels G1 and G2, and a blue sub-pixel B, and the red sub-pixel R and the blue sub-pixel B are located in the same column, and the two green sub-pixels G1 and G2 are located in the same column. However, this embodiment is not limited to this. In some examples, a pixel unit may also include sub-pixels of other colors and other numbers, and the arrangement of the plurality of sub-pixels is not limited to Figure 3 The structure shown.

[0110] For example, a pixel unit may include three sub-pixels (e.g., a red sub-pixel R, a blue sub-pixel B, and a green sub-pixel G), and the three sub-pixels may be arranged in parallel horizontally, in parallel vertically, or in a triangular pattern. For example, a pixel unit may include four sub-pixels (a red sub-pixel R, a blue sub-pixel B, a green sub-pixel G, and a white sub-pixel), and the four sub-pixels may be arranged in parallel horizontally, in parallel vertically, or in a square pattern. However, the present disclosure is not limited thereto.

[0111] FIG. 4A to FIG. 4C FIG. 1 is a partial plan view of a display substrate of at least one embodiment of the present disclosure. In some exemplary embodiments, Figure 4A As shown, the second display area R2 is a light-transmitting display area, and the first display area R1 is a non-light-transmitting display area. Figure 4A and Figure 4BAs shown, the density of the second region light emitting elements 40 of the second display region R2 may be approximately equal to the density of the first region light emitting elements 30 of the first display region R1. That is, the resolution of the second display region R2 may be approximately the same as the resolution of the first display region R1. However, this embodiment is not limited to this. For example, the density of the second region light emitting elements 40 may be greater than or less than the density of the first region light emitting elements 30. That is, the resolution of the second display region R2 may be greater than or less than the resolution of the first display region R1. Figure 4B and Figure 4C As shown, the light emitting area of ​​the light emitting element 40 in the second region is smaller than the light emitting area of ​​the light emitting element 30 in the first region. That is, the light emitting area of ​​the light emitting element 30 in the first region is larger than the light emitting area of ​​the light emitting element 40 in the second region. Figure 4C The dotted lines in FIG. 4 show the light emitting area of ​​the second region light emitting element 40 and the light emitting area of ​​the first region light emitting element 30. For example, the light emitting area of ​​the light emitting element may correspond to the area of ​​the opening of the pixel definition layer.

[0112] In some exemplary embodiments, Figure 4C As shown, in the second display area R2, a light-transmitting area R0 is provided between adjacent second-area light-emitting elements 40. For example, a plurality of light-transmitting areas R0 are connected to each other to form a continuous light-transmitting area separated by a plurality of second-area light-emitting elements 40. The conductive line L can be made of a transparent conductive material to maximize the light transmittance of the light-transmitting area R0. Figure 4C As shown, the area in the second display area R2 except for the second area light emitting element 40 can be a light-transmitting area.

[0113] In some exemplary embodiments, Figure 4B and Figure 4D As shown, in the first display area R1, the area for setting the second type pixel circuit 20 can be obtained by reducing the size of the first type pixel circuit 10 in the first direction X. For example, the size of the first type pixel circuit 10 in the first direction X can be smaller than the size of the first area light-emitting element 30 in the first direction X. The first direction X is, for example, a row direction, but is not limited thereto. In other embodiments, the first direction X can be a column direction. This exemplary embodiment is described by taking the first direction X as the row direction as an example. For example, the size of the first type pixel circuit 10 and the second type pixel circuit 20 in the first direction X can be the same, and the size of each pixel circuit in the first direction X can differ from the size of the first area light-emitting element 30 in the first direction X by about 4 microns (μm). The size of each pixel circuit in the second direction Y is substantially the same as the size of the first area light-emitting element 30 in the second direction Y. Wherein, the first direction X is perpendicular to the second direction Y.

[0114] FIG. 4D to FIG. 4FSchematic diagram of a partial structure of a display substrate of at least one embodiment of the present disclosure. In order to further reflect that after compressing the pixel circuit, there are more columns of pixel circuits, Figure 4D A schematic structural diagram of the first region light emitting element of the first display region R1 is shown. Figure 4E Shows Figure 4A A schematic diagram of a partial structure of the first display area R1 (including only the pixel circuit), Figure 4F Shows Figure 4A Schematic diagram of a partial structure of the first display area R1 (including only the light-emitting element).

[0115] In some exemplary embodiments, FIG. 4D to FIG. 4F As shown, the size of the pixel circuit in the first direction X is smaller than the size of the light-emitting element in the first direction X. In this way, the pixel circuits in the 2nd and 9th columns from right to left are not connected to any first-region light-emitting element 30, and belong to extra-column pixel circuits, which can be used as the second type pixel circuit 20 to connect the second-region light-emitting element 40 in the second display area R2. Figure 4E and Figure 4F As shown, any first-region light-emitting element 30 may be one of the four light-emitting elements RG1BG2. The first electrode E1 of the first-region light-emitting element 30 may be connected to the first transfer electrode CE1 of the first-type pixel circuit 10 through the second transfer electrode CE2. R represents a light-emitting element that emits red light, G1 represents a light-emitting element that emits green light, B represents a light-emitting element that emits blue light, and G2 represents a light-emitting element that emits green light. At least one second-type pixel circuit 20 may have a first transfer electrode, and at least one second-region light-emitting element 40 may have a second transfer electrode. For example, at least one second-type pixel circuit 20 and at least one second-region light-emitting element 40 may be connected through a conductive line L, which may include: the conductive line L is respectively connected to the first transfer electrode of at least one second-type pixel circuit 20 and the second transfer electrode of at least one second-region light-emitting element 40. In order to have sufficient space for setting the conductive line L, the axes of the first transfer electrode and the second transfer electrode in the same row of sub-pixels may be located on a straight line. However, this embodiment is not limited to this.

[0116] In some exemplary embodiments, Figure 4F As shown, G includes G1 or G2. Figure 4F In the pixel arrangement shown, one repeating unit RP includes two Gs arranged in the second direction Y and R and B arranged on both sides of the two Gs in the first direction X, wherein R and G constitute one pixel, and use B in another repeating unit adjacent thereto to constitute one virtual pixel for display, and B and G constitute one pixel, and use R in another repeating unit adjacent thereto to constitute one virtual pixel for display. However, this embodiment is not limited to this.

[0117] Figure 5A The present invention is a partial schematic diagram of a row of light-emitting elements and a second type pixel circuit connected thereto located in a second display area of ​​a display substrate according to at least one embodiment of the present disclosure. Figure 5B FIG. 1 is a schematic diagram of the capacitance of light emitting elements emitting light of different colors in the same row of light emitting elements in the second display region of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, the second display region R2 is symmetrical about the central axis in the first direction X. Figure 5A Only the connection relationship between a row of light emitting elements in the left half of the second display area R2 and the second type pixel circuit in the first display area R1 is illustrated.

[0118] In some exemplary embodiments, Figure 5A As shown, in the second display area R2, the plurality of second region light-emitting elements 40 include: a plurality of first light-emitting elements 41, a plurality of second light-emitting elements 42, a plurality of third light-emitting elements 43, and a plurality of fourth light-emitting elements 44. The first light-emitting element 41 is configured to emit a first color light, the second light-emitting element 42 is configured to emit a second color light, the third light-emitting element 43 is configured to emit a third color light, and the fourth light-emitting element 44 is configured to emit a fourth color light. In some examples, the first color light and the fourth color light are both green (G) light, the second color light is red (R) light, and the third color light is blue (B) light. However, this embodiment is not limited to this.

[0119] In some exemplary embodiments, Figure 5A As shown, in the first display area R1, the plurality of second type pixel circuits 20 include: a plurality of first pixel circuits 21, a plurality of second pixel circuits 22, a plurality of third pixel circuits 23, and a plurality of fourth pixel circuits 24. The plurality of first light-emitting elements 41 are connected to the plurality of first pixel circuits 21 through a plurality of first conductive lines La, the plurality of second light-emitting elements 42 are connected to the plurality of second pixel circuits 22 through a plurality of second conductive lines Lb, the plurality of third light-emitting elements 43 are connected to the plurality of third pixel circuits 23 through a plurality of third conductive lines Lc, and the plurality of fourth light-emitting elements 44 are connected to the plurality of fourth pixel circuits 24 through a plurality of fourth conductive lines Ld. For example, one first light-emitting element 41 is connected to one first pixel circuit 21 through one first conductive line La, one second light-emitting element 42 is connected to one second pixel circuit 22 through one second conductive line Lb, one third light-emitting element 43 is connected to one third pixel circuit 23 through one third conductive line Lc, and one fourth light-emitting element 44 is connected to one fourth pixel circuit 24 through one fourth conductive line Ld. However, this embodiment is not limited to this.

[0120] In some exemplary embodiments, at least one of the first conductive line La, the second conductive line Lb, the third conductive line Lc, and the fourth conductive line Ld may be made of a transparent conductive material.

[0121] In some exemplary embodiments, the plurality of second-region light-emitting elements 40 of the second display region R2 include a plurality of groups of second-region light-emitting elements 40, the second-region light-emitting elements 40 in each group are arranged along the first direction X, and the plurality of groups of second-region light-emitting elements 40 are arranged along the second direction Y. The plurality of second-type pixel circuits 20 include a plurality of groups of second-type pixel circuits 20, the second-type pixel circuits 20 in each group are arranged along the first direction X, and the plurality of groups of second-type pixel circuits 20 are arranged along the second direction Y. The first-type pixel circuits 10 are arranged between the second-type pixel circuits 20 in each group. Figure 5A A group of second-region light-emitting elements 40 and a group of second-type pixel circuits 20 are illustrated in FIG. In this example, a group of second-region light-emitting elements 40 may be a row of second-region light-emitting elements 40, and a group of second-type pixel circuits 20 may be a row of second-type pixel circuits 20. Figure 5A The upper side, the lower side, or the upper side and the lower side of the row of second-region light-emitting elements 40 shown may further include a plurality of rows of second-region light-emitting elements that are the same as the row of second-region light-emitting elements 40 shown.

[0122] In the disclosed embodiments, a row of light-emitting elements may refer to pixel circuits connected to the row of light-emitting elements being connected to the same gate line (e.g., scan line). A row of pixel circuits may refer to pixel circuits connected to the same gate line. A row of sub-pixels may refer to pixel circuits connected to the row of sub-pixels being connected to the same gate line. However, the present embodiment does not limit this.

[0123] In some exemplary embodiments, Figure 5A As shown, in a group of second-region light-emitting elements 40 and a group of second-type pixel circuits 20, the plurality of first pixel circuits 21 connected to the plurality of first light-emitting elements 41 are closer to the second display region R2 than each of the plurality of second pixel circuits 22 connected to the plurality of second light-emitting elements 42, and closer to the second display region R2 than each of the plurality of third pixel circuits 23 connected to the plurality of third light-emitting elements 43. The plurality of fourth pixel circuits 24 connected to the plurality of fourth light-emitting elements 44 are closer to the second display region R2 than each of the plurality of second pixel circuits 22 connected to the plurality of second light-emitting elements 42, and closer to the second display region R2 than each of the plurality of third pixel circuits 23 connected to the plurality of third light-emitting elements 43. In this example, when designing the second-type pixel circuits 20 connected to the second-region light-emitting elements 40, the G priority order is adopted, that is, the second-type pixel circuits connected to the green light-emitting elements are preferentially arranged close to the second display region R2.

[0124] In some exemplary embodiments, Figure 5A As shown, in at least one group of second-region light-emitting elements 40 and at least one group of second-type pixel circuits 20, at least one of the plurality of first-type pixel circuits 10 is disposed between two adjacent second-type pixel circuits 20. In some examples, in at least one group of second-region light-emitting elements 40 and at least one group of second-type pixel circuits 20, no other second-type pixel circuits 20 are disposed between two first pixel circuits 21 connected to two adjacent first conductive lines La. This arrangement is conducive to reducing the length of the first conductive lines La, and also conducive to reducing the length difference between the first conductive lines La.

[0125] In some exemplary embodiments, Figure 5A As shown, in order to make the second conductive lines Lb have a smaller capacitance difference and in order to make the third conductive lines Lc have a smaller capacitance difference, in at least one group of second-region light-emitting elements 40 and at least one group of second-type pixel circuits 20, a plurality of second pixel circuits 22 connected to a plurality of second conductive lines Lb and a plurality of third pixel circuits 23 connected to a plurality of third conductive lines Lc are alternately arranged. However, this embodiment is not limited to this.

[0126] In some exemplary embodiments, Figure 5A As shown, in order to make the first conductive line La have a smaller capacitance difference and the fourth conductive line Ld have a smaller capacitance difference, in at least one group of second-region light-emitting elements and at least one group of second-type pixel circuits, a plurality of fourth pixel circuits 24 connected to a plurality of fourth conductive lines Ld and a plurality of first pixel circuits 21 connected to a plurality of first conductive lines La are alternately arranged. However, this embodiment is not limited to this.

[0127] In some exemplary embodiments, Figure 5B As shown, the horizontal axis represents the position of the second display area R2 of the display substrate in the first direction X, and the vertical axis represents the ratio of the capacitance of the conductive line connected to the light-emitting element at this position to the total capacitance. Figure 5B As shown, the capacitance of the conductive line connected to the green light-emitting element is the smallest, and as Figure 5B As shown in the left half of the figure, the capacitance of the conductive line connected to the green light-emitting element shows a trend of gradually increasing, so the capacitance difference between two conductive lines connected to adjacent green light-emitting elements is small. Since the structure of the second display area R2 of the display substrate is symmetrically arranged about the first direction X, Figure 5B The right half shown will not be described in detail. Figure 5BAs shown, the capacitance of the conductive wire connected to the green light-emitting element is smaller than that of the conductive wire connected to the red light-emitting element, and the capacitance of the conductive wire connected to the green light-emitting element is smaller than that of the conductive wire connected to the blue light-emitting element. Figure 5B As shown, the capacitance of the conductive wire connected to the red light-emitting element shows a gradually increasing trend, and the capacitance of the conductive wire connected to the blue light-emitting element shows a gradually increasing trend, and the capacitance of the conductive wire connected to the red light-emitting element and the capacitance of the conductive wire connected to the blue light-emitting element are not much different.

[0128] In some exemplary embodiments, the plurality of second-type pixel circuits 20 in the first display area R1 include: a plurality of pixel circuits of the first structure and a plurality of pixel circuits of the second structure. The plurality of first-type pixel circuits 10 in the first display area R1 are all pixel circuits of the first structure. In some examples, the pixel circuit of the first structure and the pixel circuit of the second structure may both be 7T1C structures, i.e., including 7 transistors and 1 capacitor. However, this embodiment is not limited to this.

[0129] The pixel circuit of the first structure and the pixel circuit of the second structure according to the present exemplary embodiment will be described in detail below.

[0130] Fig. 6A Schematic diagram of a pixel circuit of a first structure according to at least one embodiment of the present disclosure. Figure 6B Schematic diagram of a pixel circuit of a second structure according to at least one embodiment of the present disclosure. Figure 6C This is an operation timing diagram of a pixel circuit of a first structure and a pixel circuit of a second structure according to at least one embodiment of the present disclosure.

[0131] In some exemplary embodiments, Fig. 6A and Figure 6B As shown, the pixel circuit of the first structure and the pixel circuit of the second structure both include six switch transistors (T1, T2, T4 to T7), a drive transistor T3 and a storage capacitor Cst. The six switch transistors are respectively a data writing transistor T4, a threshold compensation transistor T2, a first light emission control transistor T5, a second light emission control transistor T6, a first reset transistor T1, and a second reset transistor T7. The light emitting element EL includes a first pole E1, a second pole E2 and an organic light emitting layer located between the first pole E1 and the second pole E2. For example, the first pole E1 can be an anode, and the second pole E2 can be a cathode.

[0132] In some exemplary embodiments, the driving transistor and the six switching transistors may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product. In some possible implementations, the driving transistor and the six switching transistors may include P-type transistors and N-type transistors.

[0133] In some exemplary embodiments, the driving transistor and the six switching transistors may be low-temperature polysilicon thin film transistors, or may be oxide thin film transistors, or may be low-temperature polysilicon thin film transistors and oxide thin film transistors. The active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0134] In some exemplary embodiments, Fig. 6A and Figure 6BAs shown, the display substrate includes a scan line GT, a data line DT, a first power line PL1, a second power line PL2, a light emitting control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. In some examples, the first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel circuit, the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel circuit, and the first voltage signal VDD is greater than the second voltage signal VSS. The scan line GT is configured to provide a scan signal SCAN to the pixel circuit, the data line DT is configured to provide a data signal DATA to the pixel circuit, the light emitting control line EML is configured to provide a light emitting control signal EM to the pixel circuit, the first reset control line RST1 is configured to provide a first reset control signal RESET1 to the pixel circuit, and the second reset control line RST2 is configured to provide a scan signal SCAN to the pixel circuit. For example, in a row of pixel circuits, the second reset control line RST2 can be connected to the scan line GT to be input with the scan signal SCAN. However, this embodiment is not limited to this. For example, the second reset control signal line RST2 may be input with the second reset control signal RESET2. For example, in the nth row of pixel circuits, the first reset control line RST1 may be connected to the scan line GT of the n-1th row of pixel circuits to be input with the scan signal SCAN(n-1), that is, the first reset control signal RESET1(n) is the same as the scan signal SCAN(n-1). In this way, the signal lines of the display substrate can be reduced, and a narrow frame of the display substrate can be achieved.

[0135] In some exemplary embodiments, the first initial signal line INIT1 is configured to provide a first initial signal Vinit1 to the pixel circuit. The second initial signal line INIT2 is configured to provide a second initial signal Vinit2 to the pixel circuit. For example, the first initial signal Vinit1 and the second initial signal Vinit2 may be constant voltage signals, whose magnitudes may be, for example, between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto. For example, the first initial signal Vinit1 and the second initial signal Vinit2 may be less than or equal to the second voltage signal VSS.

[0136] In some exemplary embodiments, Fig. 6AAs shown, in the pixel circuit of the first structure, the driving transistor T3 is electrically connected to the light emitting element EL, and outputs a driving current to drive the light emitting element EL to emit light under the control of the scanning signal SCAN, the data signal DATA, the first voltage signal VDD, the second voltage signal VSS and other signals. The gate of the data writing transistor T4 is connected to the scanning line GT, the first electrode of the data writing transistor T4 is connected to the data line DT, and the second electrode of the data writing transistor T4 is connected to the first electrode of the driving transistor T3. The gate of the threshold compensation transistor T2 is connected to the scanning line GT, the first electrode of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3, and the second electrode of the threshold compensation transistor T2 is connected to the second electrode of the driving transistor T3. The gate of the first light emission control transistor T5 is connected to the light emission control line EML, the first electrode of the first light emission control transistor T5 is connected to the first power line PL1, and the second electrode of the first light emission control transistor T5 is connected to the first electrode of the driving transistor T3. The gate of the second light emission control transistor T6 is connected to the light emission control line EML, the first electrode of the second light emission control transistor T6 is connected to the second electrode of the driving transistor T3, and the second electrode of the second light emission control transistor T6 is connected to the first electrode E1 of the light emitting element EL. The first reset transistor T1 is connected to the gate of the driving transistor T3 and is configured to reset the gate of the driving transistor T3. The second reset transistor T7 is connected to the first electrode E1 of the light emitting element EL and is configured to reset the first electrode E1 of the light emitting element EL. The gate of the first reset transistor T1 is connected to the first reset control line RST1, the first electrode of the first reset transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first reset transistor T1 is connected to the gate of the driving transistor T3. The gate of the second reset transistor T7 is connected to the second reset control line RST2, the first electrode of the second reset transistor T7 is connected to the first initial signal line INIT1, and the second electrode of the second reset transistor T7 is connected to the first electrode E1 of the light emitting element EL. The first electrode of the storage capacitor Cst is connected to the gate of the driving transistor T3, and the second electrode of the storage capacitor Cst is connected to the first power line PL1. In this example, the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the driving transistor T3 and the threshold compensation transistor T2, the second node N2 is the connection point of the first light-emitting control transistor T5, the data writing transistor T4 and the driving transistor T3, the third node N3 is the connection point of the driving transistor T3, the threshold compensation transistor T2 and the second light-emitting control transistor T6, and the fourth node N4 is the connection point of the second light-emitting control transistor T6, the second reset transistor T7 and the light-emitting element EL.

[0137] Refer to the following Figure 6C right Fig. 6AThe operation process of the pixel circuit of the first structure is described by taking the pixel circuit of the first structure including a plurality of transistors which are all P-type transistors as an example.

[0138] In some exemplary embodiments, Figure 6C As shown, in a frame display time period, the working process of the pixel circuit of the first structure includes: a first stage A1, a second stage A2 and a third stage A3.

[0139] The first stage A1 is called the reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, which turns on the first reset transistor T1, and the first initial signal Vinit1 provided by the first initial signal line INIT1 is provided to the first node N1, which initializes the first node N1 and clears the original data voltage in the storage capacitor Cst. The scan signal SCAN provided by the scan line GT is a high-level signal, and the light control signal EM provided by the light control line EML is a high-level signal, which turns off the data writing transistor T4, the threshold compensation transistor T2, the first light control transistor T5, the second light control transistor T6 and the second reset transistor T7. In this stage, the light emitting element EL does not emit light.

[0140] The second stage A2 is called the data writing stage or the threshold compensation stage. The scanning signal SCAN provided by the scanning line GT is a low level signal, the first reset control signal RESET1 provided by the first reset control line RST1 and the light control signal EM provided by the light control line EML are both high level signals, and the data line DT outputs the data signal DATA. In this stage, since the second electrode of the storage capacitor Cst is at a low level, the driving transistor T3 is turned on. The scanning signal SCAN is a low level signal, which turns on the threshold compensation transistor T2, the data writing transistor T4 and the second reset transistor T7. The threshold compensation transistor T2 and the data writing transistor T4 are turned on, so that the data voltage Vdata output by the data line DT is provided to the first node N2 through the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on threshold compensation transistor T2, and the difference between the data voltage Vdata output by the data line DT and the threshold voltage of the driving transistor T3 is charged into the storage capacitor Cst, and the voltage of the second electrode (i.e., the first node N1) of the storage capacitor Cst is Vdata-|Vth|, where Vdata is the data voltage output by the data line DT, and Vth is the threshold voltage of the driving transistor T3. The second reset transistor T7 is turned on, so that the first initial signal Vinit1 provided by the first initial signal line INIT1 is provided to the first electrode E1 of the light-emitting element EL, and the first electrode E1 of the light-emitting element EL is initialized (reset), and the pre-stored voltage inside it is cleared to complete the initialization, ensuring that the light-emitting element EL does not emit light. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, which turns off the first reset transistor T1. The light emitting control signal EM provided by the light emitting control signal line EML is a high level signal, so that the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned off.

[0141] The third stage A3 is called the light-emitting stage. The light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, and the scan signal SCAN provided by the scan line GT and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals. The light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, which turns on the first light-emitting control transistor T5 and the second light-emitting control transistor T6, and the first voltage signal VDD output by the first power line PL1 provides a driving voltage to the first electrode E1 of the light-emitting element EL through the turned-on first light-emitting control transistor T5, the driving transistor T3 and the second light-emitting control transistor T6, thereby driving the light-emitting element EL to emit light.

[0142] During the pixel circuit driving process, the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the driving transistor T3 is:

[0143] I=K*(Vgs-Vth)2=K*[(VDD-Vdata+|Vth|)-Vth]2=K*[(VDD-Vdata)] 2

[0144] Among them, I is the driving current flowing through the driving transistor T3, that is, the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the driving transistor T3, Vth is the threshold voltage of the driving transistor T3, Vdata is the data voltage output by the data line DT, and VDD is the first voltage signal output by the first power line PL1.

[0145] It can be seen from the above formula that the current flowing through the light emitting element EL has nothing to do with the threshold voltage of the driving transistor T3. Therefore, the pixel circuit of the first structure of this embodiment can better compensate for the threshold voltage of the driving transistor T3.

[0146] In some exemplary embodiments, Figure 6B As shown, in the pixel circuit of the second structure, the gate of the second reset transistor T7 is connected to the second reset control line RST2, the first electrode of the second reset transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the second reset transistor T7 is connected to the first electrode E1 of the light emitting element EL. The first initial signal line INIT1 and the second initial signal line INIT2 are insulated from each other and are configured to input signals respectively. The structures of the remaining transistors and storage capacitors of the pixel circuit of the second structure can be referred to Fig. 6A The relevant description of the pixel circuit of the first structure is shown, so it will not be repeated here.

[0147] In some exemplary embodiments, Figure 6B and Figure 6C As shown, during the operation of the pixel circuit of the second structure, in the second stage A2, the second reset transistor T7 is turned on, so that the second initial signal Vinit2 provided by the second initial signal line INIT2 is provided to the first electrode E1 of the light emitting element EL, the first electrode E1 of the light emitting element EL is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and it is ensured that the light emitting element EL does not emit light. The rest of the operation process of the pixel circuit of the second structure can refer to the relevant description of the operation process of the pixel circuit of the first structure, so it will not be repeated here.

[0148] In this exemplary embodiment, the pixel circuit of the first structure adopts a single initial signal design, wherein the first reset transistor and the second reset transistor receive the same initial signal (i.e., the first initial signal); the pixel circuit of the second structure adopts a two initial signal design, wherein the first reset transistor and the second reset transistor receive different initial signals (i.e., the first reset transistor receives the first initial signal, and the second reset transistor receives the second initial signal).

[0149] The pixel circuits of the first display area R1 are Figure 6B As an example of the pixel circuit shown in FIG. 1 , the second type pixel circuit and the second area light emitting element are connected by a conductive wire, and the length of the conductive wire is too large, which may cause Figure 6B The fourth node N4 capacitance in the pixel circuit shown is too large, so that after the fourth node N4 is reset to the second initial signal Vinit2 in the second stage A2, it takes a long time to charge to reach the predetermined potential. In this way, the light-emitting element in the second area will be affected, resulting in a dark display and a display brightness difference between the first display area R1 and the second display area R2. By increasing the second initial signal Vinit2, the charge amount of the fourth node N4 can be effectively reduced. Under the condition of a constant current, the amount of electricity is proportional to the duration. Therefore, by increasing the second initial signal Vinit2, the charging duration can be effectively reduced, thereby increasing the light-emitting duration and improving the brightness difference caused by the excessive length of the conductive line. However, increasing the second initial signal Vinit2 has the risk of leakage of the light-emitting element EL. Since the second initial signal Vinit2 provides the anode voltage of the light-emitting element EL, and the second voltage signal VSS provides the cathode voltage of the light-emitting element EL, if the second initial signal Vinit2 is too high, the contrast ratio will be reduced, the black screen cannot be displayed, and the light-emitting element EL is easy to be lit.

[0150] In this exemplary embodiment, the structure of the pixel circuit is designed in consideration of the length of the conductive line to improve the display effect. The first type pixel circuit in the first display area and the first area light emitting element do not need to be connected by a conductive line. In order to avoid increasing the disadvantage of the second initial signal Vinit2, the first type pixel circuit can adopt a single initial signal design. For example, the first type pixel circuit can be Fig. 6A The pixel circuit of the first structure is shown.

[0151] In this exemplary embodiment, the second type pixel circuit in the first display area and the second area light-emitting element in the second display area are connected by a conductive wire, and the lengths of the conductive wires connected to different second area light-emitting elements are different. The length boundary value of the conductive wire that causes the brightness difference between the first display area and the second display area can be determined by simulation, and the conductive wires connecting the second area light-emitting elements and the second type pixel circuit are divided into a first group of conductive wires and a second group of conductive wires based on this length boundary value. The length of the first group of conductive wires can be less than the length boundary value. The length of the second group of conductive wires can be greater than or equal to the length boundary value, which will cause a brightness difference between the first display area and the second display area. The second type pixel circuit connected to the second area light-emitting element via the first group of conductive wires can adopt a single initial signal design, for example, it can be Fig. 6A The pixel circuit of the first structure shown in the figure can avoid the situation where the light-emitting element is easily turned on by increasing the second initial signal Vinit2. The second type of pixel circuit connected to the light-emitting element in the second area through the second group of conductive lines can adopt a dual initial signal design, for example, Figure 6B The pixel circuit of the second structure shown in the figure has difficulty in lighting up the second region light emitting element connected to the second group of conductive lines due to the large conductive line capacitance. By increasing the second initial signal Vinit2, the charging time of the fourth node N4 can be reduced to improve display defects.

[0152] In some examples, during the simulation process of determining the length demarcation value, a constant second initialization signal may be provided, and then the length demarcation value may be determined based on the effect of the brightness of the display substrate changing with the length of the conductive line. Alternatively, the capacitance of the conductive line may be calculated, and the length demarcation value may be determined based on the display effect at a low gray scale. However, this embodiment is not limited to this.

[0153] In some exemplary embodiments, Figure 5AAs shown, the length of the first conductive line La connected to the first light-emitting element 41 and the first pixel circuit 21 is about 100μm to 6000μm, the length of the second conductive line Lb connecting the second light-emitting element 42 and the second pixel circuit 22 is about 5000μm to 10000μm, the length of the third conductive line Lc connecting the third light-emitting element 43 and the third pixel circuit 23 is about 5000μm to 10000μm, and the length of the fourth conductive line Ld connecting the fourth light-emitting element 44 and the fourth pixel circuit 24 is about 100μm to 6000μm. In this example, the length boundary value of the conductive line obtained by simulation can be about 3000μm. Among them, the conductive line with a length less than 3000μm can be called the first group of conductive lines, and the conductive line with a length greater than or equal to 3000μm can be called the second group of conductive lines. The second type pixel circuit connected to the first group of conductive lines can be a pixel circuit of the first structure, and the second type pixel circuit connected to the second group of conductive lines can be a pixel circuit of the second structure. On the basis of distinguishing the first group of conductive lines from the second group of conductive lines, the structure of the pixel circuit is adjusted to avoid the situation where the second initial signal produces poor display when the capacitance of the conductive line is small, and to improve the display defect by increasing the second initial signal when the capacitance of the conductive line is large. This embodiment does not limit the length of the conductive line. When the size of the display substrate changes, the length boundary value and the length of the conductive line will change.

[0154] In some exemplary embodiments, Figure 5A As shown, the first pixel circuit 21 connected to the first conductive line La with a length of about 100μm to 3000μm can be a pixel circuit of the first structure, and the first pixel circuit 21 connected to the first conductive line La with a length of about 3000μm to 6000μm can be a pixel circuit of the second structure; the second pixel circuit 22 connected to the second conductive line Lb and the third pixel circuit 23 connected to the third conductive line Lc are both pixel circuits of the second structure; the fourth pixel circuit 24 connected to the fourth conductive line Ld with a length of about 100μm to 3000μm can be a pixel circuit of the first structure, and the fourth pixel circuit 24 connected to the fourth conductive line Ld with a length of about 3000μm to 6000μm can be a pixel circuit of the second structure.

[0155] In some exemplary embodiments, Figure 5A As shown, in the first display area R1, the first area light-emitting element 30 and the first type pixel circuit 10 do not need to be connected by a conductive line, and the first type pixel circuit 10 can all be pixel circuits of the first structure to avoid the situation where the light-emitting element is easily turned on due to the enhancement of the second initial signal.

[0156] In some exemplary embodiments, the first initial signal Vinit1 provided by the first initial signal line INIT1 may be a constant voltage signal, for example, approximately -3V. The second initial signal Vinit2 provided by the second initial signal line INIT2 may be a constant voltage signal, and is greater than the first initial signal Vinit1. For example, the second initial signal Vinit2 may be greater than -3V, such as approximately -2V, -1.5V, -1V or -0.5V. In some examples, a plurality of second initial signal lines INIT2 may provide different second initial signals. For example, the size of the second initial signal provided by the second initial signal line connected to the pixel circuit of the second structure is proportional to the length of the second group of conductive lines connected between the pixel circuit of the second structure and the second regional light-emitting element. For example, the longer the second group of conductive lines connected to the pixel circuit of the second structure, the larger the second initial signal provided by the second initial signal line connected to the pixel circuit. However, this embodiment is not limited to this.

[0157] Fig. 7A The diagram is a plan view of a pixel circuit of a first structure according to at least one embodiment of the present disclosure. Figure 7B for Fig. 7A A schematic partial cross-sectional view along the PP direction in FIG. 1 , wherein the first direction X may be the direction of the sub-pixel row (horizontal direction), and the second direction Y may be the direction of the sub-pixel column (vertical direction).

[0158] In some exemplary embodiments, Fig. 7A As shown, in a plane parallel to the display substrate, the display substrate is provided with a scan line GT, a light emission control line EML, a first reset control line RST1, a first initial signal line INIT1, a second initial signal line INIT2, a first power line PL1, a data line DT and a pixel circuit of a first structure. The pixel circuit of the first structure may include a plurality of transistors and a storage capacitor Cst, and the plurality of transistors may include a driving transistor T3, a data writing transistor T4, a threshold compensation transistor T2, a first reset transistor T1, a second reset transistor T7, a first light emission control transistor T5 and a second light emission control transistor T6.

[0159] exist Fig. 7A , a plurality of transistors T1 to T7 of the pixel circuit of the nth row, a second reset transistor T7' of the pixel circuit of the n-1th row, and a first reset transistor T1' of the pixel circuit of the n+1th row are illustrated. Fig. 7AAs shown, the first reset transistor T1 of the pixel circuit in the nth row is connected to the first reset control line RST1(n), the first reset control line RST1(n) is connected to the scan line GT(n-1) connected to the pixel circuit in the n-1th row, and the second reset transistor T7' of the pixel circuit in the n-1th row is connected to the first reset control line RST1(n), so as to realize the input scan signal SCAN(n-1). The first reset transistor T1' of the pixel circuit in the n+1th row is connected to the first reset control line RST1(n+1), the first reset control line RST1(n+1) is connected to the scan line GT(n) connected to the pixel circuit in the nth row, and the second reset transistor T7 of the pixel circuit in the nth row is connected to the first reset control line RST1(n+1), so as to realize the input scan signal SCAN(n).

[0160] In some exemplary embodiments, in a plane perpendicular to the display substrate, the display substrate may include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on a base substrate 50. In some examples, the semiconductor layer may include an active layer of a plurality of transistors. The first conductive layer may include a scan line GT, a first reset control line RST1, an emission control line EML, a first electrode of a storage capacitor Cst, and gates of a plurality of transistors. The second conductive layer may include a first initial signal line INIT1, a second initial signal line INIT2, a second electrode of a storage capacitor Cst, and a first shielding electrode BK. The third conductive layer may include a first power line PL1, a data line DT, and first and second electrodes of a plurality of transistors. The fourth conductive layer may include: a second shielding electrode SE and a first connection electrode CE1.

[0161] In some exemplary embodiments, Figure 7B As shown, the display substrate may include a first insulating layer 51, a second insulating layer 52, a third insulating layer 53, a fourth insulating layer 54, and a fifth insulating layer 55. The first insulating layer 51 is disposed between the base substrate 50 and the semiconductor layer, the second insulating layer 52 is disposed between the semiconductor layer and the first conductive layer, the third insulating layer 53 is disposed between the first conductive layer and the second conductive layer, the fourth insulating layer 54 is disposed between the second conductive layer and the third conductive layer, and the fifth insulating layer 55 is disposed between the third conductive layer and the fourth conductive layer. In some examples, the first insulating layer 51, the second insulating layer 52, the third insulating layer 53, and the fourth insulating layer 54 may be inorganic insulating layers, and the fifth insulating layer 55 may be an organic insulating layer. However, this embodiment is not limited to this.

[0162] Figure 7C FIG. 1 is a schematic diagram of a pixel circuit of a first structure after forming a semiconductor layer according to at least one embodiment of the present disclosure. In some exemplary embodiments, Figure 7CAs shown, the semiconductor layer of at least one sub-pixel may include: a first active layer T10 of a first reset transistor T1, a second active layer T20 of a threshold compensation transistor T2, a third active layer T30 of a driving transistor T3, a fourth active layer T40 of a data writing transistor T4, a fifth active layer T50 of a first light emission control transistor T5, a sixth active layer T60 of a second light emission control transistor T6, and a seventh active layer T70 of a second reset transistor T7. Among them, the first active layer T10 to the seventh active layer T70 are interconnected integral structures. The first active layer T10 and the seventh active layer T70' of the pixel circuit of the previous row are an integral structure, and the seventh active layer T10 and the first active layer T10' of the pixel circuit of the next row are an integral structure.

[0163] In some exemplary embodiments, Figure 7C As shown, the shape of the first active layer T10 and T10' can be "n"-shaped, the shape of the second active layer T20 can be "7"-shaped, the shape of the third active layer T30 can be "J"-shaped, the shape of the fourth active layer T40 can be "1"-shaped, and the shapes of the fifth active layer T50, the sixth active layer T06, and the seventh active layer T70 and T70' can be "L"-shaped.

[0164] In some exemplary embodiments, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region. Figure 7C As shown, the first area T10-1 of the first active layer T10 simultaneously serves as the first area of ​​the seventh active layer T70' of the seventh transistor T7' of the pixel circuit in the previous row, the second area T10-2 of the first active layer T10 simultaneously serves as the first area T20-1 of the second active layer T20, the first area T30-1 of the third active layer T30 simultaneously serves as the second area T40-2 of the fourth active layer T40 and the second area T50-2 of the fifth active layer T50, the second area T30-2 of the third active layer T30 simultaneously serves as the second area T20-2 of the second active layer T20 and the first area T60-1 of the sixth active layer T60, and the second area T60-2 of the sixth active layer T60 simultaneously serves as the second area T70-2 of the seventh active layer T70.

[0165] Fig.7D FIG. 1 is a schematic diagram of a pixel circuit of a first structure after forming a first conductive layer according to at least one embodiment of the present disclosure. In some exemplary embodiments, Fig.7DAs shown, the first conductive layer at least includes: a first electrode Cst-1 of a storage capacitor Cst, a scan line GT extending along a first direction X, a light-emitting control line EML, a first reset control line RST1(n) and RST1(n+1). The first electrode Cst-1 of the storage capacitor Cst may be rectangular, and the corners of the rectangular shape may be chamfered. The orthographic projection of the first electrode Cst-1 on the substrate and the orthographic projection of the third active layer T30 of the driving transistor T3 on the substrate overlap. The first electrode Cst-1 of the storage capacitor Cst also serves as the gate T33 of the driving transistor T3. The scan line GT, the gate T43 of the data writing transistor T4, and the gate T23 of the threshold compensation transistor T2 may be an integrated structure. The light-emitting control line EML, the gate T53 of the first light-emitting control transistor T5, and the gate T63 of the second light-emitting control transistor T6 may be an integrated structure. The first reset control line RST1(n), the gate T13 of the first reset transistor T1, and the gate T73' of the second reset transistor T7' of the previous row of pixel circuits may be an integrated structure. The first reset control line RST1(n+1), the gate T73 of the second reset transistor T7, and the gate T13' of the first reset transistor T1' of the next row of pixel circuits may be an integrated structure.

[0166] Fig. 7E FIG. 1 is a schematic diagram of a pixel circuit of a first structure after forming a second conductive layer according to at least one embodiment of the present disclosure. In some exemplary embodiments, Fig. 7E As shown, the second conductive layer at least includes: a first initial signal line INIT1, a second initial signal line INIT2, a second electrode Cst-2 of the storage capacitor Cst, and a first shielding electrode BK. The first initial signal line INIT1 and the second initial signal line INIT2 extend along the first direction X and are located on one side of the scan line GT. The second electrode Cst-2 of the storage capacitor Cst is located between the scan line GT and the light-emitting control line EML. The orthographic projection of the second electrode Cst-2 of the storage capacitor Cst on the substrate substrate overlaps with the orthographic projection of the first electrode Cst-1 on the substrate substrate. An opening OP1 is provided on the second electrode Cst-2, and the opening OP1 exposes the third insulating layer 53 covering the first electrode Cst-1, and the orthographic projection of the first electrode Cst-1 on the substrate substrate includes the orthographic projection of the opening OP1 on the substrate substrate. In some examples, the opening OP1 is configured to accommodate a first via H1 formed subsequently, and the first via H1 is located in the opening OP1 and exposes the first electrode Cst-1, so that the second electrode of the first reset transistor T1 formed subsequently is connected to the first electrode Cst-1.

[0167] In some exemplary embodiments, Fig. 7EAs shown, the first shielding electrode BK is located on the side of the scan line GT away from the storage capacitor Cst. The first shielding electrode BK is configured to shield the influence of the data voltage jump on the key node, avoid the data voltage jump affecting the potential of the key node of the pixel circuit, and improve the display effect.

[0168] Figure 7F FIG. 1 is a schematic diagram of a pixel circuit of a first structure after forming a fourth insulating layer according to at least one embodiment of the present disclosure. In some exemplary embodiments, Figure 7F As shown, a first via hole H1, a plurality of second via holes V1 to V4, and a plurality of third via holes K1 to K8 are formed on the fourth insulating layer 54. The fourth insulating layer 54 and the third insulating layer 53 in the first via hole H1 are etched away to expose the surface of the first conductive layer. The fourth insulating layer 54 in the plurality of second via holes V1 to V4 is etched away to expose the surface of the second conductive layer. The fourth insulating layer 54, the third insulating layer 53, and the second insulating layer 52 in the plurality of third via holes K1 to K8 are etched away to expose the surface of the semiconductor layer.

[0169] Figure 7G FIG. 1 is a schematic diagram of a pixel circuit of a first structure after forming a third conductive layer according to at least one embodiment of the present disclosure. In some exemplary embodiments, Figure 7G As shown, the third conductive layer may include: a data line DT, a first power line PL1, a first electrode T11 of a first reset transistor T1, a first electrode T71 of a second reset transistor T7, a first electrode T21 of a threshold compensation transistor T2, a second electrode T62 of a second light emitting control transistor T6, a first electrode T11' of a first reset transistor T1' of a next row of pixel circuits, and a first electrode T71' of a second reset transistor T7' of a previous row of pixel circuits. The data line DT and the first power line PL1 extend along the second direction Y.

[0170] In some exemplary embodiments, Figure 7F and Figure 7GAs shown, the data line DT is connected to the first area T40-1 of the fourth active layer T40 of the data writing transistor T4 through the third via hole K2. The first power line PL1 is connected to the second electrode Cst-2 of the storage capacitor Cst through the second via hole V1, connected to the first shielding electrode BK through the second via hole V2, and connected to the first area T50-1 of the fifth active layer T50 of the first light-emitting control transistor T5 through the third via hole K3. The first electrode T21 of the threshold compensation transistor T2 is connected to the first electrode Cst-1 of the storage capacitor Cst through the first via hole H1, and connected to the first area T20-1 of the second active layer T20 of the threshold compensation transistor T2 through the third via hole K1. The second electrode T62 of the second light-emitting control transistor T6 is connected to the second area T60-2 of the sixth active layer T60 of the second light-emitting control transistor T6 through the third via hole K4. The first electrode T11 of the first reset transistor T1 is connected to the first initial signal line INIT1 through the second via V3, and is connected to the first area T10-1 of the first active layer T10 of the first reset transistor T1 through the third via K5. The first electrode T71 of the second reset transistor T7 is connected to the first area T70-1 of the seventh active layer T70 of the second reset transistor T7 through the third via K8. The first electrode T11' of the first reset transistor T1' of the next row of pixel circuits is connected to the first initial signal line INIT1 through the second via V4, and is connected to the first area of ​​the first active layer T10' of the first reset transistor T1' through the third via K7. The first electrode T71' of the second reset transistor T7' of the previous row of pixel circuits is connected to the first area of ​​the first active layer T80' of the second reset transistor T7' through the third via K6. In this exemplary embodiment, the first electrode of the second reset transistor is not connected to the second initial signal line INIT2. Since the active layers of the second reset transistor of the pixel circuit of this row and the first reset transistor of the pixel circuit of the next row are an integrated structure and the first reset transistor of the pixel circuit of the next row is connected to the first initial signal line INIT1, the second reset transistor of the pixel circuit of this row is also connected to the first initial signal line INIT1.

[0171] Figure 7H Schematic diagram of a pixel circuit of a first structure after forming a fifth insulating layer according to at least one embodiment of the present disclosure. In some exemplary embodiments, a plurality of fourth via holes F1 to F2 are formed on the fifth insulating layer 55. The fifth insulating layer 55 in the plurality of fourth via holes F1 to F2 is removed to expose the surface of the third conductive layer.

[0172] Fig.7IThe schematic diagram of the pixel circuit of the first structure after forming the fourth conductive layer of at least one embodiment of the present disclosure. In some exemplary embodiments, the fourth conductive layer at least includes: a second shielding electrode SE and a first transfer electrode CE1. The first transfer electrode CE1 is connected to the second electrode T62 of the second light-emitting control transistor T6 through a fourth via F1. The first transfer electrode CE1 can be directly connected to the first area light-emitting element, or connected to the second transfer electrode of the first area light-emitting element, or connected to the second transfer electrode of the second area light-emitting element through a conductive line. The second shielding electrode SE is connected to the first power line PL1 through a fourth via F2. The orthographic projection of the second shielding electrode SE on the base substrate partially overlaps with the orthographic projection of the driving transistor T3 on the base substrate. The second shielding electrode SE is configured to shield the influence of the conductive line on the driving transistor T3 to improve the display effect.

[0173] Fig. 8A It is a plan view of a pixel circuit of a second structure according to at least one embodiment of the present disclosure. Figure 8B for Fig. 8A Schematic diagram of the local section along the QQ direction. Figure 8C This is a schematic diagram of a pixel circuit of a second structure after forming a semiconductor layer according to at least one embodiment of the present disclosure. Fig.8D The diagram is a schematic diagram of a pixel circuit of a second structure after forming a first conductive layer according to at least one embodiment of the present disclosure. Fig. 8E The diagram is a schematic diagram of a pixel circuit of a second structure after forming a second conductive layer according to at least one embodiment of the present disclosure. Figure 8F The diagram is a schematic diagram of a pixel circuit of a second structure after forming a fourth insulating layer according to at least one embodiment of the present disclosure. Figure 8G The diagram is a schematic diagram of a pixel circuit of a second structure after forming a third conductive layer according to at least one embodiment of the present disclosure. Figure 8H This is a schematic diagram of a pixel circuit of a second structure after forming a fifth insulating layer according to at least one embodiment of the present disclosure. Fig.8I This is a schematic diagram of a pixel circuit of a second structure after forming a fourth conductive layer according to at least one embodiment of the present disclosure.

[0174] exist Fig. 8A , a plurality of transistors T1 to T7 of the pixel circuit of the nth row, a second reset transistor T7' of the pixel circuit of the n-1th row, and a first reset transistor T1' of the pixel circuit of the n+1th row are illustrated. Fig. 7AAs shown, the first reset transistor T1 of the pixel circuit in the nth row is connected to the first reset control line RST1(n), the first reset control line RST1(n) is connected to the scan line GT(n-1) connected to the pixel circuit in the n-1th row, and the second reset transistor T7' of the pixel circuit in the n-1th row is connected to the first reset control line RST1(n), so as to realize the input scan signal SCAN(n-1). The first reset transistor T1' of the pixel circuit in the n+1th row is connected to the first reset control line RST1(n+1), the first reset control line RST1(n+1) is connected to the scan line GT(n) connected to the pixel circuit in the nth row, and the second reset transistor T7 of the pixel circuit in the nth row is connected to the first reset control line RST1(n+1), so as to realize the input scan signal SCAN(n).

[0175] In some exemplary embodiments, FIG. 8A to FIG. 8I As shown, the first active layer T10 of the first reset transistor T1, the second active layer T20 of the threshold compensation transistor T2, the third active layer T30 of the driving transistor T3, the fourth active layer T40 of the data writing transistor T4, the fifth active layer T50 of the first light emission control transistor T5, the sixth active layer T60 of the second light emission control transistor T6, and the seventh active layer T70 of the second reset transistor T7 are interconnected as an integrated structure. The first active layer T10 of the pixel circuit of this row is independent of the seventh active layer T70' of the pixel circuit of the previous row, and the seventh active layer T10 of the pixel circuit of this row is independent of the first active layer T10' of the pixel circuit of the next row. The first electrode T71 of the second reset transistor T7 of the pixel circuit of the second structure is connected to the second initial signal line INIT2 through the second via hole V5, and is connected to the first area T70-1 of the seventh active layer T70 of the second reset transistor T7 through the third via hole K8. The first electrode T11 of the first reset transistor T1 of the pixel circuit of the second structure is connected to the first initial signal line INIT1 through the second via V3, and is connected to the first area T10-1 of the first active layer T10 of the first reset transistor T1 through the third via K5. The first electrode T71' of the second reset transistor T7' of the pixel circuit of the previous row is connected to the second initial signal line INIT2 through the second via V6, and is connected to the first area of ​​the seventh active layer T70' of the second reset transistor T7' through the third via K6. The first electrode T11' of the first reset transistor T1' of the pixel circuit of the next row is connected to the first initial signal line INIT1 through the second via V4, and is connected to the first area of ​​the first active layer T10' of the first reset transistor T1' through the third via K7.

[0176] The remaining planar structures of the pixel circuit of the second structure may refer to the relevant description of the pixel circuit of the first structure, so they will not be described again here.

[0177] In this exemplary embodiment, the active layer of the second reset transistor of the pixel circuit of the first structure is connected to the active layer of the first reset transistor of the pixel circuit of the next row to realize that the second reset transistor is connected to the first initial signal line, and the active layer of the second reset transistor of the pixel circuit of the second structure is disconnected from the active layer of the first reset transistor of the pixel circuit of the next row, and the active layer of the second reset transistor is directly connected to the second initial signal line to realize that the second reset transistor is connected to the second initial signal line. The layout design of the pixel circuit provided in this exemplary embodiment can realize the spacing arrangement of the first type of pixel circuit and the second type of pixel circuit on the substrate.

[0178] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. "The orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0179] In some exemplary embodiments, a process of preparing a display substrate may include the following operations.

[0180] (1) Forming a semiconductor layer pattern.

[0181] In some exemplary embodiments, forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a base substrate 50, patterning the semiconductor film through a patterning process, forming a first insulating layer 51 covering the base substrate 50, and a semiconductor layer disposed on the first insulating layer 51, such as Figure 7B and Figure 8B shown.

[0182] After this process, the display substrate includes a first insulating layer 51 disposed on the base substrate 50 and a semiconductor layer disposed on the first insulating layer 51. The semiconductor layer may include an active layer of a plurality of transistors of the pixel circuit, such as Figure 7C and Figure 8C In this exemplary embodiment, the active layer of the second reset transistor of the pixel circuit of the first structure is an integral structure with the active layer of the first reset transistor of the adjacent pixel circuit, and the active layer of the second reset transistor of the pixel circuit of the second structure is independent of the active layer of the first reset transistor of the adjacent pixel circuit.

[0183] (2) Forming a first conductive layer pattern.

[0184] In some exemplary embodiments, forming the first conductive layer pattern may include: depositing a second insulating film and a first metal film in sequence on the substrate 50 on which the aforementioned pattern is formed, patterning the first metal film through a patterning process, forming a second insulating layer 52 covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer 52. Fig.7D and Fig.8D As shown, the first conductive layer pattern at least includes: a first reset control line RST1, a scan line GT, a light emitting control line EML, and a first electrode Cst-1 of a storage capacitor Cst. The first reset control line RST1, the scan line GT, and the light emitting control line EML extend along a first direction X, and the first electrode Cst-1 of the storage capacitor Cst is located between the scan line GT and the light emitting control line EML. In some examples, the first conductive layer may be referred to as a first gate metal (GATE 1) layer.

[0185] In some exemplary embodiments, after forming the first conductive layer pattern, the semiconductor layer can be conductorized using the first conductive layer as a shield, the semiconductor layer in the area shielded by the first conductive layer forms a channel region of multiple transistors, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the first active layer T10 to the seventh active layer T70 are all conductorized.

[0186] (3) Forming a second conductive layer pattern.

[0187] In some exemplary embodiments, forming the second conductive layer pattern may include: depositing a third insulating film and a second metal film in sequence on the substrate 50 having the aforementioned pattern, patterning the second metal film using a patterning process, forming a third insulating layer 53 covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer 53. Fig. 7E and Fig. 8E As shown, the second conductive layer pattern includes at least: a first initial signal line INIT1, a second initial signal line INIT2, a second electrode Cst-2 of a storage capacitor Cst, and a first shielding electrode BK. In some examples, the second conductive layer may be referred to as a second gate metal (GATE 2) layer.

[0188] (4) Forming a fourth insulating layer pattern.

[0189] In some exemplary embodiments, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate 50 on which the aforementioned pattern is formed, and patterning the fourth insulating film using a patterning process to form a fourth insulating layer 54 covering the second conductive layer. Figure 7F and Figure 8F As shown, a plurality of first via holes, a plurality of second via holes, and a plurality of third via holes are provided on the fourth insulating layer. The fourth insulating layer 54 and the third insulating layer 53 in the plurality of first via holes are etched away to expose the surface of the first conductive layer, the fourth insulating layer 54 in the plurality of second via holes is etched away to expose the surface of the second conductive layer, and the fourth insulating layer 54, the third insulating layer 53, and the second insulating layer 52 in the plurality of third via holes are etched away to expose the surface of the semiconductor layer.

[0190] (5) Forming a third conductive layer pattern.

[0191] In some exemplary embodiments, forming the third conductive layer may include: depositing a third metal film on the substrate 50 having the aforementioned pattern formed thereon, and patterning the third metal film using a patterning process to form a third conductive layer disposed on the fourth insulating layer 54. Figure 7G and Figure 8G As shown, the third conductive layer at least includes: a data line DT, a first power line PL1, and first and second electrodes of a plurality of transistors. In some examples, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0192] In this example, if Figure 7G As shown, the first electrode T71 of the second reset transistor T7 of the pixel circuit of the first structure is not connected to the second initial signal line INIT2. Figure 8G As shown, the first electrode T71 of the second reset transistor T7 of the pixel circuit of the second structure is connected to the second initial signal line INIT2 through the second via hole V5.

[0193] (6) Forming a fifth insulating layer pattern.

[0194] In some exemplary embodiments, forming the fifth insulating layer pattern may include: coating a flat film on the base substrate 50 on which the aforementioned pattern is formed, and patterning the flat film using a patterning process to form a fifth insulating layer 55 covering the third conductive layer. Figure 7H and Figure 8H As shown, a plurality of fourth via holes F1 and F2 are formed on the fifth insulating layer 55. The fifth insulating layer 55 in the plurality of fourth via holes is removed to expose the surface of the third conductive layer. In some examples, the fifth insulating layer 55 may be referred to as a planar layer.

[0195] (7) Forming a fourth conductive layer pattern.

[0196] In some exemplary embodiments, forming the fourth conductive layer pattern may include: depositing a fourth metal film on the substrate 50 on which the aforementioned pattern is formed, and patterning the fourth metal film using a patterning process to form a fourth conductive layer disposed on the fifth insulating layer 55. Fig.7I and Fig.8I As shown, the fourth conductive layer pattern at least includes: a first connection electrode CE1 and a second shielding electrode SE. The second shielding electrode SE is connected to the first power line PL1 through a fourth via F2, and the first connection electrode CE1 is connected to the second electrode T62 of the second light emitting control transistor T6 through the fourth via F1. In some examples, the fourth conductive layer can be referred to as a second source-drain metal (SD1) layer.

[0197] In some exemplary embodiments, the subsequent preparation process may include: forming a conductive line layer. In some examples, the plurality of conductive lines connecting the second type pixel circuit of the first display area and the second area light-emitting element of the second display area may be a same-layer structure. Forming the conductive line layer may include: coating a flat film on the substrate substrate forming the fourth conductive layer, patterning the flat film using a patterning process, and forming a sixth insulating layer covering the fourth conductive layer; then, depositing a transparent conductive film, patterning the transparent conductive film using a patterning process, and forming a conductive line layer disposed on the sixth insulating layer. The first connection electrode CE1 of the second type pixel circuit of the first display area R1 is connected to the conductive line, and the conductive line can extend from the first display area R1 to the second display area R2 so as to be connected to the second area light-emitting element of the second display area R2. However, this embodiment is not limited to this. In some examples, the plurality of conductive lines connecting the second type pixel circuit of the first display area R1 and the second area light-emitting element of the second display area R2 may be a different-layer structure. Alternatively, at least one conductive line may be formed by connecting a plurality of conductive line segments located in different conductive line layers.

[0198] In some exemplary embodiments, the preparation process after forming the conductive line layer may include: forming a flat layer covering the conductive line layer; depositing a transparent conductive film, patterning the transparent conductive film by a patterning process to form an anode disposed on the flat layer; coating a pixel definition film, patterning the pixel definition film by a patterning process to form a pixel definition layer, wherein the pixel definition layer of each sub-pixel is provided with a pixel opening, and the pixel opening exposes the anode. An organic light-emitting layer is formed by an evaporation or inkjet printing process, and a cathode is formed on the organic light-emitting layer. An encapsulation layer is formed, and the encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together, wherein the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials, and the second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer, so as to ensure that external water vapor cannot enter the light-emitting element.

[0199] In some exemplary embodiments, the substrate substrate 50 may be a flexible substrate substrate, or may be a rigid substrate substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked, and the materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate substrate, and the material of the semiconductor layer may be amorphous silicon (a-si).

[0200] In some exemplary embodiments, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer 51, the second insulating layer 52, the third insulating layer 53 and the fourth insulating layer 54 may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer. The first insulating layer 51 is called a buffer layer, which is used to improve the water and oxygen resistance of the substrate, the second insulating layer 52 and the third insulating layer 53 are called gate insulating (GI) layers, and the fourth insulating layer 54 is called an interlayer insulating (ILD) layer. The flat layer may be made of organic materials. The transparent conductive film may be made of indium tin oxide (ITO) or indium zinc oxide (IZO). The active layer may be made of polysilicon (p-Si), that is, this embodiment is applicable to LTPS thin film transistors. However, this embodiment is not limited to this. For example, the transistors in the pixel circuit of the first structure and the pixel circuit of the second structure may both be oxide thin film transistors.

[0201] The structure of the display substrate of this embodiment and its preparation process are merely exemplary. In some exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, the pixel circuit of the first structure and the pixel circuit of the second structure may include other numbers of transistors and storage capacitors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure or a 9T2C structure, or the number of transistors is less than 7.

[0202] The structure (or method) described in this embodiment mode can be combined with the structure (or method) described in other embodiment modes as appropriate.

[0203] In some exemplary embodiments, in the pixel circuit of the first structure and the pixel circuit of the second structure, the first reset transistor T1 and the threshold compensation transistor T2 may be oxide thin film transistors, and the remaining transistors (i.e., the driving transistor T3, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, and the second reset transistor T7) may be low-temperature polysilicon thin film transistors, thereby forming an LTPO display substrate. In this example, the active layer of the first reset transistor T1 and the threshold compensation transistor T2 may be a same-layer structure, and the active layer of the remaining transistors may be a different-layer structure. The active layer of the second reset transistor T7 of the pixel circuit of the first structure in the nth row and the active layer of the first reset transistor T1 of the pixel circuit of the n+1th row are different-layer structures and isolated from each other, and the second reset transistor T7 and the first reset transistor T1 of the pixel circuit of the first structure are each connected to the first initial signal line INIT1. The active layers of the second reset transistor T7 of the pixel circuit of the second structure in the nth row and the first reset transistor T1 of the pixel circuit of the n+1th row are of different layer structures and isolated from each other, the second reset transistor T7 of the pixel circuit of the second structure is connected to the second initial signal line INIT2, and the first reset transistor T1 is connected to the first initial signal line INIT1. In some examples, the first reset transistor T1 and the threshold compensation transistor T2 may be N-type transistors, and the remaining transistors may be P-type transistors. In a plane perpendicular to the display substrate, the display substrate may include: a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially arranged on the base substrate. Among them, the first semiconductor layer at least includes: an active layer of multiple P-type transistors; the first conductive layer at least includes: gates of multiple P-type transistors, a first electrode of a storage capacitor, a scan line, a light-emitting control line, and a second reset control line; the second semiconductor layer at least includes: an active layer of multiple N-type transistors; the second conductive layer at least includes: a second electrode of a storage capacitor, a first reset control line; the third conductive layer at least includes: a first pole and a second pole of multiple transistors, a first power line, a data line, a first initial signal line, and a second initial signal line; the fourth conductive layer at least includes: a first connecting electrode. An insulating layer is provided between adjacent semiconductor layers and conductive layers, and an insulating layer is provided between adjacent conductive layers. However, this embodiment is not limited to this.

[0204] Fig. 9 Another schematic diagram of a row of light emitting elements and second type pixel circuits connected thereto in the second display region of a display substrate of at least one embodiment of the present disclosure is shown in FIG. Fig. 9 Only the connection relationship between a row of light emitting elements in the left half of the second display area R2 and the second type pixel circuit in the first display area R1 is illustrated.

[0205] In some exemplary embodiments, Fig. 9 As shown, in the second display area R2, the plurality of second region light emitting elements 40 include: a plurality of first light emitting elements 41, a plurality of second light emitting elements 42, and a plurality of third light emitting elements 43. The first light emitting element 41 is configured to emit a first color light, the second light emitting element 42 is configured to emit a second color light, and the third light emitting element 43 is configured to emit a third color light. In some examples, the first color light is green (G) light, the second color light is red (R) light, and the third color light is blue (B) light. However, this embodiment is not limited to this.

[0206] In some exemplary embodiments, Fig. 9 As shown, in the first display area R1, the plurality of second type pixel circuits 20 include: a plurality of first pixel circuits 21, a plurality of second pixel circuits 22, and a plurality of third pixel circuits 23. The plurality of first light-emitting elements 41 are connected to the plurality of first pixel circuits 21 through a plurality of first conductive lines La, the plurality of second light-emitting elements 42 are connected to the plurality of second pixel circuits 22 through a plurality of second conductive lines Lb, and the plurality of third light-emitting elements 43 are connected to the plurality of third pixel circuits 23 through a plurality of third conductive lines Lc. For example, a first light-emitting element 41 is connected to a first pixel circuit 21 through a first conductive line La, a second light-emitting element 42 is connected to a second pixel circuit 22 through a second conductive line Lb, and a third light-emitting element 43 is connected to a third pixel circuit 23 through a third conductive line Lc. However, this embodiment is not limited to this.

[0207] In some exemplary embodiments, Fig. 9As shown, in a group of second-region light-emitting elements 40 and a group of second-type pixel circuits 20, a plurality of first pixel circuits 21 connected to a plurality of first light-emitting elements 41 are closer to the second display area R2 than each of a plurality of second pixel circuits 22 connected to a plurality of second light-emitting elements 42, and closer to the second display area R2 than each of a plurality of third pixel circuits 23 connected to a plurality of third light-emitting elements 43. In some examples, the second pixel circuit 22 connected to the second light-emitting element 42 and the third pixel circuit 23 connected to the third light-emitting element 43 may both be pixel circuits of the second structure, and the lengths of the second conductive line Lb and the third conductive line Lc are both greater than the length delimiting value. The first pixel circuit 21 connected to the first conductive line La whose length is less than the length delimiting value may be a pixel circuit of the first structure, and the first pixel circuit 21 connected to the first conductive line La whose length is greater than the length delimiting value may be a pixel circuit of the second structure. However, this embodiment is not limited to this. In some examples, when the length of the first conductive line La is less than the length delimiting value, and the length of a portion of the second conductive line Lb and a portion of the third conductive line Lc is greater than the length delimiting value, the first pixel circuit 21 connected to the first conductive line La is a pixel circuit of the first structure, the pixel circuit connected to the second conductive line Lb and the third conductive line Lc whose length is less than the length delimiting value is a pixel circuit of the first structure, and the pixel circuit connected to the second conductive line Lb and the third conductive line Lc whose length is greater than the length delimiting value is a pixel circuit of the second structure.

[0208] The remaining structures of the display substrate of this embodiment can refer to the description of the above embodiments, so they are not described here in detail. The structure (or method) shown in this embodiment can be appropriately combined with the structures (or methods) shown in other embodiments.

[0209] Fig.10 Another schematic diagram of a row of light emitting elements and second type pixel circuits connected thereto in the second display region of a display substrate of at least one embodiment of the present disclosure is shown in FIG. Fig. 9 Only the connection relationship between a row of light emitting elements in the left half of the second display area R2 and the second type pixel circuit in the first display area R1 is illustrated.

[0210] In some exemplary embodiments, Fig.10As shown, in a group of second-region light-emitting elements 40 and a group of second-type pixel circuits 20, a plurality of second pixel circuits 22 connected to a plurality of second light-emitting elements 42, a plurality of first pixel circuits 21 connected to a plurality of first light-emitting elements 41, and a plurality of third pixel circuits 23 connected to a plurality of third light-emitting elements 43 are arranged alternately in sequence. In this example, the first pixel circuit 21 connected to the first conductive line La whose length is less than the length delimiting value may be a pixel circuit of the first structure, and the first pixel circuit 21 connected to the first conductive line La whose length is greater than the length delimiting value may be a pixel circuit of the second structure. The second pixel circuit 22 connected to the second conductive line Lb whose length is less than the length delimiting value may be a pixel circuit of the first structure, and the second pixel circuit 21 connected to the second conductive line Lb whose length is greater than the length delimiting value may be a pixel circuit of the second structure. The third pixel circuit 23 connected to the third conductive line Lc whose length is less than the length delimiting value may be a pixel circuit of the first structure, and the third pixel circuit 23 connected to the third conductive line Lc whose length is greater than the length delimiting value may be a pixel circuit of the second structure.

[0211] The remaining structures of the display substrate of this embodiment can refer to the description of the above embodiments, so they are not described here in detail. The structure (or method) shown in this embodiment can be appropriately combined with the structures (or methods) shown in other embodiments.

[0212] Fig.11 Schematic diagram of a display substrate of at least one embodiment of the present disclosure. In some exemplary embodiments, the first display area R1 includes an auxiliary area Ra. The area of ​​the auxiliary area Ra may be smaller than the area of ​​the first display area R1 except the auxiliary area Ra. The auxiliary area Ra surrounds the second display area R2. A plurality of first-type pixel circuits and a plurality of first-region light-emitting elements are located in the first display area R1. At least one first-type pixel circuit among the plurality of first-type pixel circuits may be connected to at least one first-region light-emitting element among the plurality of first-region light-emitting elements, and the orthographic projection of at least one first-type pixel circuit on the substrate substrate may overlap at least partially with the orthographic projection of at least one first-region light-emitting element on the substrate substrate. The first-type pixel circuit may be a pixel circuit of a first structure. A plurality of second-type pixel circuits are located in the auxiliary area Ra. A plurality of second-region light-emitting elements are located in the second display area. At least one second-type pixel circuit among the plurality of second-type pixel circuits may be connected to at least one second-region light-emitting element among the plurality of second-region light-emitting elements through a conductive line. The second-type pixel circuit connected to the conductive line having a length less than the length delimiting value may be a pixel circuit of the first structure, and the second-type pixel circuit connected to the conductive line having a length greater than or equal to the length delimiting value may be a pixel circuit of the second structure.

[0213] The remaining structures of the display substrate of this embodiment can refer to the description of the above embodiments, so they are not described here in detail. The structure (or method) shown in this embodiment can be appropriately combined with the structures (or methods) shown in other embodiments.

[0214] The disclosed embodiment also provides a method for preparing a display substrate, comprising: forming a plurality of second-type pixel circuits in a first display area of ​​a base substrate, forming a plurality of second-region light-emitting elements in a second display area, and the first display area is located on at least one side of the second display area. The plurality of second-type pixel circuits include a plurality of pixel circuits of a first structure and a plurality of pixel circuits of a second structure. At least one pixel circuit among the plurality of pixel circuits of the first structure is connected to at least one light-emitting element among the plurality of second-region light-emitting elements through a first group of conductive lines. At least one pixel circuit among the plurality of pixel circuits of the second structure is connected to at least one light-emitting element among the plurality of second-region light-emitting elements through a second group of conductive lines. The length of the second group of conductive lines is greater than the length of the first group of conductive lines.

[0215] The method for preparing the display substrate of this embodiment can refer to the description of the aforementioned embodiment, so it will not be described again here.

[0216] Fig.12 FIG. 1 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Fig.12 As shown, this embodiment provides a display device 91, including the display substrate 910 of the above embodiment. In some examples, the display substrate 910 can be an OLED display substrate. The display device 91 can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame or a navigator. However, this embodiment is not limited to this.

[0217] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments.

[0218] Those skilled in the art should understand that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.

Claims

1. A display substrate, comprising: A base substrate having a first display area and a second display area, wherein the first display area is located on at least one side of the second display area; A plurality of second area light emitting elements, located in the second display area; A plurality of second type pixel circuits, located in the first display area; The plurality of second-type pixel circuits include a plurality of first-structure pixel circuits and a plurality of second-structure pixel circuits; At least one pixel circuit among the plurality of pixel circuits of the first structure is connected to at least one light emitting element among the plurality of light emitting elements in the second region through a first group of conductive lines; At least one pixel circuit among the plurality of pixel circuits of the second structure is connected to at least one light emitting element among the plurality of light emitting elements in the second region through a second group of conductive lines; The length of the second group of conductive wires is greater than the length of the first group of conductive wires; The pixel circuit of the first structure is connected to the first initial signal line, and the pixel circuit of the second structure is connected to the first initial signal line and the second initial signal line; the first initial signal line and the second initial signal line provide different initial signals; The first initial signal provided by the first initial signal line and the second initial signal provided by the second initial signal line are constant voltage signals, and the second initial signal is greater than the first initial signal; Alternatively, the magnitude of the second initial signal provided by the second initial signal line connected to the pixel circuit of the second structure is proportional to the length of the second group of conductive lines connected to the pixel circuit of the second structure.

2. The display substrate according to claim 1, further comprising: A plurality of first-area light-emitting elements, located in the first display area; A plurality of first type pixel circuits, located in the first display area; At least one first-type pixel circuit among the plurality of first-type pixel circuits is connected to at least one first-region light-emitting element among the plurality of first-region light-emitting elements, and an orthographic projection of the at least one first-type pixel circuit on the substrate at least partially overlaps with an orthographic projection of the at least one first-region light-emitting element on the substrate; The plurality of first-type pixel circuits are all pixel circuits of a first structure.

3. The display substrate according to claim 1, wherein: The pixel circuit of the first structure includes: a driving transistor, a first reset transistor and a second reset transistor; The gate of the first reset transistor is connected to the first reset control line, the first electrode of the first reset transistor is connected to the gate of the driving transistor, and the second electrode of the first reset transistor is connected to the first initial signal line; A gate of the second reset transistor is connected to a second reset control line, a first electrode of the second reset transistor is connected to a first electrode of the light emitting element, and a second electrode of the second reset transistor is connected to a first initial signal line.

4. The display substrate according to claim 1, wherein: The pixel circuit of the second structure includes: a driving transistor, a first reset transistor and a second reset transistor; The gate of the first reset transistor is connected to the first reset control line, the first electrode of the first reset transistor is connected to the gate of the driving transistor, and the second electrode of the first reset transistor is connected to the first initial signal line; The gate of the second reset transistor is connected to the second reset control line, the first electrode of the second reset transistor is connected to the first electrode of the light emitting element, and the second electrode of the second reset transistor is connected to the second initial signal line; The second initial signal provided by the second initial signal line is different from the first initial signal provided by the first initial signal line.

5. The display substrate according to claim 4, wherein: The pixel circuit of the first structure or the pixel circuit of the second structure further includes: a data writing transistor, a threshold compensation transistor, a first light emission control transistor and a second light emission control transistor; The gate of the data writing transistor is connected to the scan line, the first electrode of the data writing transistor is connected to the data line, and the second electrode of the data writing transistor is connected to the first electrode of the driving transistor; The gate of the threshold compensation transistor is connected to the scan line, the first electrode of the threshold compensation transistor is connected to the gate of the driving transistor, and the second electrode of the threshold compensation transistor is connected to the second electrode of the driving transistor; The gate of the first light emission control transistor is connected to the light emission control line, the first electrode of the first light emission control transistor is connected to the first power supply line, and the second electrode of the first light emission control transistor is connected to the first electrode of the driving transistor; A gate of the second light emission control transistor is connected to a light emission control line, a first electrode of the second light emission control transistor is connected to a second electrode of the driving transistor, and a second electrode of the second light emission control transistor is connected to a first electrode of the light emitting element.

6. The display substrate according to claim 5, wherein: In a plane perpendicular to the display substrate, the display substrate at least comprises: a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer arranged on a base substrate; The semiconductor layer at least includes: an active layer of a plurality of transistors; The first conductive layer at least includes: gates of a plurality of transistors and a first electrode of a storage capacitor, a scan line, a light emitting control line, a first reset control line and a second reset control line; The second conductive layer at least includes: a second electrode of the storage capacitor, a first initial signal line, and a second initial signal line; The third conductive layer at least includes: first electrodes and second electrodes of a plurality of transistors, a first power line, and a data line.

7. The display substrate according to claim 6, wherein: The active layers of the first reset transistor and the second reset transistor of the pixel circuit of the first structure are an integrated structure; the second reset transistor of the pixel circuit of the nth row of the first structure and the active layer of the first reset transistor of the pixel circuit of the n+1th row are an integrated structure, and n is a positive integer.

8. The display substrate according to claim 6 or 7, wherein: The active layers of the first reset transistor and the second reset transistor of the pixel circuit of the second structure are an integrated structure; the active layer of the second reset transistor of the pixel circuit of the nth row of the second structure is not connected to the active layer of the first reset transistor of the pixel circuit of the n+1th row, and n is a positive integer.

9. The display substrate according to claim 6, wherein: The third conductive layer includes: a second electrode of a second reset transistor of the pixel circuit of the second structure, and a second electrode of a second reset transistor of the pixel circuit of the first structure; The second electrode of the second reset transistor of the pixel circuit of the second structure is connected to the second initial signal line through a via hole; The second electrode of the second reset transistor in the pixel circuit of the first structure is not connected to the second initial signal line.

10. The display substrate according to claim 1, wherein: The first group of conductive lines and the second group of conductive lines are made of transparent conductive material.

11. The display substrate according to claim 1, wherein: The plurality of second-type pixel circuits are distributed between the plurality of first-type pixel circuits at intervals.

12. The display substrate according to claim 11, wherein: Among the plurality of first-type pixel circuits and the plurality of second-type pixel circuits, a size of any pixel circuit in the first direction is smaller than a size of the first-region light-emitting element in the first direction.

13. The display substrate according to claim 11 or 12, wherein: The plurality of second-region light-emitting elements include a plurality of groups of second-region light-emitting elements, the second-region light-emitting elements in each group are arranged along the first direction, and the plurality of groups of second-region light-emitting elements are arranged along the second direction; The plurality of second-type pixel circuits include a plurality of groups of second-type pixel circuits, the second-type pixel circuits in each group are arranged along the first direction, and the plurality of groups of second-type pixel circuits are arranged along the second direction; The plurality of second region light emitting elements at least include: a plurality of first light emitting elements, a plurality of second light emitting elements and a plurality of third light emitting elements; The plurality of second-type pixel circuits include: a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits; a plurality of first light-emitting elements are connected to the plurality of first pixel circuits, a plurality of second light-emitting elements are connected to the plurality of second pixel circuits, and a plurality of third light-emitting elements are connected to the plurality of third pixel circuits; In at least one group of second-area light-emitting elements and at least one group of second-type pixel circuits, a plurality of first pixel circuits connected to a plurality of first light-emitting elements are closer to the second display area than each of a plurality of second pixel circuits connected to a plurality of second light-emitting elements, and are closer to the second display area than each of a plurality of third pixel circuits connected to a plurality of third light-emitting elements.

14. The display substrate according to claim 13, wherein: The second pixel circuit connected to the second light-emitting element through the second group of conductive lines is a pixel circuit of the second structure, the third pixel circuit connected to the third light-emitting element through the second group of conductive lines is a pixel circuit of the second structure, the first pixel circuit connected to the first light-emitting element through the first group of conductive lines is a pixel circuit of the first structure, and the first pixel circuit connected to the first light-emitting element through the second group of conductive lines is a pixel circuit of the second structure.

15. The display substrate according to claim 14, wherein: The first light emitting element is configured to emit green light, one of the second light emitting element and the third light emitting element is configured to emit red light, and the other of the second light emitting element and the third light emitting element is configured to emit blue light.

16. The display substrate according to claim 1, wherein: The length of the first group of conductive lines is less than a length delimiting value, and the length of the second group of conductive lines is greater than or equal to the length delimiting value; the ratio of the length delimiting value to the maximum length of the second group of conductive lines is approximately 0.25 to 0.

35.

17. A display device comprising the display substrate according to any one of claims 1 to 16.

18. The display device according to claim 17, further comprising: The photosensitive sensor is located on one side of the display substrate, and the orthographic projection of the photosensitive sensor on the display substrate overlaps with the second display area of ​​the display substrate.

19. A method for preparing a display substrate, comprising: Forming a plurality of second-type pixel circuits in a first display area of ​​the base substrate, and forming a plurality of second-region light-emitting elements in a second display area, wherein the first display area is located on at least one side of the second display area; The plurality of second-type pixel circuits include a plurality of first-structure pixel circuits and a plurality of second-structure pixel circuits; at least one pixel circuit among the plurality of first-structure pixel circuits is connected to at least one light-emitting element among the plurality of second-region light-emitting elements through a first group of conductive lines; at least one pixel circuit among the plurality of second-structure pixel circuits is connected to at least one light-emitting element among the plurality of second-region light-emitting elements through a second group of conductive lines; and the length of the second group of conductive lines is greater than the length of the first group of conductive lines; The pixel circuit of the first structure is connected to the first initial signal line, and the pixel circuit of the second structure is connected to the first initial signal line and the second initial signal line; the first initial signal line and the second initial signal line provide different initial signals; The first initial signal provided by the first initial signal line and the second initial signal provided by the second initial signal line are constant voltage signals, and the second initial signal is greater than the first initial signal; Alternatively, the magnitude of the second initial signal provided by the second initial signal line connected to the pixel circuit of the second structure is proportional to the length of the second group of conductive lines connected to the pixel circuit of the second structure.

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