Reference current circuit, charge compensation method and chip

Abstract

The present invention discloses a reference current circuit, a charge compensation method, and a chip. The reference current circuit includes: a reference current generating unit, a reference current replicating unit, and a tracking compensation unit. The reference current replicating unit includes a first MOS transistor, a second MOS transistor, and a third MOS transistor connected in common gate fashion. The drains of the first and second MOS transistors are connected to the reference current generating unit, and the drain of the third MOS transistor is used to access a functional unit. A detection circuit is connected to the drain of the third MOS transistor. A clamping circuit is connected to the detection circuit. A compensation circuit is connected to the detection circuit, the clamping circuit, and the gate of the first MOS transistor. The reference current circuit of the present invention compensates for the charge injected or extracted during switching of the reference current IBIAS, thereby ensuring that the switched reference current IBIAS can be established at an extremely fast speed at a low cost (almost no DC power consumption) and greatly reducing the impact on the transient state of other reference currents IBIAS.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a reference current circuit, a charge compensation method and a chip. Background Art

[0002] In the internal circuit of the chip, the reference current circuit is an important component of the reference current source. Figure 1 As shown, the reference current generating unit IBIAS_GENERATE generates a specific reference current in the loop, and then uses the current mirror to obtain reference currents of different sizes Iref_1 and Iref_2 (nA level) and send them to the functional units Module_1 and Module_2 respectively (if the switch S1 is closed at this time). Figure 1 In the design, the currents I1 and I2 generated by the loop containing the reference current generating unit IBIAS_GENERATE are set at only nA levels. This setting has the advantage of extremely low power consumption when other unit circuits are turned off. However, it has the disadvantage of low loop bandwidth. When a functional unit is added, causing the corresponding reference current to change (for example, switch S1 switches from an open state to a closed state, connecting functional unit Module_2 to the circuit), the gate-source parasitic capacitance Cgs and gate-drain parasitic capacitance Cgd of the corresponding MOS transistor of the added functional unit will affect the voltage at the connection point VBP. This, in turn, will affect the magnitudes of other reference currents (for example, reference current Iref_1) during the transient state of the reference current change. The loop containing the reference current generating unit IBIAS_GENERATE will take a long time to adjust to the required settling accuracy.

[0003] In order to reduce the impact of the newly added power unit on the VBP voltage value, the following is proposed Figure 2 The technical solution shown in FIG. 1 connects a large capacitor Cx between the connection point VBP and the power supply voltage VDD. A resistor Rx is also connected in series with the gate of the MOS transistor MP2 in the switched reference current branch. Increasing the capacitor Cx can reduce the change in the voltage at the connection point VBP when the MOS transistor MP2 injects or extracts charge from or into the connection point VBP. Increasing the resistor Rx can slow the rate at which the MOS transistor MP2 injects or extracts charge from or into the connection point VBP, thereby reducing the impact on the voltage at the connection point VBP. However, a larger capacitor Cx significantly increases the chip area and significantly reduces the bandwidth of the loop in which the reference current generating unit IBIAS_GENERATE resides. Furthermore, increasing the resistor Rx cannot guarantee the speed at which the reference current Iref_2 is established.

[0004] like Figure 1As shown, when the second reference current Iref_2 output by the reference current generating unit IBIAS_GENERATE to the functional unit Module_2 switches, the circuit has two requirements for the switching of the second reference current Iref_2: first, when the switch S1 on the branch corresponding to the second reference current Iref_2 is closed and opened, the impact on the first reference current Iref_1 is as small as possible; second, when the switch on the branch corresponding to the second reference current Iref_2 is closed, the second reference current Iref_2 can be established as quickly as possible.

[0005] Therefore, if the voltage at the connection point VBP can be kept as unchanged as possible when the second reference current Iref_2 switches, it is avoided that the voltage at the connection point VBP is adjusted only through the loop where the reference current generating unit IBIAS_GENERATE with a nA current is located. This can eliminate the impact of the switching of the second reference current Iref_2 on the first reference current Iref_1, while allowing the second reference current Iref_2 to be established as quickly as possible.

[0006] The information disclosed in this background technology section is only intended to enhance understanding of the overall background of the invention and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the Invention

[0007] An object of the present invention is to provide a reference current circuit, a charge compensation method and a chip, which can keep the voltage of the connection point VBP as unchanged as possible when the reference current Iref_2 is switched.

[0008] To achieve the above objectives, an embodiment of the present invention provides a reference current circuit, comprising: a reference current generating unit, a reference current replicating unit, and a tracking compensation unit.

[0009] The tracking compensation unit includes a detection circuit, a clamping circuit, and a compensation circuit. A reference current generating unit is used to generate a reference current. A reference current replicating unit includes a first MOS transistor, a second MOS transistor, and a third MOS transistor connected in common gate. The first, second, and third MOS transistors form a current mirror. The drains of the first and second MOS transistors are connected to the reference current generating unit, and the drain of the third MOS transistor is connected to the functional unit. A detection circuit is connected to the drain of the third MOS transistor and is used to output different compensation voltages when the drain of the third MOS transistor is disconnected from and connected to the functional unit. A clamping circuit is connected to the detection circuit and is used to clamp the corresponding compensation voltage to a preset value when the drain of the third MOS transistor is disconnected from the functional unit. The compensation circuit is connected to the detection circuit, the clamping circuit, and the gate of the first MOS transistor and is used to inject charge into the gate of the first MOS transistor when the clamping circuit clamps the compensation voltage to the preset value, and to extract charge from the gate of the first MOS transistor when the drain of the third MOS transistor is connected to the functional unit.

[0010] In one or more embodiments of the present invention, the detection circuit includes a fourth MOS transistor and a fifth MOS transistor, wherein the gates of the fourth MOS transistor and the fifth MOS transistor are connected to the drain of the third MOS transistor, the drain of the fourth MOS transistor is connected to a clamping circuit to output a compensation voltage, the drain of the fifth MOS transistor is connected to the clamping circuit, and the sources of the fourth MOS transistor and the fifth MOS transistor are connected to a power supply voltage and a ground voltage, respectively.

[0011] In one or more embodiments of the present invention, the clamping circuit includes a seventh MOS transistor, the drain of the seventh MOS transistor is connected to the detection circuit, the gate of the seventh MOS transistor is connected to the gate of the first MOS transistor or the control voltage, and the source of the seventh MOS transistor is connected to the detection circuit to clamp the corresponding compensation voltage to a preset value when the drain of the third MOS transistor is disconnected from the functional unit.

[0012] In one or more embodiments of the present invention, the compensation circuit includes an eighth MOS transistor or a first capacitor, the source and drain of the eighth MOS transistor are connected and connected to the compensation voltage, the gate of the eighth MOS transistor is connected to the gate of the first MOS transistor, the first end of the first capacitor is connected to the compensation voltage, and the second end of the first capacitor is connected to the gate of the first MOS transistor.

[0013] In one or more embodiments of the present invention, the area of the conductive channel of the eighth MOS transistor is equal to 1 / 10 to 1 / 2 times the area of the conductive channel of the third MOS transistor.

[0014] In one or more embodiments of the present invention, the tracking compensation unit further includes a current limiting circuit, wherein the current limiting circuit is connected to the detection circuit and a ground voltage or the current limiting circuit is connected to the detection circuit and a power supply voltage.

[0015] In one or more embodiments of the present invention, the current limiting circuit includes a sixth MOS transistor, the gate and drain of the sixth MOS transistor are connected to the detection circuit, and the source of the sixth MOS transistor is connected to the power supply voltage or the ground voltage.

[0016] In one or more embodiments of the present invention, the reference current circuit further includes a second capacitor, a first end of the second capacitor is connected to the gate of the first MOS transistor, and a second end of the second capacitor is connected to the power supply voltage or the ground voltage.

[0017] The present invention also discloses a charge compensation method for a reference current circuit, wherein the reference current circuit includes: a reference current generating unit and a reference current replicating unit, wherein the reference current generating unit is used to generate a reference current; the reference current replicating unit includes a first MOS transistor, a second MOS transistor, and a third MOS transistor connected in common gate mode, wherein the first MOS transistor, the second MOS transistor, and the third MOS transistor form a current mirror for replicating the reference current, wherein the drains of the first MOS transistor and the second MOS transistor are connected to the reference current generating unit, and the drain of the third MOS transistor is used to access a functional unit;

[0018] The charge compensation method comprises:

[0019] When the drain of the third MOS transistor is connected to the functional unit, the detection circuit outputs a first compensation voltage based on the voltage of the drain of the third MOS transistor, and the compensation circuit extracts charge from the gate of the first MOS transistor based on the first compensation voltage;

[0020] When the drain of the third MOS transistor is disconnected from the functional unit, the detection circuit outputs a second compensation voltage based on the voltage of the drain of the third MOS transistor, the clamping circuit clamps the second compensation voltage to a preset value, and the compensation circuit injects charge into the gate terminal of the first MOS transistor based on the preset value.

[0021] The invention also discloses a chip comprising the reference current circuit.

[0022] Compared to the prior art, according to the reference current circuit, charge compensation method, and chip of this embodiment, when the drain of the third MOS transistor is disconnected from the functional unit, the detection circuit outputs a corresponding compensation voltage. When the clamping circuit clamps the compensation voltage to a preset value, the compensation circuit injects charge into the gate of the first MOS transistor. When the drain of the third MOS transistor is connected to the functional unit, the detection circuit outputs a corresponding compensation voltage, and the compensation circuit extracts charge from the gate of the first MOS transistor. Therefore, when the reference current circuit, which has an extremely low power consumption, has a low loop bandwidth and the reference current IBIAS output by the circuit switches, it is difficult to eliminate or reduce the impact of charge injection on the transient state of the reference current IBIAS through the loop. By compensating for the injected or extracted charge during the switching of the reference current IBIAS, the switched reference current IBIAS can be established at a very fast speed at a low cost (almost no DC power consumption) and the impact on the transient state of other reference currents IBIAS is greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a circuit principle diagram of a reference current circuit of prior art 1.

[0024] Figure 2 This is a circuit schematic diagram of the reference current circuit of the second prior art.

[0025] Figure 3 FIG. 4 is a first circuit principle diagram of a reference current circuit according to an embodiment of the present invention.

[0026] Figure 4 FIG. 4 is a second circuit schematic diagram of a reference current circuit according to an embodiment of the present invention.

[0027] Figure 5 is a flow chart of a charge compensation method for a reference current circuit according to an embodiment of the present invention.

[0028] Figure 6 is a first circuit principle diagram of a reference current circuit according to another embodiment of the present invention.

[0029] Figure 7 is a second circuit principle diagram of a reference current circuit according to another embodiment of the present invention. DETAILED DESCRIPTION

[0030] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

[0031] Unless expressly stated otherwise, throughout the specification and claims, the term "comprise" or variations such as "include" or "comprising", etc., will be understood to include the stated elements or components but not to exclude other elements or other components.

[0032] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by a programmable circuit. When an element or circuit is said to be "connected to" another element, or "connected to" another element, or when an element / circuit is said to be "connected" between two nodes, it may be directly coupled or connected to the other element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0033] The present invention will be further described below with reference to the accompanying drawings and examples.

[0034] Example 1

[0035] like Figure 3 As shown, a reference current circuit includes a reference current generating unit IBIAS_GENERATE, a reference current replica unit 10 and a tracking compensation unit 20.

[0036] The reference current generating unit IBIAS_GENERATE is used to generate specific reference currents I1 and I2. This embodiment does not impose any specific limitation on the specific structure of the reference current generating unit IBIAS_GENERATE, and any circuit structure capable of generating the specific reference currents I1 and I2 may be used.

[0037] After the reference current generating unit IBIAS_GENERATE generates the reference current, it needs to be replicated and outputted through the reference current replicating unit 10 for use by the functional unit Module. The reference current replicating unit 10 includes a plurality of first, second, and third MOS transistors M1, M2, and M3 connected in common gate fashion. The drain and gate of the first MOS transistor M1 are connected to form a connection point VBP. The first, second, and third MOS transistors M1, M2, and M3 form a current mirror for replicating specific reference currents I1 and I2. The drains of the first and second MOS transistors M1, M2 are connected to the reference current generating unit IBIAS_GENERATE, while the drain of the third MOS transistor is connected to the functional unit Module to replicate the reference current Iref for use by the functional unit Module.

[0038] In this embodiment, two third MOS transistors are provided: a third MOS transistor M3_1 and a third MOS transistor M3_2. The drain of the third MOS transistor M3_1 is connected to the first functional unit Module_1, and the drain of the third MOS transistor M3_2 is connected to the second functional unit Module_2. The specific reference currents I1 and I2 are proportionally replicated by the third MOS transistors M3_1 and M3_2 to form the first reference current Iref_1 and the second reference current Iref_2, which are then supplied to the first functional unit Module_1 and the second functional unit Module_2. In other embodiments, the number of third MOS transistors can be adjusted as needed; that is, the more functional units, the greater the number of third MOS transistors.

[0039] The conduction or disconnection between any functional unit Module and the drain of the corresponding third MOS transistor will affect the charge at the connection point VBP and the base current Iref of other branches, so the following takes the conduction and disconnection between the drain of the third MOS transistor M3_2 and the second functional unit Module_2 as an example to explain this embodiment in detail. Figure 3 As shown, in this embodiment, the drain of the third MOS transistor M3_2 is connected to the second functional unit Module_2 through the switch S1, so that the switch S1 controls the conduction and disconnection between the drain of the third MOS transistor M3_2 and the second functional unit Module_2.

[0040] like Figure 3 As shown, the tracking compensation unit 20 is connected to the drain of the third MOS transistor M3_2. Specifically, the tracking compensation unit 20 includes: a detection circuit 21, a clamping circuit 22 and a compensation circuit 23.

[0041] Detection circuit 21 is connected to the drain of the third MOS transistor M3_2 and is configured to output different compensation voltages when the drain of the third MOS transistor M3_2 is disconnected from and connected to the second functional unit Module_2. When the drain of the third MOS transistor M3_2 is disconnected from the second functional unit Module_2, the third MOS transistor M3_2 operates in a linear region. When the drain of the third MOS transistor M3_2 is connected to the second functional unit Module_2, the third MOS transistor M3_2 operates in a saturation region.

[0042] The detection circuit 21 includes a fourth MOS transistor M4 and a fifth MOS transistor M5. The gates of the fourth and fifth MOS transistors M4 and M5 are connected to the drain of the third MOS transistor M3_2. The source of the fourth MOS transistor M4 is connected to the power supply voltage VDD, and the drain of the fourth MOS transistor M4 is connected to the clamping circuit 22 to form a connection point Vs for outputting a compensation voltage. The drain of the fifth MOS transistor M5 is connected to the clamping circuit 22, and the source of the fifth MOS transistor M5 is connected to the ground voltage. When the third MOS transistor M3_2 operates in the saturation region (i.e., switch S1 is closed), the drain voltage of the third MOS transistor M3_2 is determined by the second functional unit Module_2 receiving the second reference current Iref_2 (generally, the gate-source voltage of the MOS transistor in the current mirror of the second functional unit Module_2, or the sum of the gate-source voltage and the saturation voltage). The fourth MOS transistor M4 is turned on, and the fifth MOS transistor M5 is turned off. At this time, the compensation voltage output at the connection point Vs is the power supply voltage VDD.

[0043] like Figure 3 As shown, the clamping circuit 22 is connected to the detection circuit 21 , and the clamping circuit 22 is used to clamp the corresponding compensation voltage to a preset value when the drain of the third MOS transistor M3_2 is disconnected from the second functional unit Module_2 .

[0044] Specifically, the clamping circuit 22 includes a seventh MOS transistor M7. The drain of the seventh MOS transistor M7 is connected to the drain of the fifth MOS transistor M5, the gate of the seventh MOS transistor M7 is connected to the gate of the first MOS transistor M1, and the source of the seventh MOS transistor M7 is connected to the drain of the fourth MOS transistor M4 to form a connection point Vs. When the third MOS transistor M3_2 operates in the linear region, the voltage at the drain of the third MOS transistor M3_2 is equal to the power supply voltage VDD, the fifth MOS transistor M5 is turned on, and the compensation voltage output at the connection point Vs begins to drop from the power supply voltage VDD. At this time, the compensation voltage output at the connection point Vs is clamped to a preset value by the seventh MOS transistor M7. Since the seventh MOS transistor M7 is in a subthreshold conduction state, the preset value is generally less than VBP+|V THP |,|V THP | is the threshold voltage of the seventh MOS transistor M7.

[0045] like Figure 4 As shown, in other embodiments, a control voltage may also be applied to the gate of the seventh MOS transistor M7, and the control voltage is VBP-|V THP |, so that when the seventh MOS transistor M7 is subthreshold turned on, the compensation voltage output from the connection point Vs is clamped to a voltage closer to the connection point VBP through the seventh MOS transistor M7.

[0046] like Figure 3As shown, the compensation circuit 23 is connected to the connection point Vs and the gate of the first MOS transistor M1. The compensation circuit 23 is used to inject charge into the gate of the first MOS transistor M1 when the clamping circuit 22 clamps the compensation voltage output from the connection point Vs to a preset value, and to extract charge from the gate of the first MOS transistor M1 when conduction occurs between the drain of the third MOS transistor M3_2 and the second functional unit Module_2.

[0047] Specifically, the compensation circuit 23 includes an eighth MOS transistor M8. The area of the conductive channel of the eighth MOS transistor is 1 / 10 to 1 / 2 times the area of the conductive channel of the third MOS transistor. The source and drain of the eighth MOS transistor M8 are connected and connected to the connection point Vs. The gate of the eighth MOS transistor M8 is connected to the gate of the first MOS transistor M1. In other embodiments, the eighth MOS transistor M8 can be replaced by a first capacitor. The first end of the first capacitor is connected to the connection point Vs, and the second end of the first capacitor is connected to the gate of the first MOS transistor M1.

[0048] When the tracking compensation unit 20 is not connected, Figure 1 As shown, when the switch S1 on the branch corresponding to the second reference current Iref_2 is turned off, the third MOS transistor M3_2 operates in the linear region, extracting charge from the connection point VBP, affecting the voltage at the connection point VBP, and further affecting the first reference current Iref_1. The gate-source capacitance and gate-drain capacitance of the third MOS transistor M3_2 are C gs 、C gd , the third MOS tube M3_2 works in the linear region, so the gate-source capacitance C gs , gate-drain capacitance C gd The corresponding ones are:

[0049] Wherein, W is the width of the conductive channel of the first MOS transistor M1 and the second MOS transistor M2, L is the length of the conductive channel of the first MOS transistor M1 and the second MOS transistor M2, C ox is the gate oxide capacitance per unit area of the third MOS transistor M3_2, C ov is the unit overlap capacitance of the third MOS transistor M3_2.

[0050] Therefore, the total gate capacitance charge of the third MOS tube M3_2 when the switch S1 is turned off is (ignoring C gb ):

[0051] Q1=(C gs +C gd )*(VBP-VDD)=(WLC ox +2WC ov )*(VBP-VDD), VBP is the voltage at the connection point VBP.

[0052] When the switch S1 is closed, the third MOS transistor M3_2 operates in the saturation region, which will inject charge into the connection point VBP, affecting the voltage at the connection point VBP, and further affecting the first reference current Iref_1. The MOS transistor MP2 enters the saturation region, so the gate-source capacitance C gs , gate-drain capacitance C gd They are:

[0053] C gd =WC ov .

[0054] Therefore, the charge of the total gate capacitance of the third MOS transistor M3_2 at this time is:

[0055] V D,mp2 is the drain voltage of the third MOS transistor M3_2.

[0056] When the switch S1 is closed, the third MOS transistor M3_2 enters the saturation region from the linear region, and the charge change of its total gate capacitance is:

[0057]

[0058] Since the first MOS tube M1 and the second MOS tube M2 are both current mirror tubes, their L values are generally large and meet the WLC ox >>WCov, therefore This is a charge that is only related to VDD-VBP and the W, L and unit area gate oxide capacitance of the conductive channel of the third MOS tube M3_2. Therefore, it can be considered to be extracted from the connection point VBP when the switch S1 is closed. The amount of charge is used to offset the impact of this charge injection on the connection point VBP.

[0059] After accessing the tracking compensation unit 20, Figure 3 As shown, when the switch S1 is turned off, the fifth MOS transistor M5 is turned on, and the compensation voltage outputted from the connection point Vs drops to the preset value clamped by the seventh MOS transistor M7 (because the seventh MOS transistor M7 is in a subthreshold conduction state, the actual value of the preset value is less than VBP+|V THP |), thereby injecting charges into the connection point VBP through the eighth MOS transistor M8 to offset the charges extracted from the connection point VBP by the third MOS transistor M3_2, thereby ensuring that the voltage of the connection point VBP remains unchanged.

[0060] When the switch S1 is closed, the fourth MOS transistor M4 is turned on, and the compensation voltage output at the connection point Vs rises to the power supply voltage VDD. Therefore, the charge at the connection point VBP is extracted through the eighth MOS transistor M8 to offset the charge injected into the connection point VBP by the third MOS transistor M3_2, thereby ensuring that the voltage at the connection point VBP remains unchanged.

[0061] The amount of charge drawn from the connection point VBP is:

[0062] Q c =W M8 L M8 C ox *(VDD-VBP-|V THP |), where W M8 is the width of the conductive channel of the eighth MOS transistor M8, L M8 is the length of the conductive channel of the eighth MOS transistor M8, |V THP | is the threshold voltage of the seventh MOS tube M7, VBP is the voltage at the connection point VBP, C ox is the gate oxide capacitance per unit area of the third MOS transistor M3_2.

[0063] Let Q c =ΔQ, we can get:

[0064] |V dsat,3_2 | is the drain-source saturation current of the third MOS transistor M3_2. This expression has nothing to do with the power supply voltage VDD, so the compensation effect will not change significantly with the change of the power supply voltage VDD.

[0065] From the above formula, it can be seen that the area of the conductive channel of the eighth MOS transistor M8 is designed to be equal to 1 / 3 times the area of the conductive channel of the third MOS transistor M3_2, that is, the width W of the conductive channel of the eighth MOS transistor M8 is M8 The length L of the conductive channel of the eighth MOS transistor M8 M8 The product value is equal to or very close to the width W of the conductive channel of the third MOS tube M3_2. 3_2 The length L of the conductive channel of the eighth MOS transistor M8 3_2 At the same time, since the seventh MOS tube M7 works in the sub-threshold state, when the switch S1 is disconnected, the compensation voltage output by the connection point Vs is closer to the voltage at the connection point VBP (relative to VBP+|V THP |), so the tracking compensation unit 20 has a better compensation effect.

[0066] like Figure 4As shown, the tracking compensation unit 20 in this embodiment further includes a current limiting circuit 24 , which is connected to the detection circuit 21 and the ground voltage. In other embodiments, the current limiting circuit 24 may also be removed.

[0067] Specifically, the current limiting circuit 24 includes a sixth MOS transistor M6. The gate and drain of the sixth MOS transistor M6 are connected to the source of the fifth MOS transistor M5. The source of the sixth MOS transistor M6 is connected to the ground voltage. By configuring the fifth MOS transistor M5, when the switch S1 is closed and the voltage output by the drain of the third MOS transistor M3_2 is equal to the gate-source voltage of the MOS transistor in the current mirror of the second functional unit Module_2 or the sum of the gate-source voltage and the saturation voltage, it is ensured that the source of the fifth MOS transistor M5 is disconnected from the ground voltage.

[0068] like Figure 3 As shown, the reference current circuit further includes a second capacitor Cx, a first end of which is connected to the gate of the first MOS transistor M1, and a second end of which is connected to the power supply voltage VDD. By providing the second capacitor Cx, the voltage at the connection point VBP is further unaffected by the voltages at other points.

[0069] In this embodiment, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3_1, the third MOS transistor M3_2, the fourth MOS transistor M4, the seventh MOS transistor M7 and the eighth MOS transistor M8 are all PMOS transistors, and the fifth MOS transistor M5 and the sixth MOS transistor M6 are both NMOS transistors.

[0070] like Figure 5 As shown, based on the above-mentioned reference current circuit, the present invention also discloses a charge compensation method for the reference current circuit, comprising:

[0071] When the drain of the third MOS transistor M3_2 is conductively connected to the second functional unit Module_2, the detection circuit 21 outputs a first compensation voltage based on the voltage at the drain of the third MOS transistor M3_2. The compensation circuit then extracts charge from the gate of the first MOS transistor M1 based on the first compensation voltage. The first compensation voltage is equal to the power supply voltage VDD.

[0072] When the drain of the third MOS transistor M3_2 is disconnected from the second functional unit Module_2, the detection circuit outputs a second compensation voltage based on the voltage at the drain of the third MOS transistor M3_2. The clamping circuit 22 clamps the second compensation voltage to a preset value, and the compensation circuit 23 injects charge based on the preset value into the gate of the first MOS transistor M1. The second compensation voltage is equal to the threshold voltage of the seventh MOS transistor M7 or the sum of the voltage at the gate of the first MOS transistor M1 and the threshold voltage of the seventh MOS transistor M7. The seventh MOS transistor M7 operates in a subthreshold state.

[0073] The present invention also discloses a chip comprising the above-mentioned reference current circuit.

[0074] Example 2

[0075] The compensation principle in this embodiment is similar to that in embodiment 1. Figure 6 and Figure 7 As shown, the difference between this embodiment and Embodiment 1 is that the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3_1, the third MOS transistor M3_2, the fourth MOS transistor M4, the seventh MOS transistor M7 and the eighth MOS transistor M8 are all NMOS transistors, and the fifth MOS transistor M5 and the sixth MOS transistor M6 are both PMOS transistors, and the corresponding connection methods are also changed accordingly.

[0076] The foregoing descriptions of specific exemplary embodiments of the present invention are for purposes of illustration and description. These descriptions are not intended to limit the invention to the precise forms disclosed, and it is apparent that many variations and modifications are possible in light of the foregoing teachings. The exemplary embodiments have been selected and described for the purpose of explaining the specific principles of the invention and their practical application, thereby enabling those skilled in the art to realize and utilize a variety of exemplary embodiments of the invention and various options and modifications. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A reference current circuit, characterized in that: include: A reference current generating unit, configured to generate a reference current; A reference current replication unit, comprising a first MOS transistor, a second MOS transistor, and a third MOS transistor connected in common gate connection, wherein the first MOS transistor, the second MOS transistor, and the third MOS transistor constitute a current mirror for replicating a reference current, wherein the drains of the first MOS transistor and the second MOS transistor are connected to the reference current generation unit, and the drain of the third MOS transistor is used to access a functional unit; as well as A tracking compensation unit, the tracking compensation unit comprising: a detection circuit connected to the drain of the third MOS transistor, the detection circuit being configured to output different compensation voltages when the drain of the third MOS transistor is disconnected from and connected to the functional unit; a clamping circuit connected to the detection circuit, wherein the clamping circuit is configured to clamp the corresponding compensation voltage to a preset value when the drain of the third MOS transistor is disconnected from the functional unit; A compensation circuit is connected to the detection circuit, the clamping circuit, and the gate of the first MOS transistor. The compensation circuit is configured to inject charge into the gate of the first MOS transistor when the clamping circuit clamps the compensation voltage to a preset value, and to extract charge from the gate of the first MOS transistor when conduction occurs between the drain of the third MOS transistor and the functional unit.

2. The reference current circuit according to claim 1, wherein: The detection circuit includes a fourth MOS transistor and a fifth MOS transistor. The gates of the fourth and fifth MOS transistors are connected to the drain of the third MOS transistor. The drain of the fourth MOS transistor is connected to a clamping circuit to output a compensation voltage. The drain of the fifth MOS transistor is connected to the clamping circuit. The sources of the fourth and fifth MOS transistors are connected to a power supply voltage and a ground voltage, respectively.

3. The reference current circuit according to claim 1, wherein: The clamping circuit includes a seventh MOS transistor, a drain of the seventh MOS transistor being connected to the detection circuit, a gate of the seventh MOS transistor being connected to the gate of the first MOS transistor or the control voltage, and a source of the seventh MOS transistor being connected to the detection circuit so as to clamp the corresponding compensation voltage to a preset value when the drain of the third MOS transistor is disconnected from the functional unit.

4. The reference current circuit according to claim 1, wherein: The compensation circuit includes an eighth MOS transistor or a first capacitor, wherein the source and drain of the eighth MOS transistor are connected and connected to the compensation voltage, the gate of the eighth MOS transistor is connected to the gate of the first MOS transistor, the first end of the first capacitor is connected to the compensation voltage, and the second end of the first capacitor is connected to the gate of the first MOS transistor.

5. The reference current circuit according to claim 4, wherein: The area of the conductive channel of the eighth MOS transistor is equal to 1 / 10 to 1 / 2 times the area of the conductive channel of the third MOS transistor.

6. The reference current circuit according to claim 1, wherein: The tracking compensation unit further includes a current limiting circuit, which is connected to the detection circuit and a ground voltage or connected to the detection circuit and a power supply voltage.

7. The reference current circuit according to claim 6, wherein: The current limiting circuit includes a sixth MOS transistor, the gate and drain of the sixth MOS transistor are connected to the detection circuit, and the source of the sixth MOS transistor is connected to the power supply voltage or the ground voltage.

8. The reference current circuit according to claim 1, wherein: The reference current circuit further includes a second capacitor, a first end of the second capacitor is connected to the gate of the first MOS transistor, and a second end of the second capacitor is connected to the power supply voltage or the ground voltage.

9. A charge compensation method for a reference current circuit, characterized in that: The reference current circuit includes: a reference current generating unit and a reference current copying unit, wherein the reference current generating unit is used to generate a reference current; the reference current copying unit includes a first MOS transistor, a second MOS transistor, and a third MOS transistor connected in common gate, wherein the first MOS transistor, the second MOS transistor, and the third MOS transistor form a current mirror for copying the reference current, the drains of the first MOS transistor and the second MOS transistor are connected to the reference current generating unit, and the drain of the third MOS transistor is used to access the functional unit; The charge compensation method comprises: When the drain of the third MOS transistor is connected to the functional unit, the detection circuit outputs a first compensation voltage based on the voltage of the drain of the third MOS transistor, and the compensation circuit extracts charge from the gate of the first MOS transistor based on the first compensation voltage; When the drain of the third MOS transistor is disconnected from the functional unit, the detection circuit outputs a second compensation voltage based on the voltage of the drain of the third MOS transistor, the clamping circuit clamps the second compensation voltage to a preset value, and the compensation circuit injects charge into the gate terminal of the first MOS transistor based on the preset value.

10. A chip, characterized in that: The device comprises the reference current circuit according to any one of claims 1 to 8.

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