Current mirror circuit

Abstract

This disclosure relates to a current mirror circuit. In one embodiment, an electronic device includes: a first MOS transistor and a second MOS transistor connected as a current mirror, wherein the first transistor is diode-connected; and a first circuit configured to provide a first current equal to a first gate current of the first transistor multiplied by the size ratio of the first and second transistors.

Description

[0001] Cross-reference of related applications

[0002] This application claims the benefit of French Application No. 2107030, filed on June 30, 2021, which is incorporated herein by reference. Technical Field

[0003] This invention generally relates to electronic circuits and systems. More specifically, this invention relates to electronic circuits capable of replicating electric current, and even more specifically, to current mirror circuits. Background Technology

[0004] There are various electronic circuits capable of performing basic operations used in more complex electronic devices. Among the most common basic operations to be performed, current mirrors are particularly useful.

[0005] A current mirror circuit, or current mirror, is an electronic circuit that can replicate the current flowing through a first conductor into a second conductor. Summary of the Invention

[0006] The embodiment provides a current mirror circuit.

[0007] The embodiment provides a current mirror circuit that can more accurately replicate current.

[0008] Various embodiments address all or part of the drawbacks of known current mirror circuits.

[0009] One embodiment provides an electronic device including: a first MOS transistor and a second MOS transistor connected as a current mirror, the first transistor being diode-connected; and a first circuit adapted to provide a first current, the first current being equal to a first gate current of the first transistor multiplied by the size ratio of the first and second transistors.

[0010] According to one embodiment, the first circuit is connected to a first node and a second node, the first node being interconnected with the gates of first and second transistors, the second node being interconnected with a first conductive terminal of the first transistor and a first conductive terminal of the second transistor, and the first circuit providing the first current to the second conductive terminal of the second transistor.

[0011] According to one embodiment, the first and second transistors are P-type MOS transistors.

[0012] According to one embodiment, the first circuit includes a first module adapted to isolate a first gate current and a first current mirror.

[0013] According to one embodiment, the first current mirror includes a third and a fourth MOS transistor, the third transistor being diode-connected, wherein the second gate current of the second and third transistors is negligible relative to the first gate current.

[0014] According to one embodiment, the third and fourth transistors are PMOS transistors with a double oxide layer.

[0015] According to one embodiment, the size ratio of the third and fourth transistors is equal to the size ratio of the first and second transistors.

[0016] According to one embodiment, the first current mirror includes a fifth and a sixth transistor, the fifth transistor being diode-connected, wherein the third gate current of the fifth transistor is proportional to the first gate current.

[0017] According to one embodiment, the third gate current is equal to half of the first gate current, and the size ratio of the fifth and sixth transistors is twice the size ratio of the first and second transistors.

[0018] According to one embodiment, the first circuit includes K second circuits arranged in a cascaded manner, where K is a relative integer, and each second circuit is adapted to isolate parasitic current from the preceding circuit.

[0019] According to one embodiment, K equals 2 or 3.

[0020] According to one embodiment, the second circuit ranked i (where i varies between 1 and K) includes: an input node connected to the output node of the second circuit ranked i-1; a first output node connected to the input node of the second circuit ranked i+1; and a second output node connected to the second conductive terminal of the second transistor.

[0021] According to one embodiment, each second circuit includes: a second current mirror including a seventh MOS transistor of the same size; a third current mirror including an eighth MOS transistor with a size ratio equal to that of the first and second transistors; and a second module adapted to isolate parasitic current from another second circuit in the second circuit.

[0022] According to one embodiment, the second module is connected to the input node of the second circuit ranked between 1 and i-2 and the interconnect node of the gates of the first and second transistors.

[0023] According to one embodiment, the second and third current mirrors share the same ninth, diode-connected transistor. Attached Figure Description

[0024] The above features and advantages, as well as others, will be described in detail in the following description of specific embodiments given by way of illustration, but not limited to the drawings, wherein:

[0025] Figure 1 A current mirror circuit including a PMOS transistor is shown;

[0026] Figure 2 An embodiment of an electronic device is schematically and partially illustrated in block form;

[0027] Figure 3 It is shown in more detail, schematically, and partially in block form. Figure 2 Examples;

[0028] Figure 4 It is shown in more detail, schematically, and partially in block form. Figure 2 Examples;

[0029] Figure 5 Another embodiment of the electronic device is schematically and partially shown in block form;

[0030] Figure 6 The diagram is shown schematically and partially in block form. Figure 5 Part of the embodiments;

[0031] Figure 7 Showing more details Figure 5 Part of the embodiments; and

[0032] Figure 8 Showing more details Figure 5 Examples of embodiments. Detailed Implementation

[0033] Similar features have been designated by similar reference numerals in the various figures. In particular, structural and / or functional features common in the various embodiments may have the same reference numerals and may be arranged with the same structure, size, and material properties.

[0034] For clarity, only the operations and elements that help to understand the embodiments described herein are described in detail.

[0035] Unless otherwise stated, when referring to two elements connected together, it means a direct connection without any intermediate elements other than conductors, and when referring to two elements coupled together, it means that the two elements can be connected or coupled via one or more other elements.

[0036] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers (such as the terms “front,” “back,” “up,” “down,” “left,” “right,” etc.) or relative position qualifiers (such as the terms “above,” “below,” “higher,” “lower,” etc.) or directional qualifiers (such as “horizontal,” “vertical,” etc.), refer to the directions shown in the figures.

[0037] Unless otherwise specified, the expressions “around,” “approximately,” “basically,” and “on the order of magnitude of” mean within 10%, preferably within 5%.

[0038] In the following description, the current mirror circuit is referred to as a current mirror.

[0039] Figure 1 This is the electrical diagram of the current mirror 100.

[0040] The current mirror 100 includes two transistors 101 and 102. Transistors 101 and 102 are gate-insulated field-effect transistors, more commonly referred to as metal-oxide-semiconductor field-effect transistors (MOSFETs) or MOS transistors. Transistors 101 and 102 are transistors of the same type. According to one example, transistors 101 and 102 are P-channel MOS transistors, also known as PMOS transistors. Figure 1 In this configuration, transistors 101 and 102 are PMOS transistors. According to one variation, transistors 101 and 102 may be N-channel MOS transistors or NMOS transistors; those skilled in the art will know how to adjust the device connections in this case.

[0041] Transistors 101 and 102 are arranged end-to-end and are current-mirrored. In other words, the gates of transistors 101 and 102 are linked (preferably connected or interconnected) to interconnect node A. Furthermore, the gate of transistor 101 is linked (preferably connected or interconnected) to one of its conductive terminals. Transistor 101 is referred to as having a diode connection. More specifically, when transistor 101 is a PMOS type transistor, the gate of transistor 101 is linked (preferably connected or interconnected) to its drain.

[0042] Transistor 101 also interconnects one of its conductive terminals to the same conductive terminal of transistor 102. More specifically, when transistors 101 and 102 are PMOS type transistors, the sources of transistors 101 and 102 are interconnected. The interconnection node of the conductive terminals of transistors 101 and 102 is denoted as VDD. According to one example, the interconnection node VDD receives a power supply potential VDD, such as a potential higher than ground.

[0043] Transistor 101 receives the current I to be replicated at its on-terminal (connected to its gate, i.e., its drain). Figure 1 In this configuration, the current I is provided, for example, by the current source 103, but in practice, the drain of transistor 101 can receive the current I from any electronic device node. Conventionally, the current I flows from the drain of transistor 101 to the current source 103.

[0044] Transistor 102 at its free conductive terminal (i.e., Figure 1A replica current I' is provided at the drain of transistor 102. Current I' flows from the drain of transistor 102 to the output node S of current mirror 100. Theoretically, current I' is proportional to current I, with the proportionality coefficient M defined by the ratio of the gate width to the gate length of transistors 101 and 102. If transistors 101 and 102 are identical, then theoretically current I' equals current I. However, in practice, current I' additionally depends on the gate current IG of transistor 101 according to the following relationship:

[0045] I′=M*(I-IG)

[0046] The gate current IG may be on the order of being non-negligible relative to the current I, or even comparable to the current I, leading to current loss at the current mirror output. Transistor miniaturization tends to increase this phenomenon. In fact, the smaller the transistor, the thinner its gate oxide layer, and the more likely it is to allow electrons to pass through via the tunneling effect. This can occur in transistors with gate lengths on the order of 3nm, 5nm, 7nm, or even 16nm and relatively small gate thicknesses (i.e., between 1nm and 1mm). The following embodiments aim to overcome this problem.

[0047] Figure 2 An electrical diagram of one embodiment of electronic device 200 is shown schematically and partially in block form. According to one embodiment, electronic device 200 is a current mirror circuit or a current mirror.

[0048] Device 200 includes two transistors 201 and 202. Transistors 201 and 202 are MOS transistors. Transistors 201 and 202 are transistors of the same type. The ratio of the gate width to the length of transistors 201 and 202 is expressed as N. According to an example, in Figure 2 In the original diagram, transistors 201 and 202 are PMOS transistors. In a variant, transistors 201 and 202 may be NMOS transistors, and those skilled in the art will know how to adjust the connections of the current mirror 200 in this case.

[0049] The arrangement of transistors 201 and 202 is similar to that of a combination Figure 1 Transistors 101 and 102 of the current mirror 100 are described. In other words, transistors 101 and 202 are current mirror mounted, and transistor 201 is connected in a diode manner. The gate interconnect node of transistors 201 and 202 is denoted as A0, and the source interconnect node of transistors 201 and 202 is still denoted as VDD. As previously stated, node VDD can receive the power supply potential.

[0050] and Figure 1Similarly, transistor 201 receives a current Iref from current source 203 at its input node (corresponding to the drain of transistor 201). Current Iref flows from the drain of transistor 201 to current source 203. Device 200 provides a copy of the current Iref at its output node S, denoted as Iref'. Current Iref' flows from node B0 to output node S.

[0051] The device 200 also includes a circuit 204 adapted to provide a current N*Ig0 at node B0 equal to the gate current of transistor 201 multiplied by a coefficient N, i.e., the gate current of transistor 202. Circuit 204 is connected to node A0, which interconnects the gates of transistors 201 and 202, and is also connected to node VDD.

[0052] Circuit 204 enables compensation for the parasitic current applied by the current mirror formed by transistors 201 and 202, corresponding to the gate current N*Ig0 that causes the loss of the output current Iref' of device 200. Combined with Figure 3 and Figure 4 The circuit 204 is described in more detail.

[0053] More specifically, the current mirror formed by transistors 201 and 202 allows current to flow from the drain of transistor 202 to node B0 at the drain of transistor 202, as given by the following formula:

[0054] Iref′=N*(Iref-Ig0)

[0055] By using node rules, it can be determined that the current Iref' is equal to the current Iref multiplied by the coefficient N.

[0056] Figure 3 The reference is shown schematically and partially in block form. Figure 2 Electrical diagram of the described device 200.

[0057] Circuit 204 includes at least two modules 2041 and 2042 arranged in series between nodes A0 and B0.

[0058] Module 2041 is a circuit suitable for isolating the gate current Ig0 of transistor 201. Module 2041 is linked (preferably connected) to nodes A0 and VDD. Module 2041 provides current Ig0 as an output. Conventionally, current Ig0 flows into module 2041.

[0059] Module 2042 is a circuit adapted to multiply the gate current Ig0, which is isolated by module 2041, by a coefficient N. Module 2042 is linked (preferably connected) to node VDD and receives the current Ig0 provided by module 2041 as input. Module 2042 provides a current N*Ig0 to node B0 as output. The current N*Ig0 flows from module 2042 to node B0.

[0060] Examples from modules 2041 and 2042 will be combined Figure 4 To describe in more detail.

[0061] Figure 4 The combination is shown Figure 2 and Figure 3 Electrical diagram of an embodiment of the described electronic device.

[0062] exist Figure 4 In the example shown, module 2041 includes transistor 20411 and current source 20412.

[0063] Transistor 20411 is identical to transistor 201. Therefore, Figure 4 Transistor 20411 is a PMOS transistor of the same size as transistor 201. Transistor 20411 and transistor 201 are current mirrors. Therefore, the gate of transistor 20411 is linked (preferably connected or interconnected) to the gate of transistor 201 (i.e., node A0), and the source of transistor 20411 is linked (preferably connected or interconnected) to the source of transistor 201 (i.e., node VDD). Therefore, the current supplied to the drain of transistor 201 is equal to the current Iref minus the gate current Ig0 of transistor 201, expressed as Iref-Ig0. The current Iref-Ig0 flows from the drain of transistor 20411 to node C0.

[0064] Current source 20412 is similar to (preferably identical to) current source 203 and provides current Iref. Current Iref flows to current source 20412.

[0065] Node C0 is the output node of module 2041. The output current is equal to the gate current Ig0 of transistor 201. Current Ig0 flows to the output node C0 of module 2041.

[0066] Module 2042 is a current mirror circuit adapted to multiply the current Ig0 provided by module 2041 by a coefficient N. Module 2042 includes two current-mirror transistors 20421 and 20422, wherein transistor 20421 is diode-connected. Transistors 20421 and 20422 are the same type of transistors as transistors 201 and 202, i.e., PMOS transistors. The gate interconnect node of transistors 20421 and 20422 is denoted as A1, and the source interconnect node of transistors 20421 and 20422 is node VDD. The current mirror input node (i.e., the drain of transistor 20421) is linked (preferably connected) to node C0. The current mirror output node (i.e., the drain of transistor 20422) is linked (preferably connected) to node B0.

[0067] The drain of transistor 20421 receives current Ig0 from module 2041. The drain output current Ig0 of transistor 20422 is multiplied by a coefficient N, denoted as N*Ig0. Current N*Ig0 flows from the drain of transistor 20422 to node B0.

[0068] Here, two embodiments can be used to obtain the product of current Ig0 and coefficient N.

[0069] According to a first embodiment, transistors 20421 and 20422 are each selected to have a gate current negligible relative to the gate current Ig0. As an example, transistors 20421 and 20422 are selected to have a smaller size than transistors 201 and 202. According to another example, transistors 20421 and 20422 are transistors having a gate consisting of two conventional gate stacks (i.e., having a double gate oxide layer). Furthermore, transistors 20421 and 20422 are selected to have a coefficient N equal to that of transistors 201 and 202. According to one example, in order to have a gate current negligible relative to the gate current Ig0, transistors 20421 and 20422 may be transistors having a double gate oxide layer. According to another example, transistors 20421 and 20422 may be transistors with a gate width and / or length greater than the gate width and / or length of transistors 201 and 202.

[0070] According to the second embodiment, transistor 20421 is selected to have a gate current equal to half the gate current of transistor 201, denoted as 2*Ig0. Furthermore, transistors 20421 and 20422 are selected to have a gate width ratio equal to twice the gate width ratio of transistors 201 and 202, denoted as 2*N. Therefore, the output current of circuit 204 is given by the following formula:

[0071]

[0072] Figure 5 Another embodiment of the electronic device 300 is schematically and partially shown in block form. According to one embodiment, the electronic device 300 is a current mirror circuit or a current mirror.

[0073] Device 300 is similar to a combination Figure 2 , Figure 3 and Figure 4 The electronic device 200 is described. The common components of devices 300 and 200 are no longer described here, but only their differences are highlighted.

[0074] Similar to device 200, device 300 includes a first current mirror formed by transistors 201 and 202, receiving a current Iref supplied by current source 203, and replacing circuit 204. It also includes a series of K circuits 301-i, where K and i are natural numbers, and i varies between 1 and K, similar to circuit 204 of device 200. According to one example, K can be equal to 1, 2, or 3. Figure 8 The case of device 300 with K equal to 2 is shown.

[0075] Each circuit 301-i includes an input node Ai and two output nodes Bi and NBi. In addition, each circuit 301-i is linked (preferably connected) to nodes VDD and A0 and nodes A1, A2, ..., Ai-2 of the preceding circuits 301-1, 301-2, ..., 301-i-2.

[0076] Circuits 301-i are cascaded. More specifically, each circuit 301-i links (preferably connects) its input node Ai to the output node Bi-1 of the preceding circuit 301-i-1. The output node NBi is linked (preferably connected) to the output node S of the device 300. The input node A1 of circuit 301-1 is connected to node A0.

[0077] Circuit 301-1 isolates the gate current Ig1 from the current mirror formed by transistors 201 and 202. Each circuit 301-i provides a current that depends on the parasitic current of the preceding circuit 301-i-1 and its own parasitic current. Therefore, if each circuit 301-i has a parasitic current denoted as Igi, then each circuit 301-i receives a current equal to (Igi-2)-(Igi-1) at its input node Ai and provides a current equal to (Igi-1)-(Igi) at its output node Bi.

[0078] Circuit 301-i also provides a current equal to N*[(Igi-1)-(Igi)] at its output node NBi. This allows the output current of device 300 to be equal to the current Iref of the current source, regardless of the gate current Ig0 of transistor 201.

[0079] Circuit 301-K is similar to a combination Figure 2 The circuit 204 is described, and the parasitic current of circuit 301-K-1 is multiplied by a coefficient N, denoted as N*IgK-1. According to one embodiment, circuit 301-K may not include the output node BK.

[0080] One advantage of this embodiment is that the gate current Ig0 of transistor 201 can be estimated more accurately.

[0081] Combination Figure 6 and Figure 7 An example embodiment of circuit 301-i is described in more detail.

[0082] Figure 6 The combination is shown Figure 5 A partial circuit diagram of an example embodiment of the described circuit 301-i.

[0083] Such as combination Figure 5 The circuit 301-i includes node Ai as an input node and nodes Bi and NBi as output nodes.

[0084] Circuit 301-i includes a current mirror consisting of two identical transistors 3011-i and 3012-i, with transistor 3011-i connected as a diode. The source links (preferably connected) of transistors 3011-i and 3012-i are connected to node VDD. More specifically, transistors 3011-i and 3012-i are coupled with… Figure 5 Transistors 201 and 202 are described as being of the same type, and preferably, transistors 3011-i and 3012-i are the same as transistor 201. Figure 6 In the diagram, transistors 3011-i and 3012-i are PMOS transistors. At their input nodes, a current mirror receives a current Igi-1 at node Ai, corresponding to the drain of transistor 3011-i. Subtracting the parasitic current Igi of circuit 301-i from this current mirror yields (Igi-1)-(Igi). Here, the current Igi corresponds to the gate current of transistor 3011-i. The current (Igi-1)-(Igi) flows from the drain of transistor 3011-i to node Ai. The output of the current mirror is node Bi, which provides a replicated current (Igi-1)-(Igi).

[0085] Circuit 301-i also includes transistor 3013-i, which is a current mirror of transistor 3011-i. Transistor 3013-i is the same type of transistor as transistor 3011-i, such as a PMOS transistor. More specifically, transistor 3013-i is identical to transistor 202, and therefore its size factor relative to transistor 3011-i is equal to the factor N of transistors 201 and 202. Transistor 3013-i is a current mirror of transistor 3011-i. In other words, the gate of transistor 3013-i is linked (preferably connected) to node Ai, the source of transistor 3013-i is linked (preferably connected) to node VDD, and the drain of transistor 3013-i is linked (preferably connected) to node NBi. Therefore, node NBi provides the current given by the following formula:

[0086] N*[(Igi-1)-(Igi)]

[0087] Circuit 301-i includes module 3014-i, which is adapted to provide the parasitic current of the preceding circuit 301-i-1 to the current mirror input composed of transistors 3011-i and 3012-i. More specifically, module 3014-i is adapted to provide current Igi-2 to node Ai. Figure 7 An example embodiment of the description module 301-i.

[0088] Figure 7 It is a combination Figure 6 Circuit diagram of an example embodiment of the described module 3014-i.

[0089] Module 3014-i includes i-1 transistors Tj, where j is an integer between 0 and i-2, which are arranged in parallel between nodes VDD and Ai. More specifically, the drain of transistor Tj is linked (preferably connected) to node Ai, and the source of transistor Tj is linked (preferably connected) to node VDD. The gate of each transistor Tj is linked (preferably connected) to nodes A0, ..., Ai-2 of the preceding circuit 301-i. More specifically, the gate of transistor T0 is linked (preferably connected) to node A0, the gate of transistor T1 is linked (preferably connected) to node A1, and so on. In other words, each transistor Tj is a current mirror of transistor 3011-j of circuit 301-j ranked j. Transistors Tj are of the same type as transistor 201. Figure 6 In this configuration, transistor Tj is a PMOS transistor. Therefore, each transistor Tj provides a current Igj-2-Igj-1 at its drain, and the current Igj-2-Igj-1 flows from the drain of transistor Tj to node Ai.

[0090] Module 3014-i also includes a current source S adapted to provide a current Iref. More specifically, the current source S is adapted to provide this current Iref to node Ai.

[0091] Figure 8 This is a circuit diagram of an example embodiment of a device 400 similar to device 300, where K equals 2.

[0092] The device 400 includes two transistors 201 and 202 connected as a current mirror, wherein transistor 201 is connected as a diode. The current mirror receives a current Iref supplied by a current source 203 at its input node (corresponding to the drain of transistor 201).

[0093] Device 400 also includes two circuits 301-1 and 301-2, in Figure 8 The middle section is defined by a dashed line.

[0094] Circuit 301-1 includes transistors 3011-1, 3012-1, 3013-1, T0, and current source S, arranged and connected as follows: Figure 6 and Figure 7 As described.

[0095] Circuit 301-2 includes transistors 3011-2, 3013-2, T0, and current source S, arranged and connected as follows: Figure 6 and Figure 7 As described. Circuit 301-2 does not include output node B2, therefore transistor 3011-2 is not included.

[0096] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined, and other variations will be readily apparent to them.

[0097] Finally, based on the functional descriptions provided above, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art.

[0098] While the invention has been described with reference to exemplary embodiments, this description is not intended to be limiting. Referring to the specification, those skilled in the art will clearly understand various modifications and combinations of exemplary embodiments and other embodiments of the invention. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. An electronic device comprising: A first transistor and a second transistor are connected as a current mirror, wherein the first transistor is connected in a diode configuration; as well as A first circuit is configured to provide a first current, the first current being equal to the first gate current of the first transistor multiplied by the size ratio of the first transistor to the second transistor. The first circuit includes K second circuits arranged in a cascaded manner. Where K is a relative integer. Each of the second circuits is configured to isolate parasitic current from the preceding circuit, and The second circuit ranked i includes: an input node (Ai) connected to the output node of the second circuit ranked i-1; a first output node (Bi) connected to the input node of the second circuit ranked i+1; and a second output node (NBi) connected to the second conductive terminal (S) of the second transistor (202), wherein i varies between 1 and K.

2. The apparatus of claim 1, wherein the first circuit is connected to a first node, the first node being interconnected with a first transistor gate of the first transistor and a second transistor gate of the second transistor, and wherein the first circuit is connected to a second node, the second node being interconnected with a first conductive terminal of the first transistor and a first conductive terminal of the second transistor.

3. The apparatus of claim 2, wherein the first circuit is configured to provide the first current to a second conductive terminal of the second transistor.

4. The apparatus of claim 3, wherein the second node is configured to receive a power supply voltage VDD.

5. The apparatus of claim 1, wherein the first transistor and the second transistor are P-type MOS transistors.

6. The apparatus of claim 1, wherein the first circuit includes a first module configured to isolate the first gate current and the first current mirror.

7. The apparatus of claim 6, wherein the first current mirror comprises a third transistor and a fourth transistor, the third transistor being diode-connected, and wherein the second gate current of the second transistor and the third transistor is negligible relative to the first gate current.

8. The apparatus of claim 7, wherein the third transistor and the fourth transistor are P-type MOS transistors having a double oxide layer.

9. The apparatus of claim 7, wherein the size ratio of the third transistor and the fourth transistor is equal to the size ratio of the first transistor and the second transistor.

10. The apparatus of claim 6, wherein the first current mirror comprises a fifth transistor and a sixth transistor, the fifth transistor being diode-connected, and wherein the third gate current of the fifth transistor is proportional to the first gate current.

11. The apparatus of claim 10, wherein the third gate current is equal to half of the first gate current, and wherein the size ratio of the fifth transistor and the sixth transistor is equal to twice the size ratio of the first transistor and the second transistor.

12. The apparatus according to claim 1, wherein K equals 2.

13. The apparatus of claim 1, wherein K equals 3.

14. An electronic device comprising: A first transistor and a second transistor are connected as a current mirror, wherein the first transistor is connected in a diode configuration; as well as A first circuit is configured to provide a first current, the first current being equal to the first gate current of the first transistor multiplied by the size ratio of the first transistor to the second transistor. The first circuit includes K second circuits arranged in a cascaded manner. Where K is a relative integer. Each of the second circuits is configured to isolate parasitic currents from the preceding circuit, and Each of the second circuits includes: The second current mirror includes a seventh MOS transistor of the same size; The third current mirror includes an eighth MOS transistor with a size ratio equal to that of the first transistor and the second transistor; and The second module is configured to isolate the parasitic current from another second circuit in the second circuit.

15. The apparatus of claim 14, wherein the first circuit is connected to a first node, the first node being interconnected with a first transistor gate of the first transistor and a second transistor gate of the second transistor, and wherein the first circuit is connected to a second node, the second node being interconnected with a first conductive terminal of the first transistor and a first conductive terminal of the second transistor.

16. The apparatus of claim 15, wherein the first circuit is configured to provide the first current to a second conductive terminal of the second transistor.

17. The apparatus of claim 16, wherein the second node is configured to receive a power supply voltage VDD.

18. The apparatus of claim 14, wherein the first transistor and the second transistor are P-type MOS transistors.

19. The apparatus of claim 14, wherein the second module is connected to the input node of the second circuit ranked between i-1 and i-2 and the interconnect node of the gates of the first transistor and the second transistor.

20. The apparatus of claim 14, wherein the second current mirror and the third current mirror share the same ninth transistor, the ninth transistor being diode-connected.

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