A multi-channel fast radio frequency sequence generation device for a cold atom interference gyroscope

Abstract

The present invention discloses a multi-channel fast radio frequency sequence generation device for a cold atom interference gyroscope, belonging to the field of quantum sensing technology. It includes a logic control module, a radio frequency signal generation module, a clock distribution module, a USB to RS232 module, a three-dimensional cooling light timing generation module, a Raman light timing generation module, a repumping light timing generation module, a quenching light timing generation module, and a two-dimensional cooling light timing generation module. By writing all the radio frequency signal information required for atomic interference into the internal registers of the DDS chip, the defect that the radio frequency signal parameters need to be reconfigured for the DDS chip during the interference timing process is overcome, and fast switching of the radio frequency frequency can be achieved within about two hundred nanoseconds. By controlling 8 DDS chips with an FPGA, 8-channel radio frequency signal output is realized. When modulating the radio frequency frequency in the DDS single-frequency or RAM mode, the DRG mode can be used to modulate the radio frequency amplitude or phase simultaneously.

Description

Technical Field

[0001] The present invention relates to the technical field of quantum sensing, and particularly to a multi-channel fast radio frequency sequence generation device for a cold atom interference gyroscope. Background Art

[0002] A cold atom interference gyroscope is an instrument for measuring angular velocity based on matter wave interference and the Sagnac effect. Since the de Broglie wavelength of cold atoms is shorter than the wavelength of light waves and the movement speed of cold atoms is much smaller than the speed of light, in the case of the same interference loop area, the theoretical sensitivity of a cold atom interference gyroscope is several orders of magnitude higher than that of an optical gyroscope. As a high-precision measurement instrument, the cold atom interference gyroscope has important potential application values in basic scientific research fields such as high-precision tests of general relativity and in the field of inertial navigation.

[0003] During the process of measuring the angular velocity of a carrier by a cold atom interference gyroscope, it is necessary to use multiple lasers to cool and trap atoms, split, reverse, and combine atomic wave packets, and detect the final state of atoms after atomic interference is completed. In different operation stages, different laser frequencies and powers are required. In order to change parameters such as the frequency of multiple lasers, usually multiple lasers are input into multiple acousto-optic modulators, and the frequency and other parameters of the radio frequency signals input into the multiple acousto-optic modulators are changed to correspondingly change the frequency and other parameters of the lasers output from the multiple acousto-optic modulators. In addition, the method of using multiple commercial radio frequency devices to generate multiple radio frequency signals commonly used in a laboratory environment is not conducive to the integration and miniaturization of a cold atom interference gyroscope. Therefore, developing an integrated multi-channel radio frequency sequence generation device is of great significance for promoting the practical engineering application of a cold atom interference gyroscope.

[0004] There is a publicly available Chinese patent "DDS Frequency Hopping Device for Controlling Laser Timing in a Cold Atom Interferometer" (Publication No.: CN 106647926 A, Publication Date: May 10, 2017), which describes that a host computer controls a DDS chip to generate radio frequency signals required for atomic velocity selection, microwave mixing, and π / 2, π, π / 2 Raman pulses through an ARM chip and a CPLD chip. Since radio frequency control parameters need to be transmitted from the host computer to the ARM chip, then from the ARM chip to the CPLD chip, and finally to the internal register of the DDS chip, there is a delay of the order of microseconds in frequency switching during the generation of the radio frequency timing, while the shortest laser pulse in a cold atom interference gyroscope only lasts for a few microseconds. In addition, this patented technology can only provide a radio frequency signal for one channel. Therefore, this publicly available patented technology cannot well meet the requirements of a cold atom interference gyroscope.

[0005] Another publicly available Chinese patent, "An Eight-channel DDS Signal Source Board" (Publication No.: CN 101662301 A, Publication Date: March 3, 2010), describes using an FPGA to control 8 DDS chips to generate 8 RF signals. Since the modulation modes of the RF signals in this patent only include single-frequency mode and sweep-frequency mode, it cannot meet the requirements of a cold atom interference gyroscope for synchronously scanning the RF frequency and RF amplitude during sub-Doppler cooling of atoms.

[0006] There is also another publicly available Chinese patent, "Reference Frequency Source Device and Method for Laser Output Control of a Cold Atom Interferometer" (Publication No.: CN 110690641 A, Publication Date: January 14, 2020), which uses an FPGA to control a DDS chip to achieve fixed-frequency output, frequency-hopping output, and sweep-frequency output of RF signals. On the one hand, this device can only output RF signals of one channel. On the other hand, only one of the fixed-frequency, frequency-hopping, and sweep-frequency modes can be selected to modulate the output RF signals. However, during the polarization gradient cooling process of atoms, it is necessary to scan both the RF frequency and the RF amplitude. Therefore, the RF signal modulation mode provided by this patent cannot well meet the requirements of a cold atom interference gyroscope.

[0007] In summary, the existing publicly available patented technologies have not solved the problems of generating RF timing sequences with fast frequency switching during the generation of multi-channel RF sequences and generating RF timing sequences that can synchronously scan laser frequency and amplitude for multi-channels. Solving these problems contributes to the engineering application of cold atom interference gyroscopes. Summary of the Invention

[0008] The purpose of the present invention is to overcome the shortcomings of the existing technology, such as the small number of RF signal channels, slow RF frequency switching speed, and inability to simultaneously scan RF frequency and amplitude, and solve the problems of generating RF timing sequences with fast frequency switching for multi-channels and generating RF timing sequences that can synchronously scan RF amplitude and frequency for multi-channels, and can meet the requirements of a cold atom interference gyroscope for generating multi-channel RF timing sequences.

[0009] The above object of the present invention is achieved by the following technical means:

[0010] A multi-channel fast RF sequence generation device for a cold atom interference gyroscope includes a logic control module, and also includes an RF signal generation module and a Raman light timing generation module. The logic control module includes an FPGA.

[0011] The Raman light timing generation module is used to save the Raman light timing configuration parameters and convert the Raman light timing configuration parameters into the internal register configuration values of the first DDS chip. The generation of the Raman light timing specifically includes a frequency generation step and a phase scanning step:

[0012] Frequency generation steps: When the FPGA detects the rising edge of the trigger signal generated by the external input radio frequency timing, modulate the radio frequency signal f11 using the frequency information contained in the first single-frequency Profile register, drive the AOM to turn off the laser field and maintain it for a time T11. When the timing of T11 ends, generate the radio frequency signal f12 required for the atomic state-selective laser pulse using the frequency information contained in the second single-frequency Profile register and maintain it for a time T12. When the timing of T12 ends, turn off the laser field using the frequency information contained in the first single-frequency Profile register and maintain it for a time T13. When the timing of T13 ends, generate the radio frequency signal f13 required for the π / 2 laser pulse using the frequency information contained in the third single-frequency Profile register and maintain it for a time T14. When the timing of T14 ends, turn off the laser field using the frequency information contained in the first single-frequency Profile register and maintain it for a time T15. When the timing of T15 ends, generate the radio frequency signal f14 required for the π laser pulse using the frequency information contained in the fourth single-frequency Profile register and maintain it for a time T16. When the timing of T16 ends, turn off the laser field using the frequency information contained in the first single-frequency Profile register and maintain it for a time T17. When the timing of T17 ends, generate the radio frequency signal f15 required for the second π / 2 laser pulse using the frequency information contained in the fifth single-frequency Profile register and maintain it for a time T18. The above times T11 to T18 are all set times, and are respectively timed by a timer.

[0013] Phase scanning steps: Before the end moment of the above T17 timing set the DRCTL pin of the first DDS chip to 1 in the time period to start the phase scanning of the radio frequency signal. Among them, is the phase step, and Δt is the step time corresponding to the phase step . When after n×Δt time, set the DRHOLD pin of the first DDS chip to 1, where n is the number of phase steps. The phase value of the radio frequency signal generated by the first DDS chip becomes In the T18 time period, the phase value of the second π / 2 laser pulse becomes When the second π / 2 laser pulse ends, set both the DRCTL pin and the DRHOLD pin of the first DDS chip to 0, and start to reverse-scan the phase of the radio frequency signal generated by the first DDS chip. When after time period, the phase of the radio frequency signal generated by the first DDS chip decreases to 0 radians. Repeat the frequency generation steps and the phase scanning steps until after the second π / 2 laser pulse gradually scans through 2π phase, a complete interference fringe is obtained.

[0014] A multi-channel fast radio frequency sequence generation device for a cold atom interference gyroscope further includes a two-dimensional cooling light timing generation module (18). The two-dimensional cooling light timing generation module (18) is used to store two-dimensional cooling light timing configuration parameters and convert the two-dimensional cooling light timing configuration parameters into internal register configuration values of a second DDS chip.

[0015] When the FPGA detects the rising edge of the externally input radio frequency timing generation trigger signal 02, it uses the frequency information contained in the first single-frequency Profile register to generate the radio frequency f21 required for the two-dimensional cooling laser pulse and maintains it for a time T21. When the timer ends the timing of the T21 time, it uses the frequency information contained in the second single-frequency Profile register to generate the radio frequency signal f22 to turn off the laser field and maintains it for a time T22.

[0016] The above T21 time to T22 time are all set times and are timed by the timer respectively.

[0017] A multi-channel fast radio frequency sequence generation device for a cold atom interference gyroscope further includes a quenching light timing generation module. The quenching light timing generation module is used to store quenching light timing configuration parameters and convert the quenching light timing configuration parameters into internal register configuration values of a third DDS chip.

[0018] When the FPGA detects the rising edge of the externally input radio frequency timing generation trigger signal 02, it uses the frequency information contained in the first single-frequency Profile register to generate the radio frequency signal f31 to turn off the laser field and maintains it for a time T31. When the timer ends the timing of the T31 time, it uses the frequency information contained in the second single-frequency Profile register to generate the radio frequency signal f32 corresponding to the laser pulse required to blow away the atoms in the non-target state after state selection and maintains it for a time T32. When the timer ends the timing of the T32 time, it uses the frequency information contained in the first single-frequency Profile register to turn off the laser field and maintains it for a time T33.

[0019] The above T31 time to T33 time are all set times and are timed by the timer respectively.

[0020] A multi-channel fast radio frequency sequence generation device for a cold atom interference gyroscope further includes a repumping light timing generation module. The repumping light timing generation module is used to store repumping light timing configuration parameters and convert the repumping light timing configuration parameters into internal register configuration values of a fourth DDS chip.

[0021] When the FPGA detects the rising edge of the trigger signal 02 generated by the externally input radio frequency timing, it uses the frequency information contained in the first single-frequency Profile register to generate the radio frequency signal f41 and maintains it for the time T41, which is used to generate a repumping light pulse during the cooling and trapping of atoms to form a cyclic transition. When the timer ends the timing of the time T41, it uses the frequency information contained in the second single-frequency Profile register to generate the radio frequency signal f42 to turn off the laser field and maintains it for the time T42. When the timer ends the timing of the time T42, it uses the frequency information contained in the third single-frequency Profile register to generate the radio frequency signal f43 and maintains it for the time T43, which is used to repump the atoms for normalized detection after the atomic interference is completed and the first detection is performed. When the timer ends the timing of the time T43, it uses the frequency information contained in the second single-frequency Profile register to generate the radio frequency signal f42 to turn off the laser field and maintains it for the time T44.

[0022] The above times T41 to T44 are all set times, and the timing is respectively performed by the timer.

[0023] A multi-channel fast radio frequency sequence generation device for a cold atom interference gyroscope further includes a four-channel three-dimensional cooling light timing generation module. The four-channel three-dimensional cooling light timing generation module is used to store the four-channel three-dimensional cooling light timing configuration parameters and convert the four-channel three-dimensional cooling light timing configuration parameters into the configuration values of the internal registers of the fifth to eighth DDS chips respectively. The internal registers of the fifth to eighth DDS chips all include a RAM register and six RAM Profile registers. Denote the six RAM Profile registers as the first RAM Profile register to the sixth RAM Profile register respectively. The starting address and the ending address stored in the RAM register of the corresponding frequency control word are stored in the first RAM Profile register to the sixth RAM Profile register.

[0024] When the FPGA detects the rising edge of the trigger signal generated by the externally input radio frequency timing, it generates a radio frequency signal f51 within the start address and end address range of the first RAM profile register and maintains it for a time T51 to load atoms. When the timer ends the timing of time T51, it generates a radio frequency signal f52 within the start address and end address range of the second RAM Profile register and maintains it for a time T52 to eject atoms. When the timer ends the timing of time T52, it generates a radio frequency signal f53 using multiple frequency points within the start address and end address range of the third RAM Profile register and maintains it for a time T53, gradually scanning the radio frequency and synchronously scanning the radio frequency amplitude in the DRG mode to perform polarization gradient cooling on the atoms. When the timer ends the timing of time T53, it generates a radio frequency signal f54 within the start address and end address range of the fourth RAM Profile register and maintains it for a time T54 to turn off the laser field. When the timer ends the timing of time T54, it generates a radio frequency signal f55 within the start address and end address range of the fifth RAM Profile register and maintains it for a time T55 for the first detection of the atomic population after atomic interference is completed. When the timer ends the timing of time T55, it generates a radio frequency signal f54 within the start address and end address range of the fourth RAM Profile register and maintains it for a time T56 to turn off the laser field. When the timer ends the timing of time T56, it generates a radio frequency signal f56 within the start address and end address range of the sixth RAM Profile register and maintains it for a time T57 for the second detection of the atomic population after atomic interference is completed. When the timer ends the timing of time T57, it generates a radio frequency signal f54 within the start address and end address range of the fourth RAM Profile register and maintains it for a time T58 to turn off the laser field. The above times T51 to T58 are all set times and are timed by the timer respectively.

[0025] The present invention has the following beneficial effects compared with the prior art:

[0026] Since all the RF information required for atomic interference has been written into the internal registers of the DDS chip before the start of the interference timing, the drawback that the RF signal parameters need to be reconfigured for the DDS chip during the interference timing is overcome, greatly improving the frequency switching speed. Thanks to the fact that the internal static memory of the DDS chip can store multiple frequency points, the requirement of continuously switching frequencies multiple times in the polarization gradient cooling timing can be met. At the same time, the DRG mode of the DDS can be used to scan the RF amplitude simultaneously. In addition, thanks to the ability of the FPGA to execute instructions in parallel, the 8-channel RF signals generated by controlling 8 DDS chips by the FPGA have good time synchronization. In summary, the feature of the present invention is that it can simultaneously output 8-channel RF timings that can complete rapid frequency switching within about 200 nanoseconds and can synchronously scan the RF frequency and amplitude, which are used to generate laser pulse timings to manipulate atoms. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a functional module block diagram of the present invention;

[0028] Figure 2 is a schematic diagram of the Raman light timing generation process of the present invention;

[0029] Figure 3 is a schematic diagram of the two-dimensional cooling light timing generation process of the present invention;

[0030] Figure 4 is a schematic diagram of the quenching light timing generation process of the present invention;

[0031] Figure 5 is a schematic diagram of the repumping light timing generation process of the present invention;

[0032] Figure 6 is a schematic diagram of the three-dimensional cooling light timing generation process of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] For the convenience of those of ordinary skill in the art to understand and implement the present invention, the present invention will be further described in detail below in conjunction with embodiments. It should be understood that the embodiments described herein are only used to illustrate and explain the present invention and are not used to limit the present invention.

[0034] A multi-channel fast RF sequence generation device for a cold atom interference gyro includes a logic control module 06, a logic control power module 11, a RF signal generation module 07, a RF signal generation power module 12, a clock distribution module 09, a clock distribution power module 10, a USB to RS232 module 05, a three-dimensional cooling light timing generation module 15, a Raman light timing generation module 16, a repumping light timing generation module 17, a two-dimensional cooling light timing generation module 18, a quenching light timing generation module 19, and an external trigger signal rising edge detection module 20.

[0035] Logic control module 06: This module contains an FPGA chip. Through the serial communication interface, it can configure the parameters of the internal registers of the DDS chip in the radio frequency signal generation module 07, and modulate the output radio frequency signal by changing the states of the PROFILE0 - PROFILE2 pins of the DDS chip. The logic control module 06 also contains a JTAG program download port for burning the FPGA program and a serial flash chip for solidifying the FPGA program.

[0036] Logic control power supply module 11: The externally input 12V voltage 04 is converted to 5V voltage by the 12V - to - 5V DC / DC conversion module 13, and then is respectively converted to 3.3V, 2.5V, and 1.2V voltages by three low - dropout voltage regulator chips to provide the operating voltage for the logic control module.

[0037] The radio frequency signal generation module 07 contains 8 DDS chips (AD9910), namely the first DDS chip to the eighth DDS chip. The complementary current signals output by each DDS chip are converted to voltage signals through the corresponding radio frequency transformers, and then are output through the corresponding low - pass filters, corresponding power amplifiers, and corresponding SMA radio frequency connectors. Four of the DDS chips are respectively used to generate the Raman light timing, the repump light timing, the two - dimensional cooling light timing, and the quenching light timing. The remaining four DDS chips are used to generate four identical three - dimensional cooling light timings, and a three - dimensional magneto - optical trap is formed by combining the use of mirrors and magnetic fields.

[0038] The radio frequency signal generation power supply module 12 outputs 6 supply voltages to provide the operating voltage for the DDS chips. The externally input 12V voltage 04 is converted to 5V voltage by the 12V - to - 5V DC / DC conversion module 13. The 5V voltage is then respectively converted to 3.3V digital power supply and 3.3V analog power supply by two low - dropout voltage regulator chips of the radio frequency signal generation power supply module 12 to supply power to the 8 DDS chips. In addition to the 3.3V supply voltage, the DDS chips also require a 1.8V supply voltage. The externally input 12V voltage 04 is converted to 3.3V voltage by the 12V - to - 3.3V DC / DC conversion module 14, and then three 1.8V analog power supplies are generated by the other three low - dropout voltage regulator chips of the radio frequency signal generation power supply module 12 to supply power to the 3rd pin, the 6th pin, and the 89 / 92nd pins of the 8 DDS chips respectively. The 1.8V digital power supply for each DDS chip is provided by a separate low - dropout voltage regulator chip of the radio frequency signal generation power supply module 12, which converts the 3.3V voltage output by the 12V - to - 3.3V DC / DC conversion module 14 to 1.8V.

[0039] The clock distribution module 09 includes a single-ended to differential signal chip and a clock buffer chip. The single-ended to differential signal chip receives the externally input single-ended clock signal 03 through an SMA RF connector. The input single-ended clock signal 03 is converted into an LVDS differential clock signal by the single-ended to differential signal chip to improve the common-mode noise suppression ability of the clock signal. Then, 9 LVDS differential signals are output through the clock buffer chip. Among them, 8 LVDS differential signals are respectively input to the clock input pins of 8 DDS chips in the RF signal generation module 07, and the other 1 LVDS differential signal is input to the logic control module 06 as the clock reference for the FPGA.

[0040] The clock distribution power supply module 10 uses a low-dropout voltage regulator chip to convert the 5V voltage output by the 12V to 5V DC / DC conversion module 13 into 3.3V voltage to provide the operating voltage for the single-ended to differential signal chip and the clock buffer chip.

[0041] The USB to RS232 module 05 is connected to the host computer 01 through a mini USB female socket and a USB cable. The USB-to-UART bridge chip is used to convert the USB signal into an RS232 signal for receiving the RF signal parameter information input by the user.

[0042] The Raman optical timing generation module 16 is used to save the Raman optical timing configuration parameters and convert the Raman optical timing configuration parameters into the configuration values of the internal registers of the first DDS chip (including the first single-frequency Profile register to the fifth single-frequency Profile register). The generation of the Raman optical timing includes a frequency generation step and a phase scanning step. The frequency generation step includes: after the circuit board is powered on, the internal registers of the first DDS chip (including the first single-frequency Profile register to the fifth single-frequency Profile register) will be configured according to the Raman optical timing configuration parameters in the Raman optical timing generation module 16. When the FPGA detects that the user has re-entered new Raman optical timing configuration parameters into the Raman optical timing generation module 16, the internal registers of the first DDS chip will be reconfigured. After the internal registers of the first DDS chip are set, when the FPGA detects the rising edge of the externally input radio frequency timing generation trigger signal 02 (monitored by the external trigger signal rising edge detection module 20), the radio frequency signal f11 is modulated using the frequency information contained in the first single-frequency Profile register, and the AOM is driven to turn off the laser field and maintain it for a time T11. When the timer T11 time expires, the radio frequency signal f12 required for generating the atomic state-selective laser pulse is generated using the frequency information contained in the second single-frequency Profile register and maintained for a time T12. When the timer T12 time expires, the laser field is turned off using the frequency information contained in the first single-frequency Profile register and maintained for a time T13. When the timer T13 time expires, the radio frequency signal f13 required for generating the π / 2 laser pulse is generated using the frequency information contained in the third single-frequency Profile register and maintained for a time T14. When the timer T14 time expires, the laser field is turned off using the frequency information contained in the first single-frequency Profile register and maintained for a time T15. When the timer T15 time expires, the radio frequency signal f14 required for generating the π laser pulse is generated using the frequency information contained in the fourth single-frequency Profile register and maintained for a time T16. When the timer T16 time expires, the laser field is turned off using the frequency information contained in the first single-frequency Profile register and maintained for a time T17. When the timer T17 time expires, the radio frequency signal f15 required for generating the second π / 2 laser pulse is generated using the frequency information contained in the fifth single-frequency Profile register and maintained for a time T18. When the timer T18 time expires, it is detected again whether the user has entered new Raman optical configuration parameters. The above T11 time to T18 time are all set times and are timed by the timer respectively.

[0043] The two-dimensional cooling light timing generation module 18 is used to save the two-dimensional cooling light timing configuration parameters and convert the two-dimensional cooling light timing configuration parameters into the configuration values of the internal registers of the second DDS chip (including the first single-frequency Profile register and the second single-frequency Profile register). After the circuit board is powered on, the internal registers of the second DDS chip (including the first single-frequency Profile register and the second single-frequency Profile register) will be configured according to the two-dimensional cooling light timing configuration parameters in the two-dimensional cooling light timing generation module 18. When the FPGA detects that the user has re-entered new two-dimensional cooling light configuration parameters into the two-dimensional cooling light timing generation module 18, the internal registers of the DDS chip (including the first single-frequency Profile register and the second single-frequency Profile register) will be reconfigured. When the FPGA detects the rising edge of the externally input radio frequency timing generation trigger signal 02 (monitored by the external trigger signal rising edge detection module 20), the radio frequency frequency f21 required for generating the two-dimensional cooling laser pulse is generated using the frequency information contained in the first single-frequency Profile register and maintained for a time T21. When the timer T21 timing ends, the radio frequency signal f22 is generated using the frequency information contained in the second single-frequency Profile register to turn off the laser field and maintained for a time T22. When the timer T22 timing ends, it is detected again whether the user has entered new two-dimensional cooling light configuration parameters. The above times T21 to T22 are all set times and are timed by the timer respectively.

[0044] The quenching light timing generation module 19 is used to save the quenching light timing configuration parameters and convert the quenching light timing configuration parameters into the configuration values of the internal registers of the third DDS chip (including the first single-frequency Profile register and the second single-frequency Profile register). After the circuit board is powered on, the internal registers of the third DDS chip (including the first single-frequency Profile register and the second single-frequency Profile register) will be configured according to the quenching light timing configuration parameters in the quenching light timing generation module 19. When the FGPA detects that the user has re-entered new quenching light configuration parameters into the quenching light timing generation module 19, the internal registers of the DDS chip (including the first single-frequency Profile register and the second single-frequency Profile register) will be reconfigured. When the FPGA detects the rising edge of the externally input radio frequency timing generation trigger signal 02 (monitored by the external trigger signal rising edge detection module 20), the radio frequency signal f31 is generated using the frequency information contained in the first single-frequency Profile register to turn off the laser field and maintain it for a time T31. When the timer T31 timing ends, the radio frequency signal f32 corresponding to the laser pulse required to blow away the atoms in the non-target state after state selection is generated using the frequency information contained in the second single-frequency Profile register and maintained for a time T32. When the timer T32 timing ends, the laser field is turned off using the frequency information contained in the first single-frequency Profile register and maintained for a time T33. When the timer T33 timing ends, it is detected again whether the user has entered new quenching light configuration parameters. The above times T31 to T33 are all set times and are timed by the timer respectively.

[0045] The optical pumping light timing generation module 17 is used to store the optical pumping light timing configuration parameters and convert the optical pumping light timing configuration parameters into the configuration values of the internal registers of the fourth DDS chip (including the first single-frequency Profile register to the third single-frequency Profile register). After the circuit board is powered on, the internal registers of the fourth DDS chip will be configured according to the optical pumping light timing configuration parameters in the optical pumping light timing generation module 17. When the FPGA detects that the user has re-entered new optical pumping light configuration parameters, the internal registers of the DDS chip (including the first single-frequency Profile register to the third single-frequency Profile register) will be reconfigured. When the FPGA detects the rising edge of the externally input radio frequency timing generation trigger signal 02 (monitored by the external trigger signal rising edge detection module 20), the radio frequency signal f41 is generated using the frequency information contained in the first single-frequency Profile register and maintained for a time T41, which is used to generate an optical pumping light pulse during the cooling and trapping of atoms to form a cyclic transition. When the timer T41 times out, the radio frequency signal f42 is generated using the frequency information contained in the second single-frequency Profile register to turn off the laser field and maintained for a time T42. When the timer T42 times out, the radio frequency signal f43 is generated using the frequency information contained in the third single-frequency Profile register and maintained for a time T43, so that after the atomic interference is completed and the first detection is performed, the atoms are pumped back for normalization detection. When the timer T43 times out, the radio frequency signal f42 is generated using the frequency information contained in the second single-frequency Profile register to turn off the laser field and maintained for a time T44. When the timer T44 times out, it is detected again whether the user has entered new optical pumping light configuration parameters. The above times T41 to T44 are all set times and are timed by the timer respectively.

[0046] The four-channel three-dimensional cooling light timing generation module 15 is used to store the four-channel three-dimensional cooling light timing configuration parameters and convert the four-channel three-dimensional cooling light timing configuration parameters into the configuration values of the internal registers of the fifth to eighth DDS chips respectively. Different from the Raman light, two-dimensional cooling light, quenching light and optical pumping light timing generation modules that use the single-frequency mode of the DDS to implement, the three-dimensional cooling light timing generation module uses the RAM mode of the DDS to implement. In the RAM mode, the single-frequency profile register becomes the RAM profile register. Since there are only 8 RAM profile registers inside the DDS chip, a complete radio frequency waveform can be divided into at most 8 segments of waveforms. The start address, end address and playback speed corresponding to each segment of the radio frequency waveform can be set in the corresponding RAM profile register. In the order of the sizes of the start address and the end address, the frequency points within the range defined by the start and end addresses will be sequentially written into the internal static memory with the address of 0x16.

[0047] When the circuit board is powered on, the internal registers of the fifth to eighth DDS chips are respectively configured with the default three-dimensional cooling light timing configuration parameters in the four-channel three-dimensional cooling light timing generation module 15. The internal registers of the configured fifth to eighth DDS chips all include a RAM register and six RAM Profile registers. Denote the six RAM Profile registers as the first RAM Profile register to the sixth RAM Profile register. The starting address and the ending address stored in the first RAM Profile register to the sixth RAM Profile register are the starting address and the ending address where the corresponding frequency control words are stored in the RAM register. When the user re-enters the three-dimensional cooling light timing configuration parameters, the internal registers of the fifth to eighth DDS chips will be reconfigured. After the register configuration is completed, when the FPGA detects the rising edge of the externally input radio frequency timing generation trigger signal 02 (monitored by the external trigger signal rising edge detection module 20), a radio frequency signal f51 is generated using the frequency points within the starting address and the ending address range of the first RAM profile register and maintained for a time T51, which is used to load atoms. When the timer T51 times out, a radio frequency signal f52 is generated using the frequency points within the starting address and the ending address range of the second RAM Profile register and maintained for a time T52, which is used to eject atoms. When the timer T52 times out, a radio frequency signal f53 is generated using multiple frequency points within the starting address and the ending address range of the third RAM Profile register and maintained for a time T53, gradually scanning the radio frequency and synchronously scanning the radio frequency amplitude using the DRG mode, which is used to perform polarization gradient cooling on atoms. When the timer T53 times out, a radio frequency signal f54 is generated using the frequency points within the starting address and the ending address range of the fourth RAM Profile register and maintained for a time T54, which is used to turn off the laser field. When the timer T54 times out, a radio frequency signal f55 is generated using the frequency points within the starting address and the ending address range of the fifth RAM Profile register and maintained for a time T55, which is used for the first detection of the atomic population number after atomic interference is completed. When the timer T55 times out, a radio frequency signal f54 is generated using the frequency points within the starting address and the ending address range of the fourth RAM Profile register and maintained for a time T56, which is used to turn off the laser field. When the timer T56 times out, a radio frequency signal f56 is generated using the frequency points within the starting address and the ending address range of the sixth RAM Profile register and maintained for a time T57, which is used for the second detection of the atomic population number after atomic interference is completed. When the timer T57 times out, a radio frequency signal f54 is generated using the frequency points within the starting address and the ending address range of the fourth RAM Profile register and maintained for a time T58, which is used to turn off the laser field.When the timing of timer T58 ends, re-detect whether the user has input new three-dimensional cooling light timing configuration parameters.

[0048] It should be noted that the generation of Raman light, two-dimensional cooling light, repump light, quenching light, and three-dimensional cooling light timing is concurrent and executed simultaneously inside the FPGA. At the same time, the multi-channel radio frequency timing generation device developed using the FPGA and 8 DDS chips has the characteristic of integration.

[0049] When obtaining the final atomic interference fringes, not only is it necessary to trigger the frequency of the radio frequency signal generated by the first DDS chip to be switched multiple times under the trigger of the externally input radio frequency timing generation trigger signal 02 to form π / 2-π-π / 2 laser pulses, but also each time it is triggered by the externally input trigger signal, the phase value of the radio frequency signal corresponding to the second π / 2 laser pulse needs to increase by a phase step value on the phase value of the previous trigger. In this way, when triggered by the externally input trigger signal times, the phase value of the radio frequency signal corresponding to the second π / 2 laser pulse will gradually increase from 0 radians to 2π radians, obtaining a complete interference fringe. It should be noted that it takes a step time Δt to complete the phase increment of the step.

[0050] To achieve the above purpose, when switching the radio frequency frequency multiple times in the single-frequency mode, the scanning pause mode of the DRG mode will be used simultaneously to make the phase value of the radio frequency signal corresponding to the second π / 2 laser pulse increase by a phase step value each time it is triggered. Specifically, the phase scanning steps include: when the FPGA detects the rising edge of the externally input radio frequency timing generation trigger signal 02 (received by the logic control module and recognized by the external trigger signal rising edge detection module 20), in the time period before the end of the T17 timing, set the DRCTL pin of the first DDS chip to 1 to start the phase scanning of the radio frequency signal, where is the phase step, and Δt is the step time corresponding to the phase step . When after n×Δt time (assuming that at this time the FPGA is triggered by the externally input trigger signal for the nth time, ), set the DRHOLD pin of the first DDS chip to 1. At this time, the phase value of the radio frequency signal generated by the first DDS chip will become n is the number of phase steps, Then, the phase value of the second π / 2 laser pulse within the T18 time period will also become That is, when the FPGA is triggered by the externally input trigger signal for the nth time, the phase value of the second π / 2 laser pulse is at the Add a phase increment on the basis of When the second π / 2 laser pulse ends, set both the DRCTL pin and the DRHOLD pin of the first DDS chip to 0, and start to reverse-scan the phase of the radio frequency signal generated by the first DDS chip. When passing through the time period, the phase of the radio frequency signal generated by the first DDS chip will be reduced to 0 radians. In this way, the phase of the radio frequency signal generated by the first DDS chip during T11 to T16 and the time period is always 0 radians. Repeat the frequency generation step and the phase scanning step until a complete interference fringe is obtained when the second π / 2 laser pulse gradually scans through 2π phase.

[0051] It should be emphasized again that since the radio frequency timing information has been written into the internal register of the DDS before the interference timing starts, during the occurrence of the interference timing, switching the radio frequency only requires changing the states of the PROFILE0~PROFILE2 pins of the DDS chip to select different profile registers. The delay of radio frequency frequency switching is only composed of the rising or falling edge time of the PROFILE pin and the delay between the change of the internal frequency value of the DDS and the change of the output radio frequency signal. In this way, during the occurrence of the radio frequency timing, the FPGA does not need to reconfigure the internal register of the DDS through the serial communication interface to change the radio frequency. By switching the radio frequency and actually measuring the instantaneous change of the corresponding laser light intensity, it is obtained that the radio frequency frequency switching can be completed within about two hundred nanoseconds.

[0052] It should be noted that the specific embodiments described in the present invention are only illustrative of the spirit of the present invention. Those skilled in the art to which the present invention pertains can make various modifications or supplements to the described specific embodiments or use similar ways to replace them, but will not deviate from the spirit of the present invention or exceed the scope defined by the appended claims.

Claims

1. A multi-channel fast radio frequency sequence generation device for a cold atom interference gyroscope, comprising a logic control module (06), characterized in that, It also includes a radio frequency signal generation module (07) and a Raman optical timing generation module (16). The logic control module (06) includes an FPGA. The Raman optical timing generation module (16) is used to store Raman optical timing configuration parameters and convert the Raman optical timing configuration parameters into internal register configuration values of the first DDS chip. The generation of the Raman optical timing specifically includes a frequency generation step and a phase scanning step: Frequency generation step: When the FPGA detects the rising edge of the externally input radio frequency timing generation trigger signal (02), it modulates the radio frequency signal f11 using the frequency information contained in the first single-frequency Profile register, drives the AOM to turn off the laser field and maintain it for a time T11. When the timing of the time T11 ends, it generates the radio frequency signal f12 required for the atomic state-selective laser pulse using the frequency information contained in the second single-frequency Profile register and maintains it for a time T12. When the timing of the time T12 ends, it turns off the laser field using the frequency information contained in the first single-frequency Profile register and maintains it for a time T13. When the timing of the time T13 ends, it generates the radio frequency signal f13 required for the π / 2 laser pulse using the frequency information contained in the third single-frequency Profile register and maintains it for a time T14. When the timing of the time T14 ends, it turns off the laser field using the frequency information contained in the first single-frequency Profile register and maintains it for a time T15. When the timing of the time T15 ends, it generates the radio frequency signal f14 required for the π laser pulse using the frequency information contained in the fourth single-frequency Profile register and maintains it for a time T16. When the timing of the time T16 ends, it turns off the laser field using the frequency information contained in the first single-frequency Profile register and maintains it for a time T17. When the timing of the time T17 ends, it generates the radio frequency signal f15 required for the second π / 2 laser pulse using the frequency information contained in the fifth single-frequency Profile register and maintains it for a time T18. The above times T11 to T18 are all set times and are respectively timed by a timer. Phase scanning step: Before the end time of the above-mentioned T17 timing Set the DRCTL pin of the first DDS chip to 1 in the time period to start the phase scanning of the radio frequency signal. Among them, is the phase step, and Δt is the step time corresponding to the phase step When the time of n×Δt has passed, set the DRHOLD pin of the first DDS chip to 1, where n is the number of phase steps. The phase value of the radio frequency signal generated by the first DDS chip becomes In the T18 time period, the phase value of the second π / 2 laser pulse becomes When the second π / 2 laser pulse ends, set both the DRCTL pin of the first DDS chip and the DRHOLD pin of the first DDS chip to 0, and start to reverse-scan the phase of the radio frequency signal generated by the first DDS chip. When passing through After the time period, the phase of the radio frequency signal generated by the first DDS chip decreases to 0 radians. Repeat the frequency generation step and the phase scanning step until a complete interference fringe is obtained after the second π / 2 laser pulse gradually scans through 2π phases.

2. The multi-channel fast radio frequency sequence generation device for a cold atom interference gyroscope according to claim 1, characterized in that It also includes a two-dimensional cooling optical timing generation module (18). The two-dimensional cooling optical timing generation module (18) is used to store two-dimensional cooling optical timing configuration parameters and convert the two-dimensional cooling optical timing configuration parameters into internal register configuration values of the second DDS chip. When the FPGA detects the rising edge of the externally input radio frequency timing generation trigger signal 02, it generates the radio frequency f21 required for the two-dimensional cooling laser pulse using the frequency information contained in the first single-frequency Profile register and maintains it for a time T21. When the timing of the timer for the time T21 ends, it generates the radio frequency signal f22 to turn off the laser field using the frequency information contained in the second single-frequency Profile register and maintains it for a time T22. The above times T21 to T22 are all set times and are respectively timed by a timer.

3. The multi-channel fast radio frequency sequence generation device for a cold atom interference gyroscope according to claim 1, wherein It also includes a quenching optical timing generation module (19). The quenching optical timing generation module (19) is used to store quenching optical timing configuration parameters and convert the quenching optical timing configuration parameters into internal register configuration values of the third DDS chip. When the FPGA detects the rising edge of the trigger signal 02 generated by the externally input RF timing, it uses the frequency information contained in the first single-frequency Profile register to generate an RF signal f31 to turn off the laser field and maintain it for a time T31. When the timer's T31 time elapses, it uses the frequency information contained in the second single-frequency Profile register to generate an RF signal f32 corresponding to the laser pulse required to blow away the atoms in the non-target state after state selection and maintain it for a time T32. When the timer's T32 time elapses, it uses the frequency information contained in the first single-frequency Profile register to turn off the laser field and maintain it for a time T33. The above T31 time to T33 time are all set times, and are timed by the timer respectively.

4. The multi-channel fast radio frequency sequence generation device for a cold atom interference gyroscope according to claim 1, characterized in that, It further includes a repump light timing generation module (17). The repump light timing generation module (17) is used to store the repump light timing configuration parameters and convert the repump light timing configuration parameters into the internal register configuration values of the fourth DDS chip. When the FPGA detects the rising edge of the trigger signal 02 generated by the externally input RF timing, it uses the frequency information contained in the first single-frequency Profile register to generate an RF signal f41 and maintain it for a time T41, which is used to generate a repump light pulse during the cooling and trapping of atoms to form a cyclic transition. When the timer's T41 time elapses, it uses the frequency information contained in the second single-frequency Profile register to generate an RF signal f42 to turn off the laser field and maintain it for a time T42. When the timer's T42 time elapses, it uses the frequency information contained in the third single-frequency Profile register to generate an RF signal f43 and maintain it for a time T43, which is used to repump the atoms for normalized detection after the atomic interference is completed and the first detection. When the timer's T43 time elapses, it uses the frequency information contained in the second single-frequency Profile register to generate an RF signal f42 to turn off the laser field and maintain it for a time T44. The above T41 time to T44 time are all set times, and are timed by the timer respectively.

5. The multi-channel fast radio frequency sequence generation device for a cold atom interference gyroscope according to claim 1, wherein It further includes a four-channel three-dimensional cooling light timing generation module (15). The four-channel three-dimensional cooling light timing generation module (15) is used to store the four-channel three-dimensional cooling light timing configuration parameters and convert the four-channel three-dimensional cooling light timing configuration parameters into the configuration values of the internal registers of the fifth to eighth DDS chips respectively. The internal registers of the fifth to eighth DDS chips all include a RAM register and six RAM Profile registers. Denote the six RAM Profile registers as the first RAM Profile register to the sixth RAM Profile register. The starting address and ending address stored in the first RAM Profile register to the sixth RAM Profile register are the starting address and ending address where the corresponding frequency control word is stored in the RAM register. When the FPGA detects the rising edge of the trigger signal 02 generated by the externally input RF timing, it generates the RF signal f51 within the start address and end address range of the first RAM profile register and maintains it for the time T51, which is used to load atoms. When the timer ends the timing of the time T51, it generates the RF signal f52 within the start address and end address range of the second RAM Profile register and maintains it for the time T52, which is used to eject atoms. When the timer ends the timing of the time T52, it generates the RF signal f53 with multiple frequency points within the start address and end address range of the third RAM profile register and maintains it for the time T53, gradually scans the RF frequency and synchronously scans the RF amplitude using the DRG mode, which is used for polarization gradient cooling of atoms. When the timer ends the timing of the time T53, it generates the RF signal f54 within the start address and end address range of the fourth RAM profile register and maintains it for the time T54, which is used to turn off the laser field. When the timer ends the timing of the time T54, it generates the RF signal f55 within the start address and end address range of the fifth RAM profile register and maintains it for the time T55, which is used for the first detection of the atomic population after atomic interference. When the timer ends the timing of the time T55, it generates the RF signal f54 within the start address and end address range of the fourth RAM profile register and maintains it for the time T56, which is used to turn off the laser field. When the timer ends the timing of the time T56, it generates the RF signal f56 within the start address and end address range of the sixth RAM profile register and maintains it for the time T57, which is used for the second detection of the atomic population after atomic interference. When the timer ends the timing of the time T57, it generates the RF signal f54 within the start address and end address range of the fourth RAM profile register and maintains it for the time T58, which is used to turn off the laser field. The above times T51 to T58 are all set times and are timed by the timer respectively.

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