A multi-chip broadcast transmission method and multi-chip system based on AXI bus

Abstract

This invention relates to the field of data transmission technology for multi-chip systems, and discloses a multi-chip broadcast transmission method and system based on the AXI bus. By utilizing the existing and widely used AXI bus protocol and PCIe interface protocol, broadcast transmission between multiple chips is realized, which can significantly improve the transmission efficiency of multiple chips, increase data transmission bandwidth, and reduce latency caused by multiple transmissions. This invention allocates an independent address space for broadcast transmission, which does not overlap with other address spaces within the chip. This invention ensures the reliability of broadcast transmission through a tiered write reply function. The method provided by this invention supports broadcast transmission between multiple chips within a chiplet, broadcast transmission between multiple chiplets, and a hybrid of both. It supports broadcast transmission to any selectable destination within a multi-chip system.

Description

Technical Field

[0001] This invention relates to the field of data transmission technology for multi-chip systems, and in particular to a multi-chip broadcast transmission method based on the AXI bus. Background Technology

[0002] Multi-chip systems utilize chiplet technology, which breaks down a single chip into multiple smaller, higher-volume, and more cost-effective chips before packaging them together. Multiple bare chips can be packaged into a single chiplet, and then interconnected to achieve goals such as higher computing power and larger storage.

[0003] Currently, chip-to-chip interconnection mainly relies on high-speed serial or parallel interfaces. However, these interfaces only support data transmission between two physically connected chips, lack routing capabilities, and cannot effectively support broadcast transmission between multiple chips, especially in multi-chip system products with multi-level cascading and different topology connection methods.

[0004] The AXI (Advanced Extensible Interface) bus is an on-chip bus protocol proposed by ARM. This protocol separates read / write channels, address / control channels, and data channels, supporting unaligned transmissions, burst transmissions, and out-of-order access. The AXI bus is a high-performance, high-bandwidth, low-latency bus protocol. The AXI bus determines the destination address of the transmission through address decoding, but it does not support broadcast transmission or chip-to-chip transmission. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a multi-chip broadcast transmission method based on the AXI bus, which realizes broadcast transmission between multiple chips, greatly improves the transmission efficiency between multiple chips, and realizes high bandwidth and low latency data transmission.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0007] A multi-chip broadcast transmission method based on the AXI bus, wherein the host and the connected chip are connected via PCIe, and the broadcast transmission includes the following steps:

[0008] 1. The host writes the destination chip identification code and the actual write command into the router register inside the chip connected to the host.

[0009] 2. The router inside the chip connected to the host determines the destination chip for this broadcast transmission based on the received chip identification code;

[0010] 3. If the current chip is not the target chip, the received chip identification code and the formal write command will be written to the router register of the next cascaded chip. If the current chip is one of the target chips, the router will send the formal write command to the internal network of the current chip, modify the chip identification code to remove the current chip from the target chips, and then write the modified chip identification code and the formal write command to the router register of the next cascaded chip.

[0011] 4. After receiving the chip identification code and the formal write command, the next-level cascaded chip repeats the actions in step 3 above until the chip identification code does not contain the destination chip, and the transmission ends.

[0012] Preferably, the chip identification code is a binary code with a number of bits greater than or equal to the total number of chips. Different chips correspond to one bit of the chip identification code, and the chip corresponding to the bit with a chip identification code value of 1 is the target chip for this broadcast transmission.

[0013] Preferably, the chip identification code is sent via the AWUSER signal in the AXI protocol, and the actual write command is sent via PCIe.

[0014] Preferably, after the router completes the transmission of the chip identification code and the formal write command, its internal encoding module stores the chip ID information in the router's internal response module for comparison with the write response; after the router sends the formal write command to the internal network of the current chip, the internal network of the current chip sends the write response to the response module; after the response module collects all the write responses from the internal network of the current chip and the next-level chip, it sends the write response to the next-level chip or the host.

[0015] Preferably, the chip allocates a separate address space for broadcast transmission, which does not overlap with other address spaces within the chip.

[0016] Furthermore, based on the chip identification code, the router determines whether the current broadcast transmission needs to be sent to the internal network of the current chip. If so, it offsets the address of the broadcast transmission, converting it to the address space within the current chip, and completes the transmission to the internal network of the current chip. Afterward, it sets the bit corresponding to the current chip in the chip identification code to 0, effectively removing the current chip from the destination chip list.

[0017] Furthermore, the router's internal configuration register information records the chip identification code bits corresponding to the current chip and all downstream chips. Based on the internal configuration information and the received chip identification codes, the router selects the appropriate path for this broadcast transmission and sets the chip identification codes broadcast for each path to include only the destination chip on this path.

[0018] The present invention also provides a multi-chip system for broadcast transmission based on the AXI bus, which consists of several chips connected via PCIe. The feature is that each chip has an internal router, which can identify the target chip for broadcast transmission based on the chip identification code, and can send the actual write command to the internal network of the current chip and the router of the next cascaded chip. The router has an encoding module and a response module.

[0019] Preferably, the chips are connected in a linear manner, with each chip connected to one next-level cascaded chip.

[0020] Preferably, the chips are connected in a ring configuration, with each chip connected to one next-level cascaded chip, and the ends of the cascaded chips are connected end to end.

[0021] Preferably, the chips are connected in a tree-like manner, with each chip connecting to 1 to 3 cascaded chips at the next lower level.

[0022] Furthermore, the multi-chip system is composed of multiple separately packaged chip combinations, and one or more chips in different combinations are connected to one or more chips in other combinations through a PCIe interface.

[0023] The beneficial effects of adopting the above technical solution are as follows:

[0024] This invention provides a multi-chip broadcast transmission method and system based on the AXI bus. By utilizing the existing and widely used AXI bus protocol and PCIe interface protocol, it realizes broadcast transmission between multiple chips, which can significantly improve the transmission efficiency of multiple chips, increase data transmission bandwidth, and reduce latency caused by multiple transmissions. This invention allocates an independent address space for broadcast transmission, which does not overlap with other address spaces within the chip. This invention ensures the reliability of broadcast transmission through a tiered write-response function. The method provided by this invention supports broadcast transmission between multiple chips within a chiplet, broadcast transmission between multiple chiplets, and a hybrid of both. It supports broadcast transmission to any selectable destination within a multi-chip system. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the internal connections of the chip in this invention.

[0026] Figure 2 This is a schematic diagram of the routing module of the present invention.

[0027] Figure 3 This is a schematic diagram of the multi-chip linear connection of the present invention.

[0028] Figure 5 This is a schematic diagram of the multi-chip ring connection of the present invention.

[0029] Figure 4 This is a schematic diagram of the multi-chip tree connection of the present invention.

[0030] Figure 6 This is a schematic diagram of the multi-chip ring and tree hybrid connection of the present invention;

[0031] ① in the figure These are different transmission paths. Detailed Implementation

[0032] Example 1

[0033] This embodiment provides a broadcast transmission method for a multi-chip system based on the AXI bus, characterized in that the host and the connected chip are connected via PCIe, and the broadcast transmission includes the following steps:

[0034] Step 1: The host writes the destination chip identification code and the actual write command to the router register inside the chip connected to the host. The chip identification code (AWUSER) is a binary code with a number of bits greater than or equal to the total number of chips in this multi-chip interconnect system. The first bit represents the first chip (DIE0), the second bit represents the second chip (DIE1), and so on. If a bit is 1, it indicates that the corresponding chip is one of the write destinations for this broadcast transmission. For example, in a system with 8 interconnected chips, if this broadcast transmission will write to the 2nd, 5th, and 8th chips, then the chip identification code for this broadcast transmission would be 10010010.

[0035] Step two: The router inside the chip connected to the host determines the destination chip for this broadcast transmission based on the received chip identification code.

[0036] Step 3: If the current chip is not the target chip, the received chip identification code and the formal write command are written to the router register of the next cascaded chip. If the current chip is the target chip, the router sends the formal write command to the internal network of the current chip, modifies the chip identification code to remove the current chip from the target chip list, and then writes the modified chip identification code and the formal write command to the router register of the next cascaded chip.

[0037] Step four: After receiving the chip identification code and the formal write command, the next-level cascaded chip repeats the actions in step three until the chip identification code does not contain the target chip, at which point the transmission ends.

[0038] like Figure 1As shown, the external host or the upstream chip writes data into the chip through the PCIe interface of path ①. Before writing the actual write command (AW), the chip identification code of the target chip of this broadcast transmission (multicast) is written into the router.

[0039] After receiving the chip identification code and write command from the external host (HOST) or the upstream chip, the router places the chip identification code into the AWUSER signal of the AXI protocol, thereby unifying the chip's internal identification code and write command. During system initialization, the router configures initialization information through path ②, recording the chip identification code bit corresponding to the current chip, as well as the chip identification code bits corresponding to all downstream chips in three different directions, as shown in paths ④, ⑤, and ⑥.

[0040] The router determines whether to continue sending the command to the next-level chip based on whether the chip identification code is all zeros. For example, if the current chip is DIE0 and the router receives a chip identification code of 10010011, after sending it to the internal network of the current chip via path ③, the router sets the bit corresponding to the current chip in the chip identification code to 0, that is, the chip identification code is reset to 10010010. The router determines that it is not all zeros and will forward this command to the next cascaded chip again.

[0041] After a write command is sent to the current chip's internal network, the address of the broadcast transmission is translated into an internal chip address, and the chip identifier is removed. For example, the address translation involves extracting the lower 32 bits of the broadcast transmission address. If the broadcast transmission command address is 0xfff_0000_0000 to 0xfff_ffff_ffff, then the internal chip address space is 0x0000_0000 to 0xffff_ffff. Broadcast transmissions (multicast) allocate a separate address space that does not overlap with other internal chip address spaces, preventing address decoding errors within the chip.

[0042] Based on the initialization information in its internal configuration registers, the router selects the appropriate path for the commands to be forwarded and sets the chip identification code for each path to include only the destination chip on that path. For example, the router's internal register configuration information is: DIE1, DIE2, and DIE3 are forwarded via path ④; DIE4 and DIE5 are forwarded via path ⑤; and DIE6 and DIE7 are forwarded via path ⑥. At this time, the chip identification code value is 10010010. Based on the comparison results, the router will forward the command to DIE1 via path ④ (corresponding chip identification code 00000010); to DIE4 via path ⑤ (corresponding chip identification code 00010000); and to DIE7 via path ⑥ (corresponding chip identification code 10000000).

[0043] The chip identification code is sent via the AWUSER signal in the AXI protocol, and the actual write command is sent via PCIe. Since PCIe itself cannot transmit the AWUSER signal, before it is sent to the next-level chip via PCIe through paths ④⑤⑥, the chip identification code is first written into the router register inside the next-level chip, and then the write command is sent to the next-level chip through paths ④⑤⑥.

[0044] like Figure 2 As shown:

[0045] The router's internal encoder module compares the chip identification codes and, based on the comparison result, determines whether to transmit the data to the internal network or the next cascaded chip, and updates the chip identification code. Before transmitting to the next cascaded chip, the corresponding chip identification code is written to the router register of the next cascaded chip. After sending the write command, the encoder module writes the chip ID and AXI information containing the transmission information into the response module via path ⑦ for comparison in the write reply.

[0046] After the router sends the formal write command to the internal network of the current chip via path ③, the internal network of the current chip sends a write reply to the response module; the response module then sends the reply via path ③. Receive write responses from the current chip's internal network, and receive write responses from the next-level chip via paths ⑧⑨⑩. After all write responses are received, compare them with the internally stored AXI information. If the comparison is successful, proceed via path... Send a write reply to the next higher-level chip or host.

[0047] Example 2

[0048] like Figure 3 As shown, this embodiment provides a multi-chip system for broadcast transmission based on the AXI bus, which consists of several chips connected via PCIe. Each chip has an internal router that can identify the target chip for the broadcast transmission based on the chip identification code. The router can send the actual write command to the internal network of the current chip and the router of the next-level cascaded chip. The router has an encoding module and a response module. The chips are connected in a linear manner, with each chip connected to one next-level cascaded chip.

[0049] Example 3

[0050] like Figure 4As shown, this embodiment provides a multi-chip system for broadcast transmission based on the AXI bus, which consists of several chips connected via PCIe. Each chip has an internal router that can identify the target chip for the broadcast transmission based on the chip identification code and send the actual write command to the internal network of the current chip and the router of the next-level cascaded chip. The router has an encoding module and a response module. The chips are connected in a ring, with each chip connected to one next-level cascaded chip, and the chips are connected end to end.

[0051] Example 4

[0052] like Figure 5 As shown, this embodiment provides a multi-chip system for broadcast transmission based on the AXI bus, consisting of several chips connected via PCIe. Each chip has an internal router that can identify the target chip for the broadcast transmission based on the chip identification code. The router can send the actual write command to the internal network of the current chip and the router of the next cascaded chip. The router has an encoding module and a response module. The chips are connected in a tree structure. The chip connected to the host (DIE0) is connected to three chips (DIE1, DIE2, and DIE3) via the PICE interface. Chip DIE1 is connected to three chips (DIE4, DIE5, and DIE6) via the PICE interface. Chip DIE2 is connected to three chips (DIE7, DIE8, and DIE9) via the PICE interface. Chip DIE3 is connected to three chips (DIE10, DIE11, and DIE12) via the PICE interface.

[0053] Example 5

[0054] This embodiment provides a multi-chip system for broadcast transmission based on an AXI bus. The multi-chip system consists of four separately packaged chip combinations (Chiplet0, Chiplet1, Chiplet2, and Chiplet3). Chiplet0 includes four chips (DIE0, DIE1, DIE2, and DIE3) connected in a tree structure; Chiplet1 includes one chip (DIE4); Chiplet2 includes four chips (DIE5, DIE6, DIE7, and DIE8) connected in a tree structure; and Chiplet3 includes four chips (DIE9, DIE10, DIE11, and DIE12) connected in a tree structure.

[0055] Chip DIE1 is connected to chip DIE4 via a PICE interface, chip DIE2 is connected to chip DIE5 via a PICE interface, and chip DIE3 is connected to chip DIE9 via a PICE interface.

[0056] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A multi-chip broadcast transmission method based on an AXI bus, characterized in that, The host and the connected chip are connected via PCIe, and the broadcast transmission includes the following steps: Step 1: The host writes the destination chip identification code and the actual write command into the router register inside the chip connected to the host. Step two: The router inside the chip connected to the host determines the destination chip for this broadcast transmission based on the received chip identification code. Step 3: If the current chip is not the target chip, the received chip identification code and the formal write command are written to the router register of the next cascaded chip in sequence; if the current chip is the target chip, the router sends the formal write command to the internal network of the current chip, modifies the chip identification code to remove the current chip from the target chip, and then writes the modified chip identification code and the formal write command to the router register of the next cascaded chip in sequence. Step four: After receiving the chip identification code and the formal write command, the next-level cascaded chip repeats the actions in step three until the chip identification code does not contain the target chip, at which point the transmission ends.

2. The multi-chip broadcast transmission method based on the AXI bus according to claim 1, characterized in that, The chip identification code is a binary code with a number of bits greater than or equal to the total number of chips. Different chips correspond to one bit of the chip identification code, and the chip corresponding to the bit with a chip identification code value of 1 is the target chip for this broadcast transmission.

3. The multi-chip broadcast transmission method based on the AXI bus according to claim 1, characterized in that, The chip identification code is sent via the AWUSER signal in the AXI protocol, while the actual write command is sent via PCIe.

4. The multi-chip broadcast transmission method based on the AXI bus according to claim 1, characterized in that, After the router completes the transmission of the chip identification code and the formal write command, its internal encoding module stores the chip ID information in the router's internal response module for comparison with the write response. After the router sends the formal write command to the internal network of the current chip, the internal network of the current chip sends the write response to the response module. After the response module collects all the write responses from the internal network of the current chip and the next-level chip, it sends the write response to the next-level chip or the host.

5. The multi-chip broadcast transmission method based on the AXI bus according to claim 1, characterized in that, The chip allocates a separate address space for broadcast transmission, which does not overlap with other address spaces within the chip.

6. The multi-chip broadcast transmission method based on the AXI bus according to claim 2, characterized in that, Based on the chip identification code, the router determines whether the current broadcast transmission needs to be sent to the internal network of the current chip. If so, it offsets the address of the broadcast transmission and converts it to the address space inside the current chip, completing the transmission to the internal network of the current chip. After that, it sets the bit corresponding to the current chip in the chip identification code to 0, that is, it removes the current chip from the destination chip.

7. The multi-chip broadcast transmission method based on the AXI bus according to claim 2, characterized in that, The router's internal configuration register records the chip identification code bits corresponding to the current chip and all downstream chips. Based on the configuration information and the received chip identification codes, the router selects the appropriate path for this broadcast transmission and sets the chip identification codes transmitted on each path to include only the destination chip on this path.

8. A multi-chip system for broadcast transmission based on an AXI bus, comprising several chips connected via PCIe, each chip internally based on an AXI bus, characterized in that... The chip has an internal router module. The router module can identify the target chip for broadcast transmission based on the chip identification code and send the formal write command to the internal network of the current chip and the router of the next cascaded chip. The router module has an encoding module and a response module. The encoding module can compare and update the chip identification code and determine whether to send the transmission to the internal network or the next cascaded chip based on the comparison result. The response module can collect all write replies from the internal network of the current chip and the next chip and send the write replies to the previous chip or the host.

9. A multi-chip system for broadcast transmission based on an AXI bus according to claim 8, characterized in that, The chips are connected in a linear manner, with each chip connected to one next-level cascaded chip.

10. A multi-chip system for broadcast transmission based on an AXI bus according to claim 8, characterized in that, The chips are connected in a ring configuration, with each chip connected to one next-level cascaded chip, and the ends of the cascaded chips are connected end to end.

11. A multi-chip system for broadcast transmission based on an AXI bus according to claim 8, characterized in that, The chips are connected in a tree structure, with each chip connecting to 1 to 3 cascaded chips at the next lower level.

12. A multi-chip system for broadcast transmission based on an AXI bus according to any one of claims 8-11, characterized in that, The multi-chip system consists of multiple separately packaged chip combinations, with one or more chips in different combinations connected to one or more chips in other chip combinations via a PCIe interface.

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