Configurable multiway simd execution lane design method, vector operation unit, and processor

Abstract

This invention discloses a configurable multi-SIMD execution path design method, a vector operation unit, and a processor. The design method includes selecting the required SIMD execution paths based on the number of SIMD execution paths in macro parameters, and turning on the configurable switches of the required SIMD execution paths and turning off the configurable switches of the unused SIMD execution paths. Furthermore, it includes dynamically controlling the number of SIMD execution paths during use. This invention supports configuring multiple SIMD execution paths without changing the CPU front-end parameters during the design phase, shortening the CPU design and development cycle and reducing the area overhead required for performance improvement. It also supports configuring the number of SIMD execution paths after CPU tape-out to balance CPU performance and power consumption, allowing for flexible increases or decreases in the number of vector operation units, improving single-core CPU performance, up to twice the vector operation capability.

Description

Technical Field

[0001] This invention belongs to the field of microprocessor architecture and pipeline design technology in the field of microprocessor design, specifically involving a configurable multi-path SIMD execution design method, a vector operation unit, and a processor. Background Technology

[0002] Upgrading the architecture of high-performance CPUs is a crucial technique for improving hardware performance. Out-of-order superscalar technology is widely used in modern high-performance CPU architectures, and CPUs employing out-of-order superscalar technology are called superscalar processors. Superscalar processors can execute multiple instructions within a single cycle; out-of-order execution allows potentially parallel instructions to be executed out of the program's specified order. Out-of-order superscalar technology fully utilizes the instruction parallelism of a program through out-of-order execution, thereby improving processor performance. Currently, performance improvements in mainstream commercial CPUs are typically accompanied by the expansion of CPU architecture parameters. However, out-of-order superscalar technology involves relatively complex instruction control logic within the processor, and upgrading the architecture parameters of high-performance CPUs incurs significant hardware area overhead and a long design cycle. Therefore, how to achieve a configurable and lightweight design for multiple SIMD execution paths has become a critical technical problem that urgently needs to be solved. Summary of the Invention

[0003] The technical problem this invention aims to solve is as follows: Addressing the aforementioned problems in existing technologies, this invention provides a configurable multi-path SIMD execution design method, a vector operation unit, and a processor. This invention aims to solve the problems of long design cycles and large area overhead associated with improving the floating-point performance of high-performance CPUs. This invention supports configuring multiple SIMD execution paths without changing the CPU front-end parameters during the design phase, shortening the CPU design and development cycle and reducing the area overhead required for unit performance improvement. Simultaneously, it supports configuring the number of SIMD execution paths after CPU tape-out to balance CPU performance and power consumption. Through a configurable method, the number of vector operation units can be flexibly increased or decreased, improving the CPU's single-core performance, up to twice the vector operation capability.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0005] A configurable multi-path SIMD execution design method includes:

[0006] S1, the number of SIMD execution paths required by the vector operation unit is set by macro parameters;

[0007] S2, based on the number of SIMD execution paths in the macro parameters, select the SIMD execution paths that need to be enabled, and turn on the configurable switches of the vector emission queue and vector operation unit in the SIMD execution paths that need to be enabled, and turn off the configurable switches of the vector emission queue and vector operation unit in the SIMD execution paths that do not need to be enabled, so as to adjust the peak vector computing performance of the vector operation unit without changing the architecture parameters other than the SIMD execution paths.

[0008] Optionally, step S2 further includes creating a system status register in the processor's logic design to control the number of valid SIMD execution paths. During use, the processor selects a SIMD execution path from those configured to be enabled according to the configuration value written to the system status register, and sets the vector issue queue and vector operation unit in the selected SIMD execution path to be valid, while setting the vector issue queue and vector operation unit in the unselected SIMD execution path to be invalid, so as to balance the processor's power consumption and performance according to the processor's actual needs.

[0009] Optionally, when setting the number of SIMD execution paths required by the vector operation unit in step S1 through macro parameters, the number of SIMD execution paths required by the vector operation unit is 2 to 4.

[0010] Furthermore, the present invention also provides a vector operation unit obtained by employing the aforementioned configurable multi-path SIMD execution path design method, comprising:

[0011] The renaming unit REN is used to generate the operands Op required for vector operation instructions;

[0012] The multi-channel SIMD execution path includes multiple vector operation units. Each vector operation unit has a vector transmit queue (VXQ) at its input end. The multiple vector operation units are divided into two groups, each group containing one or two vector operation units. The two groups of vector operation units have their own bypasses within the group and a fully connected result bus between the groups.

[0013] The results register set is used to store the computation results of the multiple SIMD execution paths, including the integer register file GRF, the identity register file FLAGRF, the floating-point status register FPSR, and the vector register file VRF.

[0014] Optionally, the plurality of vector operation units are asymmetric structures that support partially or completely different vector operation instructions; the renaming unit REN includes a filtering module, which, after generating the operand Op required by the vector operation instruction, sends the operand Op required by the vector operation instruction to the vector emission queue VXQ corresponding to the vector operation unit that supports the vector operation instruction.

[0015] Optionally, the renaming unit REN includes an inter-group balancing module, which monitors the minimum number of free items in the vector launch queue VXQ within each group of vector operation units. After generating the operand Op required for a vector operation instruction, if both groups of vector operation units support the vector operation instruction, the operand Op required for the vector operation instruction is sent to the vector launch queue VXQ corresponding to the group of vector operation units that supports the vector operation instruction and has a smaller minimum number of free items.

[0016] Optionally, the multi-channel SIMD execution path is a four-channel SIMD execution path. The multiple vector operation units include vector operation units VX0 to VX3, each corresponding one-to-one with one of the four SIMD execution paths. Vector operation units VX0 and VX2 form a group of vector operation units, and vector operation units VX1 and VX3 form a group of vector operation units. The output terminals of vector operation units VX0 and VX1 are connected to the result bus RESX and the result bus RESY, and the output terminals of vector operation units VX2 and VX3 are connected to the result bus RESX1 and the result bus R. ESY1, and the vector operation unit VX0 is separately connected to the result bus RESP, which is used to output the calculation result of the operand Op with condition flag judgment. Each result bus is connected to the result register group and to the multi-cycle integer execution unit MXU or the memory access unit LSU. At the same time, the result bus and the result of the multi-cycle integer execution unit MXU or the memory access unit LSU are connected to the input terminal of each vector operation unit through a selector to serve as the multi-cycle operand Op of the vector operation unit. The control terminal of the selector is connected to a bypass module BYP to control the selection state of the selector when the multi-cycle operand Op is needed.

[0017] Optionally, the multi-path SIMD execution path is a three-path SIMD execution path. The multiple vector operation units include vector operation units VX0 to VX2, which correspond one-to-one with the three SIMD execution paths. Vector operation units VX0 and VX2 form a group of vector operation units, and vector operation unit VX1 forms another group of vector operation units. The output terminals of vector operation units VX0 and VX1 are connected to the result bus RESX and the result bus RESY, respectively. The output terminal of vector operation unit VX2 is connected to the result bus RESX1, and vector operation unit VX0... A separate result bus RESP is connected to the calculation result of the operand Op with condition flags. Each result bus is connected to the result register group and to the multi-cycle integer execution unit MXU or memory access unit LSU. At the same time, the results of the result bus, the multi-cycle integer execution unit MXU or the memory access unit LSU are connected to the input terminal of each vector operation unit through a selector to serve as the multi-cycle operand Op of the vector operation unit. The control terminal of the selector is connected to a bypass module BYP to control the selection state of the selector when the multi-cycle operand Op is needed.

[0018] Optionally, the multiple SIMD execution path is a two-way SIMD execution path. The multiple vector operation units include vector operation units VX0 to VX1, which correspond one-to-one with the two SIMD execution paths. Each vector operation unit VX0 and VX1 constitutes a set of vector operation units. The output terminals of vector operation units VX0 and VX1 are connected to the result bus RESX and the result bus RESY. Vector operation unit VX0 is separately connected to the result bus RESP, which is used to output the calculation result of the operand Op with condition flag judgment. Each result bus is connected to the result register group and to the multi-cycle integer execution unit MXU or the memory access unit LSU. At the same time, the results of the result bus and the multi-cycle integer execution unit MXU or the memory access unit LSU are connected to the input terminal of each vector operation unit through a selector to serve as the multi-cycle operand Op of the vector operation unit. The control terminal of the selector is connected to a bypass module BYP to control the selection state of the selector when the multi-cycle operand Op is required.

[0019] In addition, the present invention also provides a processor, including a processor body and a vector operation unit disposed in the processor body, wherein the vector operation unit is the vector operation unit described above.

[0020] Compared with the prior art, the present invention has the following main advantages:

[0021] 1. This invention provides a lightweight design scheme for improving the peak performance of vectors in high-performance CPUs, which can flexibly increase or decrease the number and types of VX, thereby improving resource utilization.

[0022] 2. This invention supports configuring multiple SIMD execution paths without changing the CPU front-end parameters during the design phase, thereby shortening the CPU design and development cycle and reducing the area overhead required for unit performance improvement.

[0023] 3. This invention supports configuring the number of SIMD execution paths after CPU tape-out to balance CPU performance and power consumption. Attached Figure Description

[0024] Figure 1 This is a flowchart of a method according to an embodiment of the present invention.

[0025] Figure 2 This is a diagram of the 4-way SIMD execution path structure configured in Embodiment 1 of the present invention.

[0026] Figure 3 This is a diagram of the 3-way SIMD execution path structure configured in Embodiment 2 of the present invention.

[0027] Figure 4 This is a structural diagram of the two-way SIMD execution path configured in Embodiment 3 of the present invention. Detailed Implementation

[0028] Example 1:

[0029] like Figure 1 As shown, the configurable multi-SIMD execution path design method in this embodiment includes:

[0030] S1, the number of SIMD execution paths required by the vector operation unit is set by macro parameters;

[0031] S2, based on the number of SIMD execution paths in the macro parameters, select the SIMD execution paths to be enabled, and turn on the configurable switches for the vector launch queue and vector operation units in the required SIMD execution paths, while turning off the configurable switches for the vector launch queue and vector operation units in the unenabled SIMD execution paths. This allows adjustment of the vector peak computation performance of the vector operation units without changing the architectural parameters other than the SIMD execution paths. The configurable switches for the vector launch queue and vector operation units in the SIMD execution paths are key to the macro parameter-based configurability of the configurable multi-SIMD execution path design method in this embodiment. By designing configurable switches in the vector launch queue and execution units, the addition or removal of vector execution units can be controlled by setting macro parameters during design, adjusting the vector peak computation performance without changing the architectural parameters other than the execution paths. The above steps S1 and S2 constitute the first layer of meaning of "configurable" in the configurable multi-SIMD execution path design method of this invention.

[0032] The second meaning of "configurable" in the configurable multi-SIMD execution path design method of this invention refers to the configurability during processor operation. During the use of the physical chip, the number of effective SIMD execution paths can be controlled through system registers. The number of SIMD channels can be selected according to actual needs, balancing power consumption and performance based on the processor's actual requirements. Specifically, step S2 of this embodiment further includes creating a system status register in the processor's logic design to control the number of effective SIMD execution paths. During use, the processor, based on the configuration value written to the system status register, further selects a SIMD execution path from those configured to be enabled according to macro parameters. The vector emission queue and vector operation unit in the selected SIMD execution path are set to valid, while those in the unselected SIMD execution paths are set to invalid. This achieves the goal of balancing processor power consumption and performance according to actual processor needs. In other words, by marking the vector emission queue and vector operation unit in the SIMD execution path as valid / invalid, the balance between power consumption and performance is achieved according to the processor's actual requirements. The activation / deactivation of the vector emission queue and vector operation unit in the SIMD execution path is achieved through the system status register. This system status register can be set in the processor as needed, and its status marking can be implemented by a separate component, or by the renaming unit REN in the vector operation unit or other components.

[0033] The upper limit of the number of SIMD execution paths required by the vector computation unit depends on the number of operands (Ops) that the renaming unit (REN) can emit. Therefore, the number of SIMD execution paths required by the vector computation unit can be determined according to actual needs. As an optional implementation, in step S1 of this embodiment, when setting the number of SIMD execution paths required by the vector computation unit through macro parameters, the number of SIMD execution paths required by the vector computation unit is 2 to 4. For example, if the REN can emit a maximum of 4 Ops, then the SIMD execution paths support configurable designs with 4 or fewer paths. Undoubtedly, in this embodiment, the number of SIMD execution paths required by the vector computation unit does not depend on the number of operands (Ops) that the renaming unit (REN) can emit, thus possessing broad applicability.

[0034] Furthermore, this embodiment also provides a vector operation unit obtained using the configurable multi-path SIMD execution path design method described above, including:

[0035] The renaming unit REN is used to generate the operands Op required for vector operation instructions;

[0036] The multi-channel SIMD execution path includes multiple vector operation units. Each vector operation unit has a vector transmit queue (VXQ) at its input end. The multiple vector operation units are divided into two groups, each group containing one or two vector operation units. The two groups of vector operation units have their own bypasses within the group and a fully connected result bus between the groups.

[0037] The results register set is used to store the computation results of the multiple SIMD execution paths, including the integer register file GRF, the identity register file FLAGRF, the floating-point status register FPSR, and the vector register file VRF.

[0038] To standardize terminology, the abbreviations VX in the following text refer to the vector operation unit, REN to the renaming unit, Op to the instruction operation, and VXQ to the vector operation unit's issue queue. Each vector operation unit's input corresponds to a vector issue queue VXQ, ensuring a one-to-one correspondence between the vector operation unit and the vector issue queue VXQ. After configuring the number of SIMD execution paths required by the vector operation unit to 4, the multiple SIMD execution paths simultaneously contain 4 vector operation units and 4 vector issue queues VXQ, with each vector issue queue VXQ corresponding to one vector operation unit.

[0039] The renaming unit (REN) is primarily used to rename registers during the renaming phase to generate the operands (Op) required for vector operation instructions. Operands in the REN are filtered and dispatched into the vector issue queue (VXQ). At this point, the dispatch port performs scheduling and balancing across the asymmetric vector pipelines, scheduling operands supported by the vector operation unit to the corresponding vector issue queue (VXQ) while ensuring that the issue queue does not become congested. The vector issue queue (VXQ) will determine whether the operands are ready and whether there are conflicts or other situations preventing issuance. When configured with 4 channels and all 4 operands can be issued, 4-issue can be achieved, enabling 4-channel vector pipelines and reaching the peak vector computation capability. Similarly, when configured with 2 channels, 2-issue can be achieved, with only 2 vector pipelines and half the peak vector computation capability. The operands in the vector issue queue (VXQ) then enter the vector operation unit, activating the corresponding computation unit for operation. In this process, operand Op obtains its source operand through a bypass network. Since the source operand may be the result of a previous operation on operand Op, fast bypassing is required for forwarding to improve computational efficiency. With four vector operation units, two can be grouped together, and fast bypassing within each group is designed to implement forwarding functionality. Finally, the calculation results of each vector operation unit are written to the result bus. The result bus adopts a fully interconnected structure; for example, when configuring four vector operation units, each result bus can forward to any vector operation unit, ensuring computational efficiency. The flag register file FLAGRF and the floating-point status register FPSR are used to store intermediate results, including the flag and floating-point status. The final calculation result is written to register files, namely the vector register file VRF and the integer register file GRF.

[0040] As an optional implementation, in this embodiment, the multiple vector operation units have asymmetric structures that support partially or completely different vector operation instructions. The renaming unit (REN) includes a filtering module, which, after generating the operand Op required for the vector operation instruction, sends the operand Op to the vector dispatch queue VXQ corresponding to the vector operation unit that supports the vector operation instruction. For example, when the multi-path SIMD execution path includes four vector operation units, the computation instructions supported by the four vector operation units can be different. For instance, only vector operation unit VX1 supports memory access instructions, only vector operation unit VX0 supports division instructions, and only vector operation units VX0 and VX1 support vector move instructions. The filtering module controls the destination of the execution dispatch by the renaming unit (REN). Since the multiple vector operation units have asymmetric structures that support partially or completely different vector operation instructions, this mechanism can ensure that the operand Op is accurately sent to the vector operation unit that supports the instruction.

[0041] As an optional implementation, the renaming unit REN in this embodiment includes an inter-group load balancing module, which monitors the minimum number of free items in the vector transmission queue VXQ within each group of vector operation units. After generating the operand Op required for a vector operation instruction, if both groups of vector operation units support the vector operation instruction, the operand Op required for the vector operation instruction is sent to the vector transmission queue VXQ corresponding to the group of vector operation units that supports the vector operation instruction and has a smaller minimum number of free items. This achieves inter-group load balancing of vector operation units and prevents the difference in the number of items in the two groups of vector transmission queue VXQ from becoming too large or from causing congestion.

[0042] like Figure 2 As shown, in this embodiment, the multi-channel SIMD execution path is a four-channel SIMD execution path. The multiple vector operation units include vector operation units VX0 to VX3, which correspond one-to-one with the four SIMD execution paths. Vector operation units VX0 and VX2 form a group of vector operation units, and vector operation units VX1 and VX3 form a group of vector operation units. The output terminals of vector operation units VX0 and VX1 are connected to the result bus RESX and the result bus RESY, and the output terminals of vector operation units VX2 and VX3 are connected to the result bus RESX1 and the result bus RESY. The vector operation unit VX0 is connected to a separate result bus RESP for outputting the calculation result of the operand Op with condition flags. Each result bus is connected to the result register group and to the multi-cycle integer execution unit MXU or the memory access unit LSU. At the same time, the results of the result bus and the multi-cycle integer execution unit MXU or the memory access unit LSU are connected to the input terminal of each vector operation unit through a selector to serve as the multi-cycle operand Op of the vector operation unit. The control terminal of the selector is connected to a bypass module BYP to control the selection state of the selector when the multi-cycle operand Op is needed. Figure 2 In the diagram, the solid black line represents the execution path, the stack is marked with a black box on the right, and the stack intervals are represented by black dashed lines. RD represents the read stack for ready bits. I0–I3 represent the issue stack for steps 0–3, V1 represents the execution stack, W0–W2 represent the write-back stack for steps 0–2, and W2 represents the state after step W1. According to… Figure 2It can be seen that the renaming unit REN runs on the read stack RD, the vector emit queue VXQ runs on the emit stacks I0 to I3, and the vector operation units VX0 to VX3 run on the execution stack V1 and the 0th clock cycle W0 of the write-back stack. The result bus performs intra-group and inter-group bypassing of results on the execution stack V1 and the 1st clock cycle W1 of the write-back stack. On the 2nd clock cycle W2 of the write-back stack, the result register group is written, including the integer register file GRF, the flag register file FLAGRF, the floating-point status register FPSR, and the vector register file VRF. After configuration, the four SIMD execution paths receive the four operands Op assigned by the renaming unit REN on the read stack RD. After the equalization and filtering mechanism, the operands Op will be emitted by the subsequent vector emit queue VXQ to the corresponding vector operation units VX. Ideally, each vector emitter queue (VXQ) receives one operand Op and emits it to the subsequent vector arithmetic unit (VX). If the four operand Ops assigned by the renaming unit (REN) have special functional limitations, the filtering mechanism will bypass the operand Ops of vector arithmetic unit (VX2) or vector arithmetic unit (VX3) to vector arithmetic unit (VX0) or vector arithmetic unit (VX1). VX is responsible for instruction computation, and the results are written to the result buses RESX, RESY, RESX1, and RESY1. The four result buses are grouped: RESX and RESY form one group, and RESX1 and RESY1 form another. The two groups of result buses are fully connected, meaning that data from each result bus can be bypassed to four different vector arithmetic units to ensure computational efficiency. The computation results from the vector arithmetic units are ultimately written to the result register set, specifically the vector register file (VRF) and the integer register file (GRF), and the flag register file (FLAGRF) and floating-point status register (FPSR) are updated. It is important to note that the result bus RESP contains the calculation result of the operand Op with conditional flags, and the result bus RESP channel is unique to the vector operation unit VX0. For example... Figure 2 The Fast BYP GROUP indicates the instructions executed by the vector operation unit, including two vector calculations: VX0&VX1 and VX2&VX3.

[0043] In this embodiment, the original SIMD execution path contains a total of four SIMD execution paths, therefore, to obtain Figure 2 When the four SIMD execution paths are shown, the number of SIMD execution paths required by the vector operation unit is set to 4 through macro parameter settings. This means that the configurable switches of the vector emission queue and vector operation unit in all SIMD execution paths are turned on. This allows the vector peak computation performance of the vector operation unit to be adjusted without changing the architecture parameters other than the SIMD execution paths, so as to achieve the maximum vector peak computation performance.

[0044] In summary, addressing the issue that the main method for improving single-core performance of current general-purpose processors is to broaden architectural parameters, which incurs significant overhead, this embodiment proposes a configurable multi-path SIMD execution design method. This method supports flexible configuration of multiple SIMD paths during the logic design phase and in the actual chip, effectively improving CPU floating-point performance and balancing performance and power consumption. Compared to methods that comprehensively broaden and upgrade CPU architectural parameters, the method in this embodiment can significantly reduce design cycle and hardware area overhead, providing crucial support for agile design of high-performance general-purpose processors.

[0045] Furthermore, this embodiment also provides a processor, including a processor body and a vector operation unit disposed in the processor body, wherein the vector operation unit is the aforementioned vector operation unit. It should be noted that the processor can be a microprocessor or other processor chips that support vector operations, such as a GPU, an accelerator chip based on an FPGA or other dedicated circuits, etc., and its specific form should not constitute a limitation on the processor.

[0046] Example 2:

[0047] This embodiment is basically the same as Embodiment 1, with the main difference being: Figure 3 As shown, in this embodiment, the multi-SIMD execution path is a three-SIMD execution path. The multiple vector operation units include vector operation units VX0 to VX2, which correspond one-to-one with the three SIMD execution paths. Vector operation units VX0 and VX2 form a group of vector operation units, and vector operation unit VX1 forms another group of vector operation units. The output terminals of vector operation units VX0 and VX1 are connected to the result bus RESX and the result bus RESY, respectively. The output terminal of vector operation unit VX2 is connected to the result bus RESX1, and the vector operation unit VX... A separate result bus RESP is connected to the result of the operand Op, which is used to output the calculation result with conditional flags. Each result bus is connected to the result register group and to the multi-cycle integer execution unit MXU or memory access unit LSU. Simultaneously, the results of the result buses and the multi-cycle integer execution unit MXU or memory access unit LSU are connected to the input terminals of each vector operation unit via a selector to serve as the multi-cycle operand Op for the vector operation unit. The control terminal of the selector is connected to a bypass module BYP to control the selection state of the selector when a multi-cycle operand Op is needed. In this embodiment, the original SIMD execution path contains four SIMD execution paths; therefore, to obtain... Figure 3When the four SIMD execution paths are shown, the number of SIMD execution paths required for the vector computation unit is set to 3 via macro parameter settings. This means selecting three SIMD execution paths, turning on the configurable switches for the vector emission queue and vector computation unit in the three selected paths, and turning off the configurable switches for the vector emission queue and vector computation unit in the remaining SIMD execution path. When selecting three SIMD execution paths, the vector computation units VX0 to VX2 selected above are merely examples; any three of the four vector computation units can be used in combination. The selected operand Op will enter the three vector computation units via the three vector emission queues VXQ for execution. The calculation results are written to the three result buses, then to the register file, and the corresponding status registers are updated. This allows adjustment of the vector peak computation performance of the vector computation unit without changing the architectural parameters other than the SIMD execution paths.

[0048] Furthermore, this embodiment also provides a processor, including a processor body and a vector operation unit disposed in the processor body, wherein the vector operation unit is the aforementioned vector operation unit. It should be noted that the processor can be a microprocessor or other processor chips that support vector operations, such as a GPU, an accelerator chip based on an FPGA or other dedicated circuits, etc., and its specific form should not constitute a limitation on the processor.

[0049] Example 3:

[0050] This embodiment is basically the same as Embodiment 1, with the main difference being: Figure 4 As shown, in this embodiment, the multi-channel SIMD execution path is a two-channel SIMD execution path. The multiple vector operation units include vector operation units VX0 to VX1, which correspond one-to-one with the two SIMD execution paths. Each vector operation unit VX0 and VX1 constitutes a set of vector operation units. The output terminals of vector operation units VX0 and VX1 are connected to the result bus RESX and the result bus RESY, respectively. Vector operation unit VX0 is separately connected to the result bus RESP, which is used to output the calculation result of the operand Op with conditional flags. Each result bus is connected to the result register set and to the multi-cycle integer execution unit MXU or the memory access unit LSU. Simultaneously, the results of the result buses and the multi-cycle integer execution unit MXU or the memory access unit LSU are connected to the input terminals of each vector operation unit via a selector to serve as the multi-cycle operand Op of the vector operation unit. The control terminal of the selector is connected to a bypass module BYP to control the selection state of the selector when the multi-cycle operand Op is needed. In this embodiment, the original SIMD execution path contains four SIMD execution paths; therefore, to obtain... Figure 4When the four SIMD execution paths are shown, the number of SIMD execution paths required by the vector operation unit is set to 2 via macro parameter settings. This means selecting two SIMD execution paths, turning on the configurable switches for the vector emission queues and vector operation units in the selected two SIMD execution paths, and turning off the configurable switches for the vector emission queues and vector operation units in the remaining two SIMD execution paths. When selecting two SIMD execution paths, the vector operation units VX0 to VX1 selected above are merely examples; any two of the four vector operation units can be used in combination. The selected operand Op will enter the two vector operation units via the two vector emission queues VXQ for execution. The calculation results are written to the two result buses, then to the register file, and the corresponding status registers are updated. This allows adjustment of the peak vector computation performance of the vector operation unit without changing the architectural parameters other than the SIMD execution paths.

[0051] Furthermore, this embodiment also provides a processor, including a processor body and a vector operation unit disposed in the processor body, wherein the vector operation unit is the aforementioned vector operation unit. It should be noted that the processor can be a microprocessor or other processor chips that support vector operations, such as a GPU, an accelerator chip based on an FPGA or other dedicated circuits, etc., and its specific form should not constitute a limitation on the processor.

[0052] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A vector operation unit, characterized by, The application comprises: a renaming unit REN for generating an operand Op required by a vector operation instruction; a multi-path SIMD execution path corresponding to a plurality of vector operation components, each vector operation component having a corresponding vector emission queue VXQ at its input end, and the plurality of vector operation components being divided into two groups, each group comprising one or two vector operation components, and the two groups of vector operation components having their own bypasses and a full-connection result bus between the groups; a result register group for storing the calculation results of the multi-path SIMD execution path, comprising an integer register file GRF, an identification register file FLAGRF, a floating point state register FPSR and a vector register file VRF; the design method of the multi-path SIMD execution path comprises: S1, setting the number of SIMD execution paths required by the vector operation unit through macro parameters; S2, selecting the SIMD execution paths to be enabled according to the number of SIMD execution paths in the macro parameters, and opening the configurable switches of the vector emission queue and the vector operation unit in the SIMD execution paths to be enabled and closing the configurable switches of the vector emission queue and the vector operation unit in the SIMD execution paths not to be enabled, so as to adjust the vector peak calculation performance of the vector operation unit under the premise that the architecture parameters except the SIMD execution path remain unchanged; creating a system state register for controlling the number of effective SIMD execution paths in the logical design of the processor, so that the processor, in the use process, selects the SIMD execution path according to the configuration value written in the system state register, and further selects the SIMD execution path according to the configuration value in the SIMD execution path configured to be enabled according to the macro parameters, and sets the vector emission queue and the vector operation unit in the selected SIMD execution path to be effective and sets the vector emission queue and the vector operation unit in the unselected SIMD execution path to be ineffective, so as to balance the power consumption and performance of the processor according to the actual demand of the processor.

2. The vector operation unit of claim 1, wherein, In step S1, the number of SIMD execution paths required by the vector operation unit is set through macro parameters, and the number of SIMD execution paths required by the vector operation unit is 2-4.

3. The vector operation unit of claim 1, wherein, The plurality of vector operation components are asymmetric structures supporting part or all of different vector operation instructions; the renaming unit REN comprises a screening module for sending the operand Op required by the vector operation instruction into the vector emission queue VXQ corresponding to the vector operation component supporting the vector operation instruction after generating the operand Op required by the vector operation instruction.

4. The vector arithmetic unit of claim 3, wherein, The renaming unit REN comprises an inter-group balancing module for monitoring the minimum idle item number of the vector emission queue VXQ in each group of vector operation components, and sending the operand Op required by the vector operation instruction into the vector emission queue VXQ corresponding to the group of vector operation components supporting the vector operation instruction and having a smaller minimum idle item number after generating the operand Op required by the vector operation instruction.

5. The vector arithmetic unit according to any one of claims 1 to 4, characterized in that The multi-way SIMD execution lane is a four-way SIMD execution lane, the plurality of vector operation components include vector operation components VX0-VX3 corresponding to the four-way SIMD execution lane, vector operation component VX0 and vector operation component VX2 form a group of vector operation components, vector operation component VX1 and vector operation component VX3 form a group of vector operation components, the output ends of vector operation component VX0 and vector operation component VX1 are connected to result bus RESX and result bus RESY, the output ends of vector operation component VX2 and vector operation component VX3 are connected to result bus RESX1 and result bus RESY1, and vector operation component VX0 is separately connected to result bus RESP for outputting the calculation result of the operand Op with a conditional flag judgment, each result bus is connected to a result register group and a multi-cycle integer execution unit MXU or a memory access unit LSU, and the results of the result bus, the multi-cycle integer execution unit MXU or the memory access unit LSU are connected to the input ends of each vector operation component through a selector as a multi-cycle operand Op of the vector operation component, and the control end of the selector is connected to a bypass module BYP for controlling the selection state of the selector when a multi-cycle operand Op is needed.

6. The vector arithmetic unit according to any one of claims 1 to 4, characterized in that The multi-way SIMD execution lane is a three-way SIMD execution lane, the plurality of vector operation components include vector operation components VX0-VX2 corresponding to the three-way SIMD execution lane, vector operation component VX0 and vector operation component VX2 form a group of vector operation components, vector operation component VX1 is a group of vector operation components, the output ends of vector operation component VX0 and vector operation component VX1 are connected to result bus RESX and result bus RESY, the output end of vector operation component VX2 is connected to result bus RESX1, and vector operation component VX0 is separately connected to result bus RESP for outputting the calculation result of the operand Op with a conditional flag judgment, each result bus is connected to a result register group and a multi-cycle integer execution unit MXU or a memory access unit LSU, and the results of the result bus, the multi-cycle integer execution unit MXU or the memory access unit LSU are connected to the input ends of each vector operation component through a selector as a multi-cycle operand Op of the vector operation component, and the control end of the selector is connected to a bypass module BYP for controlling the selection state of the selector when a multi-cycle operand Op is needed.

7. The vector arithmetic unit according to any one of claims 1 to 4, characterized in that The multiple SIMD execution lanes are two-lane SIMD execution lanes, and the multiple vector operation components include vector operation components VX0-VX1 corresponding to the two-lane SIMD execution lanes respectively, the vector operation components VX0 and VX1 form a group of vector operation components respectively, the output ends of the vector operation components VX0 and VX1 are connected to a result bus RESX and a result bus RESY, and the vector operation component VX0 is connected to a result bus RESP for outputting the calculation result of the operand Op with a conditional flag judgment, each result bus is connected to a result register group and a multi-cycle integer execution unit MXU or a memory access unit LSU, and the results of the result bus, the multi-cycle integer execution unit MXU or the memory access unit LSU are connected to the input ends of each vector operation component through a selector as the multi-cycle operands Op of the vector operation components, and the control end of the selector is connected to a bypass module BYP for controlling the selection state of the selector when the multi-cycle operand Op is needed.

8. A processor comprising a processor body and a vector operation unit arranged in the processor body, and the vector operation unit is the vector operation unit according to any one of claims 1-7.

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