Voltage conversion circuit, display device, target clock signal, and near-end scan signal

Abstract

The application discloses a voltage conversion circuit, a display device, a target clock signal and a near-end scanning signal. The voltage conversion circuit comprises a voltage conversion module and a compensation module. The voltage conversion module is used for outputting a second clock signal according to a first clock signal, a first power signal and a second power signal, the second clock signal has the same waveform as the first clock signal and different voltage amplitudes; and the compensation module is used for outputting a target clock signal according to the first clock signal, an adjustment signal, the second clock signal, a third power signal and a fourth power signal, each rising edge of the target clock signal comprises two sub-rising edges, and each falling edge of the target clock signal comprises two sub-falling edges. The application can compensate for the loss of high-frequency components of the target clock signal in transmission, correct waveform distortion of the target clock signal generated in the transmission process, improve the charging rate and improve the display effect.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a voltage conversion circuit, a display device, a target clock signal and a near-end scanning signal. BACKGROUND

[0002] In a display panel, a PMIC (Power Management IC) usually generates a clock signal, and a gate driving chip or a GOA (Gate on Array) generates a scanning signal for driving a scanning line in the display panel based on the clock signal.

[0003] With the development of display technology, in a large-size high-resolution display panel, the problem of low charging efficiency of the display panel has attracted widespread attention. However, the clock signal output by the PMIC needs to be transmitted to the corresponding gate driving chip or GOA circuit through WOA (Wire On Array) wiring, and due to the RC delay (resistor-capacitor delay) of the wiring, the waveform of the clock signal will be distorted due to loss, and the farther away from the PMIC the gate driving chip or GOA circuit receives the clock signal, the more serious the waveform distortion of the clock signal, and the worse the charging, thereby affecting the display effect of the display panel. SUMMARY

[0004] The present application provides a voltage conversion circuit, a display device, a target clock signal and a near-end scanning signal to solve the technical problem that the clock signal is severely distorted in the transmission process in the prior art, resulting in insufficient charging and affecting the display effect.

[0005] The present application provides a voltage conversion circuit, which comprises:

[0006] A voltage conversion module has a first control end, a first input end, a second input end and a first output end. The first control end is connected to a first clock signal, the first input end is connected to a first power signal, and the second input end is connected to a second power signal. The voltage conversion module is used to output a second clock signal at the first output end according to the first clock signal, the first power signal and the second power signal. The second clock signal has the same waveform as the first clock signal, but different voltage amplitude.

[0007] The compensation module has a second control terminal, a third input terminal, a fourth input terminal, a fifth input terminal, a sixth input terminal and a second output terminal, the second control terminal is connected to the first clock signal, the third input terminal is connected to an adjustment signal, the fourth input terminal is connected to the first output terminal, the fifth input terminal is connected to a third power supply signal, the sixth input terminal is connected to a fourth power supply signal, and the compensation module is used for outputting a target clock signal at the second output terminal according to the first clock signal, the adjustment signal, a second clock signal, the third power supply signal and the fourth power supply signal, each rising edge of the target clock signal includes two sub-rising edges, each falling edge of the target clock signal includes two sub-falling edges, a first preset time is arranged between the two sub-rising edges, and a second preset time is arranged between the two sub-falling edges.

[0008] Optionally, in some embodiments of the present application, the voltage conversion module comprises a first transistor and a second transistor; a gate of the first transistor and a gate of the second transistor are connected to the first control terminal; a source of the first transistor is connected to the first input terminal; a source of the second transistor is connected to the second input terminal; a drain of the first transistor and a drain of the second transistor are connected to the first output terminal.

[0009] Optionally, in some embodiments of the present application, the first transistor is one of an N-type transistor and a P-type transistor, and the second transistor is the other of the N-type transistor and the P-type transistor.

[0010] Optionally, in some embodiments of the present application, the compensation module comprises a first compensation unit, and the first compensation unit comprises a third transistor, a fourth transistor, a fifth transistor, a first resistor and a first diode.

[0011] Optionally, in some embodiments of the present application, the third transistor is one of an N-type transistor and a P-type transistor, and the second transistor is the other of the N-type transistor and the P-type transistor.

[0012] Optionally, in some embodiments of the present application, the compensation module comprises a first compensation unit, and the first compensation unit comprises a third transistor, a fourth transistor and a fifth transistor.

[0013] The gate of the third transistor is connected to the first clock signal, the source of the third transistor is connected to the third input terminal, the drain of the third transistor, the gate of the fourth transistor and the gate of the fifth transistor are connected together, the source of the fourth transistor is connected to the fourth input terminal, the source of the fifth transistor is connected to the fifth input terminal, and the drain of the fourth transistor and the drain of the fifth transistor are both connected to the second output terminal.

[0014] Optionally, in some embodiments of the present application, the voltage value of the first power signal is greater than the voltage value of the third power signal, the fourth transistor is an N-type transistor, and the fifth transistor is a P-type transistor.

[0015] Or the voltage value of the first power signal is less than the voltage value of the third power signal, the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.

[0016] Optionally, in some embodiments of the present application, the compensation module comprises a second compensation unit, and the second compensation unit comprises a sixth transistor, a seventh transistor, an eighth transistor, a second resistor and a second diode.

[0017] The gate of the sixth transistor is connected to the first clock signal, the source of the sixth transistor is connected to the adjustment signal, the drain of the sixth transistor, the gate of the seventh transistor and the gate of the eighth transistor are connected together, the source of the seventh transistor and the source of the eighth transistor are both connected to the first output terminal, the drain of the seventh transistor is connected to the second output terminal, the drain of the eighth transistor and one end of the second resistor are connected together, the other end of the second resistor and the cathode of the second diode are connected to the second output terminal, and the anode of the second diode is connected to the fourth power signal.

[0018] Optionally, in some embodiments of the present application, the compensation module comprises a second compensation unit, and the second compensation unit comprises a sixth transistor, a seventh transistor and an eighth transistor.

[0019] The gate of the sixth transistor is connected to the first clock signal, the source of the sixth transistor is connected to the adjustment signal, the drain of the sixth transistor, the gate of the seventh transistor and the gate of the eighth transistor are connected together, the source of the seventh transistor is connected to the first output terminal, the source of the eighth transistor is connected to the fourth power signal, and the drain of the seventh transistor and the drain of the eighth transistor are both connected to the second output terminal.

[0020] Optionally, in some embodiments of the present application, the voltage value of the second power supply signal is greater than the voltage value of the fourth power supply signal, the seventh transistor is an N-type transistor, and the eighth transistor is a P-type transistor.

[0021] Or the voltage value of the second power supply signal is less than the voltage value of the fourth power supply signal, the seventh transistor is a P-type transistor, and the eighth transistor is an N-type transistor.

[0022] Optionally, in some embodiments of the present application, the first clock signal comprises a first high level and a first low level alternately appearing, the second clock signal comprises a second high level and a second low level alternately appearing, the second high level is greater than the first high level, and the second low level is less than the first low level.

[0023] Optionally, in some embodiments of the present application, the adjustment signal comprises a third high level, a third low level, a fourth high level and a fourth low level alternately appearing; the third high level and the third low level have a duration equal to the duration of the second high level, and the fourth high level and the fourth low level have a duration equal to the duration of the second low level.

[0024] The present application also provides a display device comprising a display panel and a voltage conversion circuit, wherein the voltage conversion circuit is any one of the voltage conversion circuits described above, and the voltage conversion circuit outputs the target clock signal to the display panel.

[0025] Optionally, in some embodiments of the present application, the display panel comprises a plurality of scan lines and a plurality of sub-pixels arranged in an array, each of the sub-pixels comprises a first side and a second side arranged adjacently, the length of the first side is greater than the length of the second side, and the extension direction of the scan line is parallel to the first side.

[0026] The present application also provides a target clock signal comprising a plurality of continuous clock periods, each of the clock periods comprises a rising edge and a falling edge, the rising edge comprises two sub-rising edges, the falling edge comprises two sub-falling edges, the first preset time is between the two sub-rising edges, and the second preset time is between the two sub-falling edges.

[0027] The application also provides a near-end scanning signal, which comprises a continuous first rising time period, a second rising time period, a first falling time period and a second falling time period, in the first rising time period, the voltage value of the near-end scanning signal gradually increases, in the second rising time period, the voltage value of the near-end scanning signal first decreases and then increases; in the first falling time period, the voltage value of the near-end scanning signal gradually decreases, in the second falling time period, the voltage value of the near-end scanning signal gradually increases to a fixed value.

[0028] The application provides a voltage conversion circuit, which comprises a voltage conversion module and a compensation module. The voltage conversion module is used for outputting a second clock signal according to a first clock signal, a first power supply signal and a second power supply signal, the second clock signal has the same waveform as the first clock signal and different voltage amplitude; the compensation module is used for outputting a target clock signal according to the first clock signal, an adjusting signal, the second clock signal, a third power supply signal and a fourth power supply signal, each rising edge of the target clock signal comprises two sub-rising edges, each falling edge of the target clock signal comprises two sub-falling edges, and the interval between the two sub-rising edges is a first preset time, and the interval between the two sub-falling edges is a second preset time. By adding the compensation module in the voltage conversion circuit, the voltage at the rising edge and the falling edge of the second clock signal is adjusted, so that each rising edge of the target clock signal comprises two sub-rising edges, each falling edge of the target clock signal comprises two sub-falling edges, the amplitude of the high-frequency component of the target clock signal in the frequency domain is improved, the loss of the high-frequency component in the transmission is compensated, the waveform distortion of the target clock signal after the transmission loss is corrected, the charging rate is improved, and the display effect is improved. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0030] Figure 1 is a structural schematic diagram of the voltage conversion circuit provided by the application;

[0031] Figure 2 is a transmission schematic diagram of the target clock signal in a display device provided by the application;

[0032] Figure 3 is a simulation waveform of the target clock signal at the near end provided by the application;

[0033] Figure 4is a simulation waveform of the target clock signal at a far end provided by the present application;

[0034] Figure 5 is a first circuit schematic diagram of the voltage conversion circuit provided by the present application;

[0035] Figure 6 is Figure 5 is a signal timing diagram of the voltage conversion circuit shown in

[0036] Figure 7 is a second circuit schematic diagram of the voltage conversion circuit provided by the present application;

[0037] Figure 8 is a third circuit schematic diagram of the voltage conversion circuit provided by the present application;

[0038] Figure 9 is Figure 8 is a signal timing diagram of the voltage conversion circuit shown in

[0039] Figure 10 is a structural schematic diagram of the display device provided by the present application. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0041] In the description of the present application, it should be understood that the terms "first" and "second" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more of the features, and therefore cannot be understood as a limitation on the present application. In addition, it should be noted that, unless otherwise specified and limited, the terms "connected", "connected" should be understood in a broad sense, for example, it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or the communication between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0042] The present application provides a voltage conversion circuit, a display device, a target clock signal and a near-end scanning signal, which will be described in detail below. It should be noted that the description order of the following embodiments is not limited as the preferred order of the embodiments of the present application.

[0043] Please refer toFigure 1 , Figure 1 is a structural schematic diagram of the voltage conversion circuit provided by the present application. In the embodiment of the present application, the voltage conversion circuit 100 comprises a voltage conversion module 10 and a compensation module 20.

[0044] The voltage conversion module 10 has a first control end 10a, a first input end 10b, a second input end 10c and a first output end 10d. The first control end 10a is connected to the first clock signal CK_in. The first input end 10b is connected to the first power supply signal VGH1. The second input end 10c is connected to the second power supply signal VGL1. The voltage conversion module 10 is configured to output the second clock signal CKA at the first output end 10d according to the first clock signal CK_in, the first power supply signal VGH1 and the second power supply signal VGL1. The second clock signal CKA has the same waveform as the first clock signal CK_in, but different voltage amplitude, thereby realizing the level conversion of the first clock signal CK_in. It should be noted that the same waveform mentioned herein not only means the same type of signal, i.e. the same sine wave, square wave, rectangular wave, triangular wave, sawtooth wave, etc., but also means the same frequency of the signal.

[0045] The compensation module 20 has a second control end 20a, a third input end 20b, a fourth input end 20c, a fifth input end 20d, a sixth input end 20e and a second output end 20f. The second control end 20a is connected to the first clock signal CK_in. The third input end 20b is connected to the adjustment signal K. The fourth input end 20c is connected to the first output end 10d. The fifth input end 20d is connected to the third power supply signal VGH. The sixth input end 20e is connected to the fourth power supply signal VGL. The compensation module 20 is configured to adjust the voltage at the rising edge and the falling edge of the second clock signal CKA according to the first clock signal CK_in, the adjustment signal K, the third power supply signal VGH and the fourth power supply signal VGL, so as to output the target clock signal CK_out at the second output end 20f. Each rising edge of the target clock signal CK_out comprises two sub-rising edges, and each falling edge of the target clock signal CK_out comprises two sub-falling edges.

[0046] The interval between the two sub-rising edges is a first preset time, i.e. the two sub-rising edges are not directly continuous. The interval between the two sub-falling edges is a second preset time, i.e. the two sub-falling edges are not directly continuous.

[0047] Please refer to Figure 2 , Figure 2is a transmission schematic diagram of the target clock signal provided by the present application in a display device. In the related art, the display device includes a display panel 200 and a power management integrated circuit 300. The power management integrated circuit 300 outputs a second clock signal CKA. The second clock signal CKA is transmitted from the power management integrated circuit 300 to a GOA circuit (not shown in the figure) in the display panel 200.

[0048] It can be understood that the GOA circuit includes a plurality of cascaded GOA units, and each GOA unit outputs a corresponding scan signal according to the received target clock signal CK_out. The plurality of cascaded GOA units are arranged at least on one side of the display panel 200. Along the arrow direction in Figure 2 The target clock signal CK_out is transmitted from the power management integrated circuit 300 to each GOA unit in the direction of the arrow. Due to the RC delay of the signal transmission trace, the loss of the target clock signal CK_out received by the GOA unit at the far end is greater than that of the GOA unit at the near end, and the waveform distortion is more serious. Since the waveform of the scan signal output by the GOA unit is basically consistent with the waveform of the received target clock signal CK_out, the waveform of the scan signal will also be distorted, thereby causing insufficient charging and affecting the picture display effect of the display panel 200.

[0049] In addition, since the high and low of the signal frequency is mainly determined by the speed of the signal level change, the high frequency component of the signal mainly appears at the rising edge and the falling edge of the signal. The signal transmission trace exhibits low-pass filtering characteristics, and the high frequency component of the signal attenuates greatly during transmission, and the low frequency component attenuates less. Therefore, the waveform distortion at the rising edge and the falling edge of the target clock signal CK_out is most obvious. In this regard, the embodiment of the present application adds a compensation module 20 in the voltage conversion circuit 100 to adjust the voltage at the rising edge and the falling edge of the second clock signal CKA, so that each rising edge of the target clock signal CK_out includes two sub-rising edges, and each falling edge of the target clock signal CK_out includes two sub-falling edges. The amplitude of the high frequency component of the target clock signal CK_out is improved in the frequency domain, thereby compensating for the loss of the high frequency component of the target clock signal CK_out during transmission, improving the charging rate, and improving the display effect.

[0050] Specifically, please refer to Figures 2-4 , Figure 3 is a simulation waveform of the target clock signal at the near end provided by the present application; Figure 4 is a simulation waveform of the target clock signal at the far end provided by the present application.

[0051] As Figure 3As shown, curve A represents the waveform of the uncompensated target clock signal; curve B represents the waveform of the uncompensated target clock signal at the near end; curve C represents the waveform of the compensated target clock signal CK_out; and curve D represents the waveform of the compensated target clock signal CK_out at the near end. It can be seen that each rising edge of the compensated target clock signal CK_out has two sub-rising edges, namely the first sub-rising edge t3 and the second sub-rising edge t4; each falling edge has two sub-falling edges, namely the first sub-falling edge t1 and the second sub-falling edge t2. Therefore, after transmission loss, the waveforms of the target clock signal CK_out transmitted to the near end are improved at both the rising and falling edges, with shorter rise and fall times, effectively improving the charging rate.

[0052] like Figure 4 As shown, curve A represents the waveform of the uncompensated target clock signal; curve E represents the waveform of the uncompensated target clock signal at the far end; curve C represents the waveform of the compensated target clock signal CK_out; and curve F represents the waveform of the compensated target clock signal CK_out at the near end. Similarly, after compensating for the voltage at the rising and falling edges of the target clock signal CK_out, the waveforms at the rising and falling edges of the target clock signal CK_out transmitted to the far end are improved, with shorter rise and fall times, effectively improving the charging rate.

[0053] In this embodiment, the second clock signal CKA and the first clock signal CK_in have the same waveform but different voltage values. Both the first clock signal CK_in and the second clock signal CKA are signals that alternate between high and low levels. The voltage amplitude relationship between the first clock signal CK_in and the second clock signal CKA can be set according to requirements.

[0054] In this embodiment, the first power signal VGH1, the second power signal VGL1, the third power signal VGH, and the fourth power signal VGL are all DC signals. The voltage values ​​of the first power signal VGH1, the second power signal VGL1, the third power signal VGH, and the fourth power signal VGL can be set according to the specific circuit structure and operating timing of the compensation module 20, which will be described in detail in the following embodiments.

[0055] Please see Figure 1 , Figure 5 as well as Figure 6 , Figure 5 This is a first circuit diagram of the voltage conversion circuit provided in this application; Figure 6 yes Figure 5 The signal timing diagram of the voltage conversion circuit is shown. In some embodiments of this application, the voltage conversion module 10 includes a first transistor T1 and a second transistor T2.

[0056] The gate of the first transistor T1 and the gate of the second transistor T2 are connected to the first control end 10a, that is, the first clock signal CK_in is input. The source of the first transistor T1 is connected to the first input end 10b, that is, the first power signal VGH1 is input. The source of the second transistor T2 is connected to the second input end 10c, that is, the second power signal VGL1 is input. The drain of the first transistor T1 and the drain of the second transistor T2 are connected to the first output end 10d.

[0057] The first transistor T1 is one of an N-type transistor and a P-type transistor. The second transistor T2 is the other of the N-type transistor and the P-type transistor.

[0058] The first clock signal CK_in is a signal in which a first high level a2 and a first low level a1 appear alternately. The second clock signal CKA is a signal in which a second high level A2 and a second low level A1 appear alternately. The first high level a2 is smaller than the second high level A2. The first low level a1 is greater than the second low level A1. Thus, the voltage amplitude of the first clock signal CK_in is increased. Of course, the present application is not limited thereto.

[0059] For example, when the first transistor T1 is an N-type transistor and the second transistor T2 is a P-type transistor, the voltage value of the first power signal VGH1 is greater than the voltage value of the second power signal VGL1. Under the control of the first clock signal CK_in, the first transistor T1 and the second transistor T2 are opened alternately to alternately output the first power signal VGH1 and the second power signal VGL1. At this time, the voltage value of the first power signal VGH1 is equal to the second high level A2, and the voltage value of the second power signal VGL1 is equal to the second low level A1.

[0060] For example, when the first transistor T1 is an N-type transistor and the second transistor T2 is a P-type transistor, the voltage value of the first power signal VGH1 is greater than the voltage value of the second power signal VGL1. Under the control of the first clock signal CK_in, the first transistor T1 and the second transistor T2 are opened alternately to alternately output the first power signal VGH1 and the second power signal VGL1. At this time, the voltage value of the first power signal VGH1 is equal to the second high level A2, and the voltage value of the second power signal VGL1 is equal to the second low level A1.

[0061] The following embodiments of the present application are described by taking the first transistor T1 as an N-type transistor, the second transistor T2 as a P-type transistor, and the voltage value of the first power signal VGH1 being greater than the voltage value of the second power signal VGL1 as an example, but this cannot be understood as a limitation of the present application.

[0062] In the embodiment of the present application, the compensation module 20 comprises a first compensation unit 21. The first compensation unit 21 comprises a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a first resistor R1 and a first diode D1.

[0063] The gate of the third transistor Q3 is connected to the first clock signal CK_in. The source of the third transistor Q3 is connected to the third input terminal 20b, i.e. connected to the adjusting signal K. The drain of the third transistor Q3, the gate of the fourth transistor Q4 and the gate of the fifth transistor Q5 are connected together. The source of the fourth transistor Q4 and the source of the fifth transistor Q5 are both connected to the fourth input terminal 20c. The drain of the fourth transistor Q4 is connected to the second output terminal 20f. The drain of the fifth transistor Q5 is connected to one end of the first resistor R1. The other end of the first resistor R1 and the anode of the first diode D1 are connected to the second output terminal 20f. The cathode of the first diode D1 is connected to the fifth input terminal 20d, i.e. connected to the third power signal VGH.

[0064] The compensation module 20 further comprises a second compensation unit 22. The second compensation unit 22 comprises a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, a second resistor R2 and a second diode D2.

[0065] The gate of the sixth transistor Q6 is connected to the first clock signal CK_in. The source of the sixth transistor Q6 is connected to the third input terminal 20b, i.e. connected to the adjusting signal K. The drain of the sixth transistor Q6, the gate of the seventh transistor Q7 and the gate of the eighth transistor Q8 are connected together. The source of the seventh transistor Q7 and the source of the eighth transistor Q8 are both connected to the fourth input terminal 20c. The drain of the seventh transistor Q7 is connected to the second output terminal 20f. The drain of the eighth transistor Q8 is connected to one end of the second resistor R2. The other end of the second resistor R2 and the cathode of the second diode D2 are connected to the second output terminal 20f. The anode of the second diode D2 is connected to the sixth input terminal 20e, i.e. connected to the fourth power signal VGL.

[0066] In the embodiment of the present application, the voltage value of the first power signal VGH1 is greater than the voltage value of the third power signal VGH. The voltage absolute value of the second power signal VGL1 is greater than the voltage absolute value of the fourth power signal. The third transistor Q3, the fourth transistor Q4 and the seventh transistor Q7 are N-type transistors, and the fifth transistor Q5, the sixth transistor Q6 and the eighth transistor Q8 are P-type transistors.

[0067] The adjustment signal K includes a third high level k1, a third low level k2, a fourth high level k3 and a fourth low level k4 which appear alternately in sequence. The third high level k1 and the third low level k2 have a duration equal to that of the second high level A2. The fourth high level k3 and the fourth low level k4 have a duration equal to that of the second low level A1.

[0068] In detail, please refer to Figure 5 and Figure 6 When the first clock signal CK_in is at the first high level a2, the first transistor T1 is turned on, and the first power signal VGH1 is transmitted to the first output terminal 10d through the first transistor T1. When the first clock signal CK_in is at the first low level a1, the second transistor T2 is turned on, and the second power signal VGL1 is transmitted to the first output terminal 10d through the second transistor T2. In this way, as the level of the first clock signal CK_in changes, the voltage conversion module 10 can output the second clock signal CKA at the first output terminal 10d, which has the same waveform as the first clock signal CK_in.

[0069] Meanwhile, when the first clock signal CK_in is at the first high level a2, the third transistor Q3 is turned on; the adjustment signal K is at the third high level k1, the fourth transistor Q4 is turned on, and the first power signal VGH1 is transmitted to the second output terminal 20f through the first transistor T1 and the fourth transistor Q4; then, the adjustment signal K changes from the third high level k1 to the third low level k2, the fifth transistor Q5 is turned on, and under the action of the limiting circuit composed of the third power signal VGH and the first diode D1, the first power signal VGH1 is outputted to the second output terminal 20f through the first transistor T1, the fifth transistor Q5 and the first resistor R1.

[0070] Then, when the first clock signal CK_in changes from the first high level a2 to the first low level a1, the sixth transistor Q6 is turned on; the adjustment signal K changes from the third low level k2 to the fourth high level k3, the seventh transistor Q7 is turned on, and the second power signal VGL1 is transmitted to the second output terminal 20f through the sixth transistor Q6 and the seventh transistor Q7; then, the adjustment signal K changes from the fourth high level k3 to the fourth low level k4, the eighth transistor Q8 is turned on, and under the action of the limiting circuit composed of the fourth power signal VGL and the second diode D2, the second power signal VGL1 is outputted to the second output terminal 20f through the sixth transistor Q6, the eighth transistor Q8 and the second resistor R2. In this way, as the levels of the first clock signal CK_in and the adjustment signal K change, the compensation module 20 can output the target clock signal CK_out at the second output terminal 20f.

[0071] The limiting circuit primarily clamps the voltage at the second output terminal 20f to the potential of either the third power supply signal VGH or the fourth power supply signal VGL. Taking the VGH clamping circuit as an example, when the fifth transistor Q5 is turned on, the potential at the drain of the fifth transistor Q5 is the potential of the second power supply signal VGL1. After being divided by the first resistor R1, the voltage at the second output terminal 20f is clamped to the potential of the third power supply signal VGH. The resistance value of the first resistor R1 can be set according to the first power supply signal VGH1 and the third power supply signal VGH. Similarly, the resistance value of the second resistor R2 can be set according to the second power supply signal VGL1 and the fourth power supply signal VGL.

[0072] like Figure 6 As shown, the target clock signal CK_out is a signal in which the second high level A2, the fifth high level A4, the second low level A1, and the fifth low level A3 alternate sequentially. The second high level A2 is equal to the voltage value of the first power supply signal VGH1; the fifth high level A4 is equal to the voltage value of the third power supply signal VGH; the second low level A1 is equal to the voltage value of the second power supply signal VGL1; and the fifth low level A3 is equal to the voltage value of the fourth power supply signal VGL. Since the voltage value of the first power supply signal VGH1 is greater than that of the third power supply signal VGH, and the absolute value of the voltage value of the second power supply signal VGL1 is greater than that of the fourth power supply signal, the voltage at the rising and falling edges of the target clock signal CK_out is higher. This increases the amplitude of the high-frequency components of the target clock signal CK_out in the frequency domain, thereby compensating for the loss of high-frequency components during transmission and improving the charging rate.

[0073] In this embodiment, the voltage adjustment width at the rising and falling edges of the target clock signal CK_out depends on the duty cycle of the adjustment signal K. The duty cycle refers to the proportion of the on-time relative to the total time within a pulse cycle.

[0074] Specifically, the position of the first rising edge t3 depends on the duration of the fourth high level k3. The voltage adjustment width at the rising edge of the target clock signal CK_out (the duration of the second high level A2) is equal to the duration of the third high level k1. The duration of the first preset time t11 is equal to the duration of the fourth low level k4. The position of the first falling edge t1 depends on the duration of the third high level k1. The voltage adjustment width at the falling edge of the target clock signal CK_out (the duration of the first low level A1) is equal to the duration of the fourth high level k3. The duration of the second preset time t12 is equal to the duration of the third low level k2. The duty cycle of the adjustment signal K can be adjusted according to the transmission loss of the target clock signal CK_out.

[0075] The transistors used in all the embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and the drain of the transistors used herein are symmetrical, the source and the drain can be interchangeable. In the embodiments of the present application, one of the two poles of the transistor other than the gate is referred to as the source and the other is referred to as the drain. In the mode shown in the drawings, the middle terminal of the switching transistor is the gate, the signal input terminal is the source and the output terminal is the drain. In addition, the transistors used in the embodiments of the present application can include both P-type transistors and / or N-type transistors, wherein the P-type transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level, and the N-type transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level.

[0076] For example, in an embodiment of the present application, the first transistor T1 and the second transistor T2 are MOS tubes, which are commonly used field effect transistors. The MOS tube is relatively stable and conducive to integration. The third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7 and the eighth transistor Q8 are transistors, which mainly serve as switches. Of course, the present application is not limited thereto.

[0077] Please refer to Figure 1 and Figure 7 , Figure 7 is a second circuit schematic diagram of the voltage conversion circuit provided by the present application. Different from the voltage conversion circuit 100 shown in Figure 5 , in the embodiments of the present application, the first compensation unit 21 includes the third transistor Q3, the fourth transistor Q4 and the fifth transistor Q5.

[0078] The gate of the third transistor Q3 is connected to the first clock signal CK_in. The source of the third transistor Q3 is connected to the third input terminal 20b, i.e., connected to the adjustment signal K. The drain of the third transistor Q3, the gate of the fourth transistor Q4 and the gate of the fifth transistor Q5 are connected together. The source of the fourth transistor Q4 is connected to the fourth input terminal 20c. The source of the fifth transistor Q5 is connected to the third power supply signal VGH. The drain of the fourth transistor Q4 and the drain of the fifth transistor Q5 are both connected to the second output terminal 20f.

[0079] The working timing of the voltage conversion circuit 100 in the embodiments of the present application is the same as the signal timing in the voltage conversion circuit 100 shown in Figure 5 , except that when the first clock signal CK_in is the first high level a2 and the adjustment signal K is changed from the third high level k1 to the third low level k2, the fifth transistor Q5 is turned on and the third power supply signal VGH is output to the second output terminal 20f through the fifth transistor Q5.

[0080] The circuit structure of the first compensation unit 21 is simplified in the embodiments of the present application.

[0081] In some embodiments of the present application, the second compensation unit 22 comprises a sixth transistor Q6, a seventh transistor Q7 and an eighth transistor Q8.

[0082] The gate of the sixth transistor Q6 is connected to the first clock signal CK_in. The source of the sixth transistor Q6 is connected to the third input terminal 20b, i.e. connected to the adjustment signal K. The drain of the sixth transistor Q6, the gate of the seventh transistor Q7 and the gate of the eighth transistor Q8 are connected together. The source of the seventh transistor Q7 is connected to the fourth input terminal 20c. The source of the eighth transistor Q8 is connected to the sixth input terminal 20e, i.e. connected to the fourth power signal VGL. The drain of the seventh transistor Q7 and the drain of the eighth transistor Q8 are both connected to the second output terminal 20f.

[0083] The working timing of the voltage conversion circuit 100 of the embodiments of the present application is the same as that of the voltage conversion circuit 100 shown in Figure 5 the difference is that when the first clock signal CK_in is changed from the first high level a2 to the first low level al and the adjustment signal K is changed from the fourth high level k3 to the fourth low level k4, the eighth transistor Q8 is turned on, and the fourth power signal VGL is output to the second output terminal 20f through the eighth transistor Q8.

[0084] Similarly, the embodiments of the present application simplify the circuit structure of the second compensation unit 22.

[0085] Please refer to Figure 8 , Figure 8 is a third circuit schematic diagram of the voltage conversion circuit provided by the present application. Compared with Figure 5 the difference is that in the embodiments of the present application, the voltage value of the first power signal VGH1 is smaller than the voltage value of the third power signal VGH. The absolute value of the voltage of the second power signal VGL1 is smaller than the absolute value of the voltage of the fourth power signal VGL. The third transistor Q3, the fifth transistor Q5 and the eighth transistor Q8 are N-type transistors, and the fourth transistor Q4, the sixth transistor Q6 and the seventh transistor Q7 are P-type transistors.

[0086] When the first clock signal CK_in is the first high level a2, the third transistor Q3 is turned on; the adjusting signal K is the third high level k1, the fifth transistor Q5 is turned on, under the action of the limiting circuit composed of the third power signal VGH and the first diode D1, the first power signal VGH1 is transmitted to the second output end 20f through the first transistor T1, the fifth transistor Q5 and the first resistor R1, and the third power signal VGH is output to the second output end 20f; then, the adjusting signal K is changed from the third high level k1 to the third low level k2, the fourth transistor Q4 is turned on, and the first power signal VGH1 is transmitted to the second output end 20f through the first transistor T1 and the fifth transistor Q5.

[0087] Then, when the first clock signal CK_in is changed from the first high level a2 to the first low level a1, the eighth transistor Q8 is turned on, under the action of the limiting circuit composed of the fourth power signal VGL and the second diode D2, the second power signal VGL1 is transmitted to the second output end 20f through the sixth transistor Q6, the eighth transistor Q8 and the second resistor R2, and the fourth power signal VGL is output to the second output end 20f; then, the adjusting signal K is changed from the fourth high level k3 to the fourth low level k4, the sixth transistor Q6 is turned on; the adjusting signal K is changed from the third low level k2 to the fourth high level k3, the seventh transistor Q7 is turned on, and the second power signal VGL1 is transmitted to the second output end 20f through the sixth transistor Q6 and the seventh transistor Q7. In this way, with the change of the level of the first clock signal CK_in and the adjusting signal K, the compensation module 20 can output the target clock signal CK_out at the second output end 20f.

[0088] As shown in Figure 9 the fifth high level A4, the second high level A2, the fifth low level A3 and the second low level A1 appear alternately. The fifth high level A4 is equal to the voltage value of the third power signal VGH; the fifth low level A3 is equal to the voltage value of the fourth power signal VGL; the second high level A2 is equal to the voltage value of the first power signal VGH1; and the second low level A1 is equal to the voltage value of the second power signal VGL1. Since the voltage value of the first power signal VGH1 is less than the voltage value of the third power signal VGH, and the absolute value of the voltage of the second power signal VGL1 is less than the absolute value of the voltage of the fourth power signal, the voltage at the rising and falling edges of the target clock signal CK_out is higher, the amplitude of the high frequency component of the target clock signal CK_out in the frequency domain is improved, thereby compensating for the loss of high frequency components in transmission and improving the charging rate.

[0089] The application can realize the function of the voltage conversion circuit 100 by adjusting the types of the first transistor T1, the second transistor T2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, and the eighth transistor Q8, and adjusting the voltage values of the first power signal VGH1, the second power signal VGL1, the third power signal VGH, and the fourth power signal VGL, which will not be described here.

[0090] In the embodiment of the application, the voltage difference between the first power signal VGH1 and the third power signal VGH is usually 6V to 10V (volt), and the voltage difference between the second power signal VGL1 and the fourth power signal VGL is usually -6V to -3V. Within the above pressure difference range, the loss of high-frequency components in transmission can be better compensated. For example, in a specific embodiment, the voltage value of the first power signal VGH1 is 36V (volt), the voltage value of the third power signal VGH is 28V, the voltage value of the second power signal VGL1 is -10V, and the voltage value of the fourth power signal VGL is -14V.

[0091] The application also provides a target clock signal CK_out, which can be specifically referred to Figure 3 and Figure 6 . The target clock signal CK_out includes a plurality of continuous clock periods. Each clock period includes a rising edge and a falling edge. The rising edge includes two sub-rising edges, namely a first sub-rising edge t3 and a second sub-rising edge t4. The falling edge has two sub-falling edges, namely a first sub-falling edge t1 and a second sub-falling edge t2. The first sub-rising edge t3 and the second sub-rising edge t4 are separated by a first preset time t11. The first sub-falling edge t1 and the second sub-falling edge t2 are separated by a second preset time t12.

[0092] Specifically, the target clock signal CK_out is a signal in which the second high level A2, the fifth high level A4, the second low level A1, and the fifth low level A3 appear alternately. The second high level A2 is greater than the fifth high level A4. The second low level A1 is greater than the fifth low level A3.

[0093] Among them, the target clock signal CK_out is an ideal signal without loss, so the transition of the target clock signal CK_out from the second high level A2 to the fifth high level A4, from the fifth high level A4 to the second low level A1, and from the second low level A1 to the fifth low level A3 can be considered as an instantaneous action. That is, the rising edge time corresponding to the first sub-rising edge t3 and the second sub-rising edge t4 of the target clock signal CK_out can be considered as 0, and the falling edge time corresponding to the first sub-falling edge t1 and the second sub-falling edge t2 of the target clock signal CK_out can be considered as 0.

[0094] The application modifies the waveform of the target clock signal CK_out, so that the waveform at the rising edge and the falling edge of the target clock signal CK_out is improved after transmission loss, and the charging rate of the display device using the target clock signal CK_out is effectively improved.

[0095] The application also provides a near-end scanning signal, which can be specifically referred to Figure 3 As can be seen from the above embodiments, the GOA unit receives the target clock signal CK_out and outputs a scanning signal. The waveform of the scanning signal is basically consistent with the waveform of the received target clock signal CK_out, and therefore can be referred to curve D.

[0096] Specifically, the near-end scanning signal includes a continuous first rising time period t21, a second rising time period t22, a first falling time period t23 and a second falling time period t24. In the first rising time period t21, the voltage value of the near-end scanning signal gradually increases. In the second rising time period t22, the voltage value of the near-end scanning signal first decreases and then increases. In the first falling time period t23, the voltage value of the near-end scanning signal gradually decreases. In the second falling time period t24, the voltage value of the near-end scanning signal gradually increases to a fixed value.

[0097] That is, the near-end scanning signal has a first wave crest at the intersection of the first rising time period t21 and the second rising time period t22. The near-end scanning signal has a second wave crest at the intersection of the second rising time period t22 and the first falling time period t23. The near-end scanning signal has a wave trough at the intersection of the first falling time period t23 and the second falling time period t24.

[0098] Compared with the waveform of the uncompensated target clock signal at the near end shown in curve B, the waveform of the rising edge and the falling edge of the near-end scanning signal provided by the application is improved, and the charging rate of the display panel is effectively improved.

[0099] Please refer to Figure 10 , Figure 10 is a structural schematic diagram of a display device provided by the application. The display device 1000 includes a display panel 200 and a voltage conversion circuit 100. The voltage conversion circuit 100 is any one of the voltage conversion circuits 100 described above, and can be specifically referred to the above embodiments, which will not be described here. The voltage conversion circuit 100 outputs a target clock signal CK_out to the display panel 200.

[0100] The display panel 200 includes a plurality of scan lines 201, a plurality of data lines 202, and a plurality of sub-pixels 203. The plurality of scan lines 201 are arranged along a column direction. The plurality of data lines 202 are arranged along a row direction. The plurality of sub-pixels 203 are arranged in an array. The display panel 200 further includes at least one GOA circuit 204. The GOA circuit 204 is disposed in a non-display area of the display panel 200. The GOA circuit 204 is connected with the plurality of scan lines 201 to provide a scan signal to a corresponding scan line 201.

[0101] In some embodiments of the present application, the display device 1000 further includes a timing control chip 400 and a power management integrated circuit 300. The voltage conversion circuit 100 is integrated in the power management integrated circuit 300. The timing control chip 400 outputs a first clock signal CK_in to the power management integrated circuit 300.

[0102] Figure 10 In some embodiments of the present application, the display panel 200 adopts a 1G1D (1 Gate & 1 Data) driving architecture, i.e., one column of sub-pixels 203 corresponds to one scan line 201 and one data line 202. However, the present application is not limited thereto.

[0103] In some embodiments of the present application, each sub-pixel 203 includes a first side edge 203a and a second side edge 203b arranged adjacently. The length of the first side edge 203a is greater than the length of the second side edge 203b. The extension direction of the scan line 201 is parallel to the first side edge 203a.

[0104] The display panel 200 in the embodiments of the present application adopts a Tri-gate architecture. The Tri-gate architecture is a commonly used method to reduce cost. The structure is to rotate all the sub-pixels 203 by 90 degrees. For example, when the sub-pixels 203 are arranged in an RGB structure, the number of scan lines 201 is increased by three times, and the number of data lines 202 is reduced to 1 / 3 of the original. Since the cost of a data chip is relatively high, the use amount of the data chip is reduced by the above method, thereby achieving the purpose of reducing cost.

[0105] However, compared with the 1G1D architecture, the scan lines of the Tri-gate architecture are usually 3 times of the 1G1D architecture, the attenuation of the target clock signal CK_out transmitted to the GOA circuit 204 is more serious, and the charging rate is poorer. By applying the voltage conversion circuit 100 in the display device 1000 with the Tri-gate architecture, the voltage at the rising edge and the falling edge of the target clock signal CK_out is compensated, so that each rising edge of the target clock signal CK_out includes two sub-rising edges, each falling edge of the target clock signal CK_out includes two sub-falling edges, the amplitude of the high-frequency component of the target clock signal CK_out in the frequency domain is improved, thereby compensating the loss of the high-frequency component of the target clock signal CK_out in the transmission, improving the charging rate, and improving the display effect.

[0106] Of course, the display panel 200 in the embodiments of the present application can also use other driving architectures with more scan lines 201, such as a DLS (Data Line Sharing) architecture, etc., which are not limited in the present application.

[0107] The voltage conversion circuit, the display device, the target clock signal and the near-end scan signal provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples in this paper. The above description of the embodiments is only used to help understand the method of the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation manner and application range will be changed, and the above description should not be understood as a limitation of the present application.

Claims

1. A voltage conversion circuit, characterized by, The application relates to a voltage conversion module and a compensation module. The voltage conversion module has a first control terminal, a first input terminal, a second input terminal and a first output terminal, the first control terminal is connected with a first clock signal, the first input terminal is connected with a first power supply signal, the second input terminal is connected with a second power supply signal, and the voltage conversion module is used for outputting a second clock signal at the first output terminal according to the first clock signal, the first power supply signal and the second power supply signal, the second clock signal has the same waveform as the first clock signal but different voltage amplitude. The compensation module has a second control terminal, a third input terminal, a fourth input terminal, a fifth input terminal, a sixth input terminal and a second output terminal, the second control terminal is connected with the first clock signal, the third input terminal is connected with an adjustment signal, the fourth input terminal is connected with the first output terminal, the fifth input terminal is connected with a third power supply signal, the sixth input terminal is connected with a fourth power supply signal, and the compensation module is used for outputting a target clock signal at the second output terminal according to the first clock signal, the adjustment signal, the second clock signal, the third power supply signal and the fourth power supply signal, each rising edge of the target clock signal comprises two sub-rising edges, each falling edge of the target clock signal comprises two sub-falling edges, the first preset time is arranged between the two sub-rising edges, and the second preset time is arranged between the two sub-falling edges. The compensation module comprises a first compensation unit, and the first compensation unit comprises a third transistor, a fourth transistor, a fifth transistor, a first resistor and a first diode. The gate of the third transistor is connected with the first clock signal, the signal input pole of the third transistor is connected with the third input terminal, the signal output pole of the third transistor, the gate of the fourth transistor and the gate of the fifth transistor are connected together, the signal input pole of the fourth transistor and the signal input pole of the fifth transistor are connected with the fourth input terminal, the signal output pole of the fourth transistor is connected with the second output terminal, the signal output pole of the fifth transistor is connected with one end of the first resistor, the other end of the first resistor and the anode of the first diode are connected with the second output terminal, and the cathode of the first diode is connected with the fifth input terminal. Alternatively, the compensation module comprises a first compensation unit, and the first compensation unit comprises a third transistor, a fourth transistor and a fifth transistor. The gate of the third transistor is connected with the first clock signal, the signal input pole of the third transistor is connected with the third input terminal, the signal output pole of the third transistor, the gate of the fourth transistor and the gate of the fifth transistor are connected together, the signal input pole of the fourth transistor is connected with the fourth input terminal, the signal input pole of the fifth transistor is connected with the fifth input terminal, and the signal output pole of the fourth transistor and the signal output pole of the fifth transistor are connected with the second output terminal.

2. The voltage conversion circuit according to claim 1, characterized by The voltage conversion module comprises a first transistor and a second transistor; a gate of the first transistor and a gate of the second transistor are connected to the first control end; a signal input pole of the first transistor is connected to the first input end; a signal input pole of the second transistor is connected to the second input end; a signal output pole of the first transistor and a signal output pole of the second transistor are connected to the first output end. The first transistor is one of an N-type transistor and a P-type transistor, and the second transistor is the other one of the N-type transistor and the P-type transistor.

3. The voltage conversion circuit of claim 1, wherein, The voltage value of the first power supply signal is greater than the voltage value of the third power supply signal; the fourth transistor is an N-type transistor; and the fifth transistor is a P-type transistor. Or the voltage value of the first power supply signal is less than the voltage value of the third power supply signal; the fourth transistor is a P-type transistor; and the fifth transistor is an N-type transistor.

4. The voltage conversion circuit of claim 1, wherein, The compensation module comprises a second compensation unit, and the second compensation unit comprises a sixth transistor, a seventh transistor, an eighth transistor, a second resistor and a second diode; the sixth transistor is a P-type transistor. The gate of the sixth transistor is connected to the first clock signal; a signal input pole of the sixth transistor is connected to the adjustment signal; a signal output pole of the sixth transistor, a gate of the seventh transistor and a gate of the eighth transistor are connected together; a signal input pole of the seventh transistor and a signal input pole of the eighth transistor are connected to the first output end; a signal output pole of the seventh transistor is connected to the second output end; a signal output pole of the eighth transistor and one end of the second resistor are connected together; the other end of the second resistor and a cathode of the second diode are connected to the second output end; and an anode of the second diode is connected to the fourth power supply signal.

5. The voltage conversion circuit of claim 1, wherein, The compensation module comprises a second compensation unit, and the second compensation unit comprises a sixth transistor, a seventh transistor and an eighth transistor; the sixth transistor is a P-type transistor. The gate of the sixth transistor is connected to the first clock signal; a signal input pole of the sixth transistor is connected to the adjustment signal; a signal output pole of the sixth transistor, a gate of the seventh transistor and a gate of the eighth transistor are connected together; a signal input pole of the seventh transistor is connected to the first output end; a signal input pole of the eighth transistor is connected to the fourth power supply signal; and a signal output pole of the seventh transistor and a signal output pole of the eighth transistor are connected to the second output end.

6. The voltage conversion circuit according to claim 4 or 5, characterized by The voltage value of the second power supply signal is greater than the voltage value of the fourth power supply signal; the seventh transistor is a P-type transistor; and the eighth transistor is an N-type transistor. Or the voltage value of the second power supply signal is less than the voltage value of the fourth power supply signal; the seventh transistor is an N-type transistor; and the eighth transistor is a P-type transistor.

7. The voltage conversion circuit of claim 1, wherein, The first clock signal comprises a first high level and a first low level alternately appearing, the second clock signal comprises a second high level and a second low level alternately appearing, the second high level is greater than the first high level, and the second low level is less than the first low level.

8. The voltage conversion circuit of claim 7, wherein, The adjustment signal comprises a third high level, a third low level, a fourth high level and a fourth low level alternately appearing; the third high level and the third low level have a duration equal to that of the second high level, and the fourth high level and the fourth low level have a duration equal to that of the second low level.

9. A voltage conversion circuit, characterized by comprising: Comprise: A voltage conversion module having a first control end, a first input end, a second input end and a first output end, the first control end being connected to a first clock signal, the first input end being connected to a first power signal, the second input end being connected to a second power signal, the voltage conversion module being configured to output a second clock signal at the first output end according to the first clock signal, the first power signal and the second power signal, the second clock signal having the same waveform as the first clock signal but different voltage amplitude; A compensation module having a second control end, a third input end, a fourth input end, a fifth input end, a sixth input end and a second output end, the second control end being connected to the first clock signal, the third input end being connected to an adjustment signal, the fourth input end being connected to the first output end, the fifth input end being connected to a third power signal, the sixth input end being connected to a fourth power signal, the compensation module being configured to output a target clock signal at the second output end according to the first clock signal, the adjustment signal, the second clock signal, the third power signal and the fourth power signal, each rising edge of the target clock signal comprising two sub-rising edges, each falling edge of the target clock signal comprising two sub-falling edges, the two sub-rising edges being separated by a first preset time, and the two sub-falling edges being separated by a second preset time; The compensation module comprises a second compensation unit, and the second compensation unit comprises a sixth transistor, a seventh transistor, an eighth transistor, a second resistor and a second diode. The gate of the sixth transistor is connected to the first clock signal, the signal input end of the sixth transistor is connected to the adjustment signal, the signal output end of the sixth transistor, the gate of the seventh transistor and the gate of the eighth transistor are connected together, the signal input end of the seventh transistor and the signal input end of the eighth transistor are connected to the first output end, the signal output end of the seventh transistor is connected to the second output end, the signal output end of the eighth transistor and one end of the second resistor are connected together, the other end of the second resistor and the cathode of the second diode are connected to the second output end, and the anode of the second diode is connected to the fourth power signal. Alternatively, the compensation module comprises a second compensation unit, and the second compensation unit comprises a sixth transistor, a seventh transistor and an eighth transistor. A gate of the sixth transistor is connected to the first clock signal, a signal input end of the sixth transistor is connected to the adjustment signal, a signal output end of the sixth transistor, a gate of the seventh transistor and a gate of the eighth transistor are connected together, a signal input end of the seventh transistor is connected to the first output end, a signal input end of the eighth transistor is connected to the fourth power signal, and a signal output end of the seventh transistor and a signal output end of the eighth transistor are both connected to the second output end.

10. The voltage conversion circuit of claim 9, wherein, The voltage conversion module comprises a first transistor and a second transistor; a gate of the first transistor and a gate of the second transistor are both connected to the first control end, a signal input end of the first transistor is connected to the first input end, a signal input end of the second transistor is connected to the second input end, and a signal output end of the first transistor and a signal output end of the second transistor are both connected to the first output end. The first transistor is one of an N-type transistor and a P-type transistor, and the second transistor is the other one of the N-type transistor and the P-type transistor.

11. The voltage conversion circuit of claim 9, wherein, The compensation module comprises a first compensation unit, and the first compensation unit comprises a third transistor, a fourth transistor, a fifth transistor, a first resistor and a first diode. The gate of the third transistor is connected to the first clock signal, a signal input end of the third transistor is connected to the third input end, a signal output end of the third transistor, a gate of the fourth transistor and a gate of the fifth transistor are connected together, a signal input end of the fourth transistor and a signal input end of the fifth transistor are both connected to the fourth input end, a signal output end of the fourth transistor is connected to the second output end, a signal output end of the fifth transistor and one end of the first resistor are connected together, the other end of the first resistor and an anode of the first diode are connected to the second output end, and a cathode of the first diode is connected to the fifth input end.

12. The voltage conversion circuit of claim 9, wherein, The compensation module comprises a first compensation unit, and the first compensation unit comprises a third transistor, a fourth transistor and a fifth transistor. The gate of the third transistor is connected to the first clock signal, a signal input end of the third transistor is connected to the third input end, a signal output end of the third transistor, a gate of the fourth transistor and a gate of the fifth transistor are connected together, a signal input end of the fourth transistor is connected to the fourth input end, a signal input end of the fifth transistor is connected to the fifth input end, and a signal output end of the fourth transistor and a signal output end of the fifth transistor are both connected to the second output end.

13. The voltage conversion circuit according to claim 11 or 12, characterized in that, The voltage value of the first power signal is greater than the voltage value of the third power signal, the fourth transistor is an N-type transistor, and the fifth transistor is a P-type transistor. Or the voltage value of the first power signal is less than the voltage value of the third power signal, the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.

14. The voltage conversion circuit of claim 9, wherein, The voltage value of the second power supply signal is greater than the voltage value of the fourth power supply signal, the seventh transistor is a P-type transistor, and the eighth transistor is an N-type transistor. Or the voltage value of the second power supply signal is less than the voltage value of the fourth power supply signal, the seventh transistor is an N-type transistor, and the eighth transistor is a P-type transistor.

15. The voltage conversion circuit of claim 9, wherein, The first clock signal comprises a first high level and a first low level alternately appearing, and the second clock signal comprises a second high level and a second low level alternately appearing, the second high level being greater than the first high level, and the second low level being less than the first low level.

16. The voltage conversion circuit of claim 15, wherein, The adjustment signal comprises a third high level, a third low level, a fourth high level and a fourth low level alternately appearing, the duration of the third high level and the third low level being equal to the duration of the second high level, and the duration of the fourth high level and the fourth low level being equal to the duration of the second low level.

17. A display device comprising: The display panel comprises a display panel and a voltage conversion circuit, the voltage conversion circuit being the voltage conversion circuit according to any one of claims 1-16, and the voltage conversion circuit outputs the target clock signal to the display panel.

18. The display device of claim 17, wherein, The display panel comprises a plurality of scanning lines and a plurality of sub-pixels arranged in an array, each of the sub-pixels comprises a first side and a second side arranged adjacently, and the extension direction of the scanning lines is parallel to the first side.

Images