A method and apparatus for total dose radiation testing of resistive random access memory

Abstract

The application relates to the field of resistive random access memory (RRAM), and specifically discloses a total dose radiation test method for RRAM, which comprises the following steps: grouping a plurality of RRAMs to obtain M groups of RRAMs, each group of RRAMs comprising N RRAMs, and the M groups of RRAMs corresponding to M initial resistance states respectively; performing a total dose radiation experiment on the M groups of RRAMs; and performing a cycle endurance experiment on the M groups of RRAMs, wherein the result of the cycle endurance experiment is used to indicate a test result of the RRAMs related to the total dose radiation. Through the test method, the change in the endurance of the RRAMs after being subjected to total dose radiation can be simulated, so as to provide an optimization scheme for the application of the RRAMs in a total dose radiation environment.

Description

Technical Field

[0001] The present application relates to the technical field of resistive random access memory, and in particular to a total dose radiation testing method and device for resistive random access memory. Background Art

[0002] With the advancement of aerospace technology, the types and volumes of data required to be processed by aerospace chips have increased dramatically, placing higher demands on the data storage and computing capabilities of aerospace electronic devices. Resistive random access memory (RRAM) has great potential for aerospace applications due to its simple structure, scalability, high speed, low power consumption, compatibility with CMOS processes, analog characteristics, and multi-value storage. However, aerospace chips operate in the harsh radiation environment of space. The cumulative radiation effects of total radiation doses from space radiation, such as electrons, X-rays, and gamma rays, can cause RRAM performance fluctuations, leading to degradation of the device's cycling tolerance and causing serious reliability issues.

[0003] Since the performance fluctuations of resistive random access memories with different resistance states and windows to total radiation dose may be different, if the resistance state, window and other information of the resistive random access memory are set arbitrarily and applied arbitrarily in a space radiation environment, the cyclic tolerance of the resistive random access memory may be seriously degraded, affecting the normal operation of the aerospace chip. Summary of the Invention

[0004] The present application provides a total-dose radiation testing method and apparatus for resistive random access memory (RRAM). This testing method allows statistical analysis of changes in the resistance of RRAM after exposure to total-dose radiation, thereby providing optimization solutions for the use of RRAM in total-dose radiation environments. In one application scenario, the test results can be used to design the usable resistance state range of the RRAM in conjunction with a specific total-dose radiation scenario. In another application scenario, the test results can be used to determine whether the designed RRAM can meet the requirements of use in a specific total-dose radiation scenario.

[0005] In a first aspect, a method for testing total radiation dose of a resistive random access memory is provided, the method comprising:

[0006] Grouping the plurality of resistive memory devices to obtain M groups of resistive memory devices, each group of resistive memory devices including N resistive memory devices, and the M groups of resistive memory devices respectively corresponding to M initial resistance states;

[0007] Performing a total dose radiation experiment on the M groups of resistive random access memories;

[0008] A cyclic tolerance test is performed on the M groups of resistive random access memories, and a result of the cyclic tolerance test is used to indicate a test result of the resistive random access memory related to the total radiation dose.

[0009] Compared with the existing technology, the solution provided by this application includes at least the following beneficial technical effects:

[0010] (1) The tolerance change of the resistive random access memory after being subjected to total dose radiation can be statistically analyzed to provide an optimization solution for the application of the resistive random access memory in a total dose radiation environment. In one application scenario, the available resistance state range of the resistive random access memory can be designed based on the test results and combined with the specific total dose radiation scenario. In another application scenario, the test results can be used to determine whether the designed resistive random access memory can meet the usage requirements in a specific total dose radiation scenario.

[0011] (2) It can systematically and accurately test and characterize the parameter fluctuations and tolerance drift of RRAM after total dose radiation, providing effective data for the total dose radiation evaluation and assessment of RRAM; accurately obtaining the total dose radiation degradation law of RRAM is of great significance for further optimizing the radiation characteristics of RRAM and promoting the aerospace application of RRAM.

[0012] In conjunction with the first aspect, in certain implementations of the first aspect, a test result of the resistive random access memory related to the total radiation dose includes at least one of the following:

[0013] The available resistance state range of the resistive random access memory under a preset total dose radiation environment;

[0014] A total radiation dose environment in which the resistive random access memory can be applied;

[0015] Whether the resistive random access memory is usable under a preset total dose radiation environment.

[0016] In one possible scenario, technicians intend to apply a resistive random access memory (RRAM) to a spacecraft. The total radiation dose environment that the spacecraft may experience can be determined through simulation, experimentation, and other methods. Through the solutions provided in the embodiments of this application, the low-resistance and high-resistance states of the RRAM can be optimized, resulting in a relatively large resistance window and relatively good tolerance performance.

[0017] In one possible scenario, a technician intends to use a resistive random access memory (RRAM) in a spacecraft. However, the RRAM has different tolerance limits in different total-dose radiation environments. Using the solution provided in the embodiments of this application, the RRAM can be placed in multiple total-dose radiation environments and the tolerance of each RRAM can be verified one by one to determine the RRAM's tolerance limit.

[0018] In one possible scenario, the total radiation dose environment that a spacecraft may be subjected to can be obtained through simulation, experimentation, etc. The solution provided by the embodiments of the present application can verify whether the low-resistance state and high-resistance state of a resistive random access memory can have the required cycling tolerance performance under the known total radiation dose environment; if so, the experimental results can guide technicians in applying the resistive random access memory to a spacecraft, so that the spacecraft can be successfully designed and operated; if not, the experimental results can guide technicians in selecting other suitable resistive random access memories for application.

[0019] In combination with the first aspect, in some implementations of the first aspect, the M groups of resistive switching memories correspond to M high-resistance R h and M low resistance R l , the plurality of resistive switching memories are grouped to obtain M groups of resistive switching memories, including:

[0020] Perform a read operation on the target resistive random access memory and obtain the resistance value of the target resistive random access memory as R mn ;

[0021] When R mn ≥(R hm +R lm ) / 2, perform J times of resistance-lowering operations, each resistance-lowering operation includes a first write operation and a first reset operation. After the J times of resistance-lowering operations are successful, R lm *(1-λ L %)≤R mn ≤R lm *(1+λ L %), λ L % is the maximum resistance error allowed in the low resistance state of the target resistive random access memory, R hm The target high resistance R corresponding to the group where the target resistive memory is located hm , R lm The target low resistance R corresponding to the group where the target resistive memory is located lm ;

[0022] When R mn <(R hm +R lm ) / 2, perform K high resistance adjustment operations, each high resistance adjustment operation includes a second reset operation and a second write operation, after the K high resistance adjustment operations are successful, R hm *(1-λ H %)≤R mn ≤R hm *(1+λ H %), λ H % is the maximum resistance error allowed in the high-resistance state of the target resistive random access memory;

[0023] The write operation includes:

[0024] Apply a write pulse amplitude V to the target resistive memory device setm , pulse width P setm , write gate voltage pulse amplitude V gsetm , pulse width P gsetm Write operation;

[0025] Apply a read pulse amplitude V to the target resistive memory device R , pulse width P R , and the read gate voltage pulse amplitude V gR , pulse width P gR Read operation;

[0026] The reset operation includes:

[0027] Apply a reset pulse amplitude V to the target resistive memory device rem , pulse width P rem and reset gate voltage pulse amplitude V grem , pulse width P grem Reset operation;

[0028] Apply a read pulse amplitude V to the target resistive memory device R , pulse width P R , and the read gate voltage pulse amplitude V gR , pulse width P gR Read operation.

[0029] In this way, the low-resistance state and high-resistance state of the M groups of resistive random access memories can be flexibly adjusted, and resistive random access memories that do not meet the test requirements can be promptly eliminated.

[0030] In conjunction with the first aspect, in certain implementations of the first aspect, performing a total dose radiation experiment on the M groups of resistive random access memories includes:

[0031] Perform S total dose radiation level experiments on the target group of resistive random access memories;

[0032] Count the S radiation high resistance R' of the target group resistive memory h , S radiation low resistance R' l ;

[0033] Count the S radiation high resistance R' h , the S radiation low resistance R' l and the relationship between the S total dose radiation levels;

[0034] Under the same total dose radiation level, according to the M initial resistance states, M radiation high resistances R' of the M groups of resistive random access memories are determined. h , M radiation low resistance R'l The amount of change.

[0035] This allows statistical analysis of the total radiation dose test results, including the relationship between at least two of the total radiation dose level, the initial resistance state, and the radiation resistance state. Furthermore, if an abnormal radiation resistance state is observed, RRAMs that do not meet test requirements can be promptly removed. The total radiation dose test results can also reflect the maximum total radiation dose level that the RRAM can withstand at one time.

[0036] In conjunction with the first aspect, in certain implementations of the first aspect, performing a cycle endurance test on the M groups of resistive random access memories includes:

[0037] Perform multiple cycle endurance experiments on the target resistive random access memory;

[0038] Count the S high-resistance R” corresponding to the S total radiation dose levels of each group of resistive random access memory h and S tolerant low resistance R" l ;

[0039] The results of the multiple cycle tolerance experiments are statistically analyzed, including the relationship between at least two of the number of cycles, the total radiation dose level, and the resistance state.

[0040] Tolerance to high resistance R" h It is the high resistance after the tolerance test. The tolerance low resistance R" h The low resistance after the endurance test. The results of the cyclic endurance test can reflect the relationship between various elements, providing more information for technicians to rationally select and design resistive random access memory and its application scenarios.

[0041] In combination with the first aspect, in some implementations of the first aspect, the resistance state is an initial resistance state, a radiation resistance state, or a tolerance resistance state.

[0042] In conjunction with the first aspect, in certain implementations of the first aspect, the cth cyclic tolerance experiment in the multiple cyclic tolerance experiments includes:

[0043] Apply a write pulse amplitude V to the target resistive memory setm , pulse width P setm , write gate voltage pulse amplitude V gsetm , pulse width P gsetm Write operation;

[0044] Apply a read pulse amplitude V to the target resistive memory R , pulse width P R , read the gate voltage pulse amplitude V gR , pulse width P gR Read operation;

[0045] record the current target resistive random access memory resistance as R" lmc ;

[0046] apply a reset pulse amplitude V rem , pulse width P rem , and reset gate voltage pulse amplitude V grem , pulse width P grem to the target resistive random access memory;

[0047] apply a read pulse amplitude V R , pulse width P R , read gate voltage pulse amplitude V gR , pulse width P gR to the target resistive random access memory;

[0048] record the current resistive random access memory resistance as R" hmc .

[0049] With reference to the first aspect, in some implementations of the first aspect, the stopping condition of the cycle endurance experiment comprises:

[0050] when the low resistance read out by B cycle tests all satisfy R" lmc ≤R lm *(1-δ L %) or R" lmc ≥R lm *(1+δ L %), or the high resistance read out by B cycle tests all satisfy R" hmc ≤R hm *(1-δ H %) or R" hmc ≥R hm *(1+δ H %), it is determined that the resistive random access memory cycle endurance fails, and the test is stopped.

[0051] With reference to the first aspect, in some implementations of the first aspect, the method further comprises:

[0052] according to the window of the target group of resistive random access memories in the M groups of resistive random access memories, dividing the target group of resistive random access memories into P groups of resistive random access memory subgroups, the P groups of resistive random access memory subgroups respectively corresponding to P intermediate resistive states in the window;

[0053] performing a total dose radiation experiment on the P groups of resistive random access memory subgroups;

[0054] performing a cycle endurance experiment on the P groups of resistive random access memory subgroups, the result of the cycle endurance experiment being used to indicate a test result of the resistive random access memory related to total dose radiation.

[0055] By using the above method, the intermediate resistance state of the resistive random access memory can be debugged and optimized.

[0056] In combination with the first aspect, in some implementations of the first aspect, the test result of the resistive random access memory related to the total radiation dose includes: the resistive random access memory can preset an available intermediate resistance state under a total radiation dose environment.

[0057] Based on the test results, technicians can reasonably select and debug the resistive random access memory so that the intermediate resistance state of the resistive random access memory meets the use requirements. In one possible scenario, technicians intend to apply a certain resistive random access memory to a spacecraft. The total radiation dose environment that a spacecraft may be subjected to can be obtained through simulation, experimentation, and the like. Through the solution provided in the embodiment of the present application, the intermediate resistance state of the resistive random access memory can be optimized so that the resistive random access memory has advantages such as relatively optimized resistance state and relatively good tolerance performance.

[0058] In conjunction with the first aspect, in some implementations of the first aspect, the method further includes:

[0059] After the total dose irradiation, a high temperature annealing treatment is introduced. The high temperature annealing condition is 100° C.±5° C., and the annealing time is 100 to 200 hours.

[0060] This allows testing the effect of the annealing process on the parameters of the post-irradiation resistive random access memory.

[0061] In a second aspect, a method for testing total radiation dose of a resistive random access memory is provided, the method further comprising:

[0062] Grouping a plurality of resistive memory devices to obtain P groups of resistive state memories, wherein the P groups of resistive state memories correspond to the same low resistance state, the P groups of resistive state memories correspond to the same high resistance state, and the P groups of resistive state memories correspond to P intermediate resistance states respectively;

[0063] Performing a total dose radiation experiment on the P group of resistive state memories;

[0064] A cyclic tolerance test is performed on the P group of resistive memory devices, and a result of the cyclic tolerance test is used to indicate a test result of the resistive memory device related to total radiation dose.

[0065] In a third aspect, a total dose radiation testing device for a resistive random access memory is provided, which is used to perform the testing method described in any one of the implementations of the first to second aspects above. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 A schematic flowchart of a total dose radiation testing method for a resistive random access memory provided in an embodiment of the present application.

[0067] Figure 2 A schematic diagram of a resistive memory structure.

[0068] Figure 3 A schematic flowchart of grouping multiple resistive random access memories provided in an embodiment of the present application.

[0069] Figure 4 A schematic flowchart of another resistive random access memory total dose radiation testing method provided in an embodiment of the present application.

[0070] Figure 5 A schematic structural diagram of another resistive random access memory total dose radiation testing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0071] The present application is described in further detail below with reference to the accompanying drawings and specific embodiments.

[0072] Figure 1 This is a schematic flow chart of a total dose radiation testing method for a resistive random access memory provided in an embodiment of the present application.

[0073] 110, grouping the plurality of resistive memory devices to obtain M groups of resistive memory devices, where each group of resistive memory devices includes N resistive memory devices, and the M groups of resistive memory devices correspond to M initial resistance states (in this application, the initial resistance state may include a high resistance state and a low resistance state);

[0074] 120, conduct total dose radiation experiment on M groups of resistive random access memories;

[0075] 130 , performing a cyclic tolerance test on the M groups of resistive random access memories, where the results of the cyclic tolerance test are used to indicate a test result of the resistive random access memories related to the total radiation dose.

[0076] By placing the resistive random access memory in a total-dose radiation environment, subjecting the resistive random access memory to the effects of the total-dose radiation, and then conducting a cycling tolerance test on the resistive random access memory, the performance fluctuation of the resistive random access memory can be determined. In some embodiments, the test results related to the total-dose radiation of the resistive random access memory include at least one of the following: the usable resistance state range of the resistive random access memory in a preset total-dose radiation environment; the total-dose radiation environment in which the resistive random access memory can be applied; and whether the resistive random access memory is usable in the preset total-dose radiation environment.

[0077] In one possible scenario, technicians intend to apply a resistive random access memory (RRAM) to a spacecraft. The total radiation dose environment that the spacecraft may experience can be determined through simulation, experimentation, and other methods. Through the solutions provided in the embodiments of this application, the low-resistance and high-resistance states of the RRAM can be optimized, resulting in a relatively large resistance window and relatively good tolerance performance.

[0078] In one possible scenario, a technician intends to use a resistive random access memory (RRAM) in a spacecraft. However, the RRAM has different tolerance limits in different total-dose radiation environments. Using the solution provided in the embodiments of this application, the RRAM can be placed in multiple total-dose radiation environments and the tolerance of each RRAM can be verified one by one to determine the RRAM's tolerance limit.

[0079] In one possible scenario, the total radiation dose environment that a spacecraft may be subjected to can be obtained through simulation, experimentation, etc. The solution provided by the embodiments of the present application can verify whether the low-resistance state and high-resistance state of a resistive random access memory can have the required cycling tolerance performance under the known total radiation dose environment; if so, the experimental results can guide technicians in applying the resistive random access memory to a spacecraft, so that the spacecraft can be successfully designed and operated; if not, the experimental results can guide technicians in selecting other suitable resistive random access memories for application.

[0080] Figure 2 This is a schematic diagram of a resistive memory structure. Figure 2 Taking the resistive random access memory shown in the figure as an example, the solution provided by the embodiment of the present application is described. This resistive random access memory is composed of a field effect transistor T1 and a resistive random access device R1. The type of transistor in this structure can be an N-type field effect transistor or a P-type field effect transistor. The connection terminal between the transistor and the SL is defined as the first electrode, the connection terminal between the transistor and the resistive random access device is defined as the second electrode, the connection terminal between the forward operation terminal of the resistive random access device and the BL is defined as the first electrode, the connection terminal between the reverse operation terminal of the resistor and the transistor is defined as the second electrode, and the word line WL is connected to the gate of the transistor.

[0081] Resistive memory operating conditions include:

[0082] Write operation conditions: Apply write pulse amplitude V to BL terminal setm , pulse width P setm , the write gate voltage pulse amplitude V is applied to the WL end gsetm , pulse width P gsetm ;

[0083] Reset operation conditions: Apply reset pulse amplitude V to SL terminal rem , pulse width P rem , WL end resets the gate voltage pulse amplitude V grem , pulse width P grem ;

[0084] Read operation conditions: BL terminal applies a read pulse amplitude V R , pulse width P R , the read gate voltage pulse amplitude V is applied to the WL terminal gR , pulse width P gR .

[0085] Reference Figure 3 , 110Implementation can be as follows.

[0086] Set the different resistance state will be different resistance memory into M groups, each group of devices the number of N (N≥10); each group of devices target high resistance R hm , target low resistance R lm , λ L % is the maximum resistance error allowed in the low resistance state of the resistance change memory, λ H % is the maximum resistance error allowed in the high resistance state of the resistance change memory.

[0087] (1) initial state m = 1, n = 1;

[0088] (2) select the mn device, and perform read operation, record the resistance value of the resistance change memory at this time R t ;

[0089] (3) when R t ≥ (R hm + R lm ) / 2, first, the resistance change memory is subjected to the first write operation;

[0090] The first write operation process is: the selected resistance change memory device is subjected to a write pulse amplitude V setm , pulse width P setm , write gate voltage pulse amplitude V gsetm , pulse width P gsetm write operation; the resistance change memory device is subjected to a read pulse amplitude V R , pulse width P R , and read gate voltage pulse amplitude V gR , pulse width P gR read operation, record the determination times i = i + 1, i from 0 count; I is the maximum number of determinations set, in some embodiments, 1≤I≤20; when i≤I, record the resistance of the resistance change memory R mn , and perform the determination process; when i≥I, record the device failure, select a new device to start the operation of step (2);

[0091] The determination process is: when R lm *(1-λ L %)≤R mn ≤R lm *(1+λ L %), determine that the write operation is successful, record the resistance value of the resistance change memory at this time R lmn ; when R mn <R lm *(1-λ L %), a reset pulse amplitude V rem, pulse width P rem and reset gate voltage pulse amplitude V grem , pulse width P grem , and the resistance of the resistance variable device after the operation is determined again; when R mn >R lm *(1+λ L %), write pulse amplitude V setm , pulse width P setm , write gate voltage pulse amplitude V gsetm , pulse width P gsetm is applied to the resistance variable memory, and the resistance of the resistance variable device after the operation is determined again;

[0092] (4) After the first write operation is completed, the first reset operation is performed on the resistance variable memory (in this application, the first write operation + the first reset operation is referred to as a low resistance adjustment operation);

[0093] The first reset operation process is that reset pulse amplitude V rem , pulse width P rem and reset gate voltage pulse amplitude V grem , pulse width P grem are applied to the selected resistance variable device to perform a reset operation; read pulse amplitude V R , pulse width P R and read gate voltage pulse amplitude V gR , pulse width P gR are applied to the resistance variable device to perform a read operation, and the determination number i is recorded as i+1, i being counted from 0; I is the maximum number of determinations set, and in some embodiments, 1≤I≤20; when i≤I, the resistance of the resistance variable memory is recorded as R mn , and the determination process is performed; when i≥I, the device is recorded as being invalid, and a new device is selected to start the operation of step (2) again;

[0094] The determination process is that when R hm *(1-λ H %)≤R mn ≤R hm *(1+λ H %), it is determined that the reset operation is successful, and the resistance of the resistance variable memory at this time is recorded as R hmn ; when R mn ≥R hm *(1+λ H %), write pulse amplitude V setm , pulse width P setm , write gate voltage pulse amplitude V gsetm , pulse width P gsetm is applied to the resistance variable memory, and the resistance of the resistance variable device after the operation is determined again; when R mn <R hm*(1-λ H %), a reset pulse amplitude V is applied to the resistive memory rem , pulse width P rem and reset gate voltage pulse amplitude V grem , pulse width P grem The reset operation is performed and the resistance value of the resistive switching device after the operation is determined again;

[0095] (5) When R t <(R hm +R lm ) / 2, firstly, a second reset operation is performed on the resistive random access memory. The specific implementation of the second reset operation refers to the first reset operation described above;

[0096] (6) After the second reset operation is completed, a second write operation is performed on the resistive random access memory. The specific implementation of the second write operation refers to the first write operation described above (in this application, the second reset operation + the second write operation is referred to as a high resistance adjustment operation);

[0097] (7)n=n+1;

[0098] (8) When n≤N, select the mnth device and continue the screening and grouping process;

[0099] (9) When n>N, m=m+1;

[0100] (10) When m≤M, select the mnth device and continue the screening and grouping process;

[0101] (11) When m>M, the screening and grouping process ends.

[0102] In some embodiments, statistics may be collected on the following information:

[0103] a. Average low resistance value of each group of resistive switching devices

[0104] b. Low resistance standard deviation of each group of resistive switching devices

[0105] c. Average high resistance value of each group of resistive switching devices

[0106] d. High resistance standard deviation of each group of resistive switching devices

[0107] e. Average value of each group of resistive switching devices W m =R Hm -R Lm ;

[0108] f. Standard deviation of each group of resistive switching devices

[0109] 120 The specific implementation may be as follows.

[0110] S total dose level tests are performed on M groups of resistive memory devices, where S ≥ 2. The S total dose levels can refer to S test points. The highest total radiation dose level is determined by the test requirements and is not specifically required here, but a 0 rad (Si) radiation dose test is required as a control group. Each total dose level experiment can be performed on A devices in each group of resistive memory devices, where 0 ≤ A*S ≤ N. The resistive memory device must undergo a total dose radiation test under the required bias conditions.

[0111] In some embodiments, the S trial test points may be determined by:

[0112] First determine the maximum experimental test point to be verified;

[0113] Based on the maximum test point, select the starting point, the maximum radiation dose point and at least one intermediate test point; the intermediate test points can be selected by using equivalued interval points or other methods, and no special requirements are made here.

[0114] In practice, the total dose test can be conducted on each device separately, or all devices tested at the same total dose level can be tested at once. During the total dose radiation test, each time a total dose test point is reached, the devices involved in the test are tested to obtain the test data of each device; the test parameters include the (radiation) high resistance R' of the resistive random access memory. h 、(Radiation) Low resistance R' l When the test is completed within the (radiation) window W', each group of resistive random access memories can obtain S total dose levels, with a total of S*A groups of data for A devices.

[0115] Process and record the total dose experimental data;

[0116] The data processing process includes:

[0117] a. Based on the test results of the radiation experiments at different total dose levels for each group of resistive random access memory, obtain the standard deviation and mean of the test parameters;

[0118] b. Based on the test results, obtain the relationship curve between the parameter standard deviation and the parameter mean as the total radiation dose level changes;

[0119] c. Based on the test results, the relationship between the parameter standard deviation, parameter mean, initial resistance state, and window of the resistive random access memory under the same total radiation dose level is obtained.

[0120] In the specific implementation process, high-temperature annealing treatment can be introduced after the total dose irradiation to test the impact of the annealing process on the parameters of the resistive random access memory after radiation. In some specific examples, the high-temperature annealing conditions are 100°C ± 5°C and the annealing time is 100 to 200 hours.

[0121] 130 The specific implementation may be as follows.

[0122] The cyclic tolerance test of the resistive memory is carried out for M groups of different resistance windows and after S total dose radiation level tests. The cyclic tolerance test of the resistive memory is realized by applying multiple cycle tests. A single cycle test includes applying a write pulse amplitude V setm , pulse width P setm , write gate voltage pulse amplitude V gsetm , pulse width P gsetm For write operation, apply a read pulse with amplitude V R , pulse width P R , read the gate voltage pulse amplitude V gR , pulse width P gR Read operation, record the current resistance value of the resistive memory R" lmc , apply a reset pulse amplitude V rem , pulse width P rem and reset gate voltage pulse amplitude V grem , pulse width P grem For reset operation, apply a read pulse with amplitude V R , pulse width P R , read the gate voltage pulse amplitude V gR , pulse width P gR Read operation, record the current resistance value of the resistive memory R" hmc , that is, the "write-read-reset-read" process, where c is the number of single cycles currently performed.

[0123] In practice, in order to reduce the test time, the cycle tolerance test can also adopt the "write-reset-write-reset-...-write-read-reset-read" process of multiple write operations and reset operations followed by read operations. The number of cycles of write and reset operations can be set to a fixed number, such as 100 times, or can be set in a doubling manner, such as doubling every 10 times, 100 times, or 1000 times. In this cycle tolerance experiment, one "write-reset" or "write-read-reset-read" is recorded as a single cycle; the cycle tolerance test can be set to a fixed number of cycles such as 10,000 times, 100,000 times, etc. for testing, that is, a fixed number of cycle tolerance tests; the cycle tolerance test can also be set to δ L % is the maximum resistance error allowed in the low resistance state of the resistive random access memory after the cycle test, δ H% is the maximum resistance error allowed in the high-resistance state of the resistive memory after the cycle test. When the low resistance read out by (continuous) B cycle tests all meet R″ lmc ≤R lm *(1-δ L %) or R″ lmc ≥R lm *(1+δ L %), or (continuously) the high resistance read out by B cycles of testing all meets R″ hmc ≤R hm *(1-δ H %) or R″ hmc ≥R hm *(1+δ H %), the resistance switching memory cycle tolerance is judged to be failed, the test is stopped, and the total number of cycles C is recorded. mn In some embodiments, B≥10.

[0124] Based on the experimental data, the mean and standard deviation of the parameters of each group of resistive random access memory at different total radiation dose levels are obtained to determine the parameter drift of the resistive random access memory caused by the total radiation dose. The data processing process includes:

[0125] a. In a fixed number of cycle tolerance tests, based on M groups of different resistive memory cycle tolerance test data, calculate the average low resistance value R″ of each group of resistive devices (tolerance) after testing at different total dose levels. Lms , (tolerance) low resistance standard deviation σ″ Lms , (tolerance) high resistance average value R″ Hms , (tolerance) low resistance standard deviation σ″ Hms , the average value of the resistive switching device (tolerance) window W″ ms , (tolerance) window standard deviation σ″ Wms ;

[0126] b. Perform curve fitting on the mean and standard deviation of the high and low resistance values ​​and windows of each group of resistive random access memories after the same number of cycles and different total radiation doses to determine the relationship between the cyclic tolerance drift of the resistive random access memories with different resistance windows and the total radiation dose level;

[0127] c. In the cycle tolerance limit test, based on M groups of different resistive memory cycle tolerance test data, calculate the average value C of the maximum number of cycles of each group of resistive devices after testing at different total dose levels. ms ;

[0128] d. Perform curve fitting on the average value of the maximum cycle times of each group of RRAM after different total radiation doses to determine the relationship between the maximum cycle times of RRAM and the initial resistance state, window, and total radiation dose level of the RRAM.

[0129] In summary, the relationship between at least two of the number of cycles, the total radiation dose level, and the resistance state can be determined. The resistance state can refer to the initial resistance state, the radiation resistance state, or the tolerance resistance state. In one possible scenario, technicians can rationally select and debug the resistive random access memory based on the test results, ensuring that the low-resistance and high-resistance states of the resistive random access memory meet the requirements.

[0130] Furthermore, for the selected RRAM, in some scenarios, such as storage-computing integration, the RRAM also has an intermediate resistance state. The intermediate resistance state of the RRAM can be between a low resistance state and a high resistance state. Embodiments of the present application also provide a testing method for debugging and optimizing the intermediate resistance state of the RRAM.

[0131] 140 , dividing the target group of resistive state memories into P resistive state memory subgroups according to the window of the target group of resistive state memories in the M groups of resistive state memories, wherein the P resistive state memory subgroups respectively correspond to the P intermediate resistive states in the window.

[0132] The target group of resistive memories may be a group of resistive memories selected based on the results of the tolerance experiment after step 130. The target resistive memories include N resistive memories. The N resistive memories are divided into P groups of resistive memories. The P groups of resistive memories may be P subgroups of the target group of resistive memories. Each resistive memory subgroup may include Q resistive memories.

[0133] The low resistance states of the P resistive memory subgroups can be the same or substantially the same, and the high resistance states of the P resistive memory subgroups can be the same or substantially the same. The intermediate resistance states of the P resistive memory subgroups are different from each other and correspond to the P intermediate resistance states, respectively. In some embodiments, the intermediate resistance state of the resistive memory can be obtained by modulating the low resistance state through the above-mentioned high resistance modulation operation, or can be obtained by modulating the high resistance state through the above-mentioned low resistance modulation operation.

[0134] 150. Perform a total dose radiation experiment on P resistive memory subgroups.

[0135] For each of the P resistive memory subgroups, S total dose level tests are performed, where S ≥ 2. These S total dose levels can refer to S test points. The maximum total radiation dose level is determined by the test requirements and is not specifically required here, but a 0 rad (Si) radiation dose test is required as a control group. Each total dose level experiment can be performed on D devices in each resistive memory subgroup, where 0 ≤ D * S ≤ Q. The resistive memory device must undergo the total dose radiation test under the required bias conditions. The specific implementation of step 150 can refer to step 120 above.

[0136] 160 , performing a cyclic tolerance test on the P resistive memory subgroups. The results of the cyclic tolerance test are used to indicate the test results of the resistive memory related to the total radiation dose. The specific implementation of 160 can refer to the above step 130 .

[0137] In summary, the relationship between at least two of the number of cycles, the total radiation dose level, and the intermediate resistance states can be determined. In some embodiments, the test results of the resistive random access memory related to the total radiation dose include: the available intermediate resistance states of the resistive random access memory under a preset total radiation dose environment. Based on the test results, technicians can rationally select and debug the resistive random access memory to ensure that the intermediate resistance states of the resistive random access memory meet usage requirements.

[0138] In one possible scenario, a technician intends to apply a resistive random access memory (RRAM) to a spacecraft. The total radiation dose environment that the spacecraft may experience can be determined through simulation, experimentation, and other methods. Using the solutions provided in the embodiments of this application, the intermediate resistance states of the RRAM can be optimized, resulting in relatively optimized resistance states and better tolerance performance.

[0139] Figure 4 This is a schematic flow chart of a total dose radiation testing method for a resistive random access memory provided in an embodiment of the present application.

[0140] 210. Group the multiple resistive memory cells to obtain P groups of resistive memory cells. The P groups of resistive memory cells correspond to the same low resistance state, the P groups of resistive memory cells correspond to the same high resistance state, and the P groups of resistive memory cells correspond to P intermediate resistance states. The specific implementation of 210 can refer to the above 140.

[0141] 220 , performing a total dose radiation experiment on the P group of resistive memory devices. The specific implementation of 220 may refer to the above 150 .

[0142] 230 , performing a cycling tolerance test on the P group of resistive memory. The result of the cycling tolerance test is used to indicate the test result of the resistive memory related to the total radiation dose. The specific implementation of 230 can refer to the above 160 .

[0143] The present application also provides a device for testing the total dose radiation of a resistive random access memory, which is used to perform the following steps: Figure 1 or Figure 4 Test method shown.

[0144] Figure 5 This is a schematic diagram of a total dose radiation test device for resistive random access memory (RRAM). The device may include: a computer and supporting test software, an embedded control module, a test module, and a total dose radiation test board.

[0145] The computer provides a mounting platform for the matching test software and displays the test results; the embedded controller can be used to set the experiment process, dispatch the test module to perform test operation and test data acquisition according to the designed process; the test module includes an arbitrary waveform generator for generating analog test signals, a digital waveform generator for generating digital pulse test signals, high-performance analog / digital IO for inputting and outputting analog / digital signals, a high-performance data acquisition card for high-precision measurement of voltage or current, a matrix switch for selecting and controlling the opening and closing of different test paths, an oscilloscope for displaying voltage / current signal dynamic waveforms, and other necessary test structures; the embedded control module and the test module are integrated in the test case, and the outside of the case is connected by a connection port; the test case is connected with the total dose test board through a bus; the total dose test board is used to mount one or more test chips for testing.

[0146] Although the application is disclosed with the preferred embodiments as above, it is not intended to limit the application, and any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the application, therefore, the protection scope of the application should be defined by the scope of the claims of the application.

Claims

1. A method for testing total dose radiation of a resistive random access memory, characterized in that: The method comprises: Grouping the plurality of resistive memory devices to obtain M groups of resistive memory devices, each group of resistive memory devices including N resistive memory devices, and the M groups of resistive memory devices respectively corresponding to M initial resistance states; Performing a total dose radiation experiment on the M groups of resistive random access memories; Performing a cyclic tolerance test on the M groups of resistive random access memories, wherein a result of the cyclic tolerance test is used to indicate a test result of the resistive random access memory related to total radiation dose; The M groups of resistive memory correspond to M high resistance R h and M low resistance R l , the plurality of resistive switching memories are grouped to obtain M groups of resistive switching memories, including: Perform a read operation on the target resistive random access memory and obtain the resistance value of the target resistive random access memory as R mn ; When R mn ≥(R hm +R lm ) / 2, perform J times of resistance-lowering operations, each resistance-lowering operation includes a first write operation and a first reset operation. After the J times of resistance-lowering operations are successful, R lm *(1-λ L %)≤R mn ≤R lm *(1+λ L %), λ L % is the maximum resistance error allowed in the low resistance state of the target resistive random access memory, R hm The target high resistance R corresponding to the group where the target resistive memory is located hm , R lm The target low resistance R corresponding to the group where the target resistive memory is located lm ; When R mn <(R hm +R lm ) / 2, perform K high resistance adjustment operations, each high resistance adjustment operation includes a second reset operation and a second write operation, after the K high resistance adjustment operations are successful, R hm *(1-λ H %)≤R mn ≤R hm *(1+λ H %), λ H % is the maximum resistance error allowed in the high-resistance state of the target resistive random access memory; The write operation includes: Apply a write pulse amplitude V to the target resistive memory device setm , pulse width P setm , write gate voltage pulse amplitude V gsetm , pulse width P gsetm Write operation; Apply a read pulse amplitude V to the target resistive memory device R , pulse width P R , and the read gate voltage pulse amplitude V gR , pulse width P gR Read operation; The reset operation includes: Apply a reset pulse amplitude V to the target resistive memory device rem , pulse width P rem and reset gate voltage pulse amplitude V grem , pulse width P grem Reset operation; Apply a read pulse amplitude V to the target resistive memory device R , pulse width P R , and the read gate voltage pulse amplitude V gR , pulse width P gR Read operation.

2. The testing method according to claim 1, wherein: The test result of the resistive random access memory related to the total radiation dose includes at least one of the following: The available resistance state range of the resistive random access memory under a preset total dose radiation environment; A total radiation dose environment in which the resistive random access memory can be applied; Whether the resistive random access memory is usable under a preset total dose radiation environment.

3. The testing method according to claim 1 or 2, characterized in that: The total dose radiation experiment on the M groups of resistive random access memories includes: Perform S total dose radiation level experiments on the target group of resistive random access memories; Count the S radiation high resistance R' of the target group resistive memory h , S radiation low resistance R' l ; Count the S radiation high resistance R' h , the S radiation low resistance R' l and the relationship between the S total dose radiation levels; Under the same total dose radiation level, according to the M initial resistance states, M radiation high resistances R' of the M groups of resistive random access memories are determined. h 、M radiation low resistance R' l The amount of change.

4. The testing method according to claim 1 or 2, characterized in that: The performing a cycle tolerance test on the M groups of resistive random access memories includes: Perform multiple cycle endurance experiments on the target resistive random access memory; Count the S high-resistance R” corresponding to the S total radiation dose levels of each group of resistive random access memory h and S tolerant low resistance R" l ; The results of the multiple cycle tolerance experiments are statistically analyzed, including the relationship between at least two of the number of cycles, the total radiation dose level, and the resistance state.

5. The testing method according to claim 4, characterized in that: The resistance state is an initial resistance state, a radiation resistance state or a tolerance resistance state.

6. The testing method according to claim 4, wherein: The cth cycle tolerance experiment in the multiple cycle tolerance experiments includes: Apply a write pulse amplitude V to the target resistive memory setm , pulse width P setm , write gate voltage pulse amplitude V gsetm , pulse width P gsetm Write operation; Apply a read pulse amplitude V to the target resistive memory R , pulse width P R , read the gate voltage pulse amplitude V gR , pulse width P gR Read operation; Record the current target resistance value of the resistive random access memory as R″ lmc ; Apply a reset pulse amplitude V to the target resistive memory rem , pulse width P rem and reset gate voltage pulse amplitude V grem , pulse width P grem Reset operation; Apply a read pulse amplitude V to the target resistive memory R , pulse width P R , read the gate voltage pulse amplitude V gR , pulse width P gR Read operation; Record the current resistance value of the resistive memory as R″ hmc .

7. The testing method according to claim 6, characterized in that: The stopping conditions of the cyclic tolerance experiment include: When the low resistance read out by B cycle tests all meets R lmc ≤R lm *(1-δ L %) or R″ lmc ≥R lm *(1+δ L %), or the high resistance read out by B cycle tests all meet R″ hmc ≤R hm *(1-δ H %) or R″ hmc ≥R hm *(1+δ H %), the resistive random access memory cycle endurance is determined to have failed, and the test is stopped.

8. The testing method according to claim 1 or 2, characterized in that: The method further comprises: According to a window of a target group of resistive state memories in the M groups of resistive state memories, the target group of resistive state memories is divided into P resistive state memory subgroups, wherein the P resistive state memory subgroups respectively correspond to P intermediate resistive states in the window; performing a total dose radiation experiment on the P resistive memory subgroups; A cyclic tolerance test is performed on the P resistive memory subgroups, and a result of the cyclic tolerance test is used to indicate a test result of the resistive memory related to the total radiation dose.

9. The testing method according to claim 8, characterized in that: The test result of the resistive random access memory related to the total radiation dose includes: the resistive random access memory can be preset to have an available intermediate resistance state under a total radiation dose environment.

10. The testing method according to claim 1 or 2, characterized in that: The method further comprises: introducing a high-temperature annealing treatment after the total dose irradiation, wherein the high-temperature annealing condition is 100° C.±5° C. and the annealing time is 100 to 200 hours.

11. A method for testing total dose radiation of a resistive random access memory, characterized in that: The cycling endurance test of M groups of resistive random access memories was conducted, including: Perform multiple cycle endurance experiments on the target resistive random access memory; Count the S high-resistance R” corresponding to the S total radiation dose levels of each group of resistive random access memory h and S tolerant low resistance R" l ; Counting the results of the multiple cycle tolerance experiments, including the relationship between at least two of the number of cycles, the total radiation dose level, and the resistance state; The cth cycle tolerance experiment in the multiple cycle tolerance experiments includes: Apply a write pulse amplitude V to the target resistive memory setm , pulse width P setm , write gate voltage pulse amplitude V gsetm , pulse width P gsetm Write operation; Apply a read pulse amplitude V to the target resistive memory R , pulse width P R , read the gate voltage pulse amplitude V gR , pulse width P gR Read operation; Record the current target resistance value of the resistive random access memory as R″ lmc ; Apply a reset pulse amplitude V to the target resistive memory rem , pulse width P rem and reset gate voltage pulse amplitude V grem , pulse width P grem Reset operation; Apply a read pulse amplitude V to the target resistive memory R , pulse width P R , read the gate voltage pulse amplitude V gR , pulse width P gR Read operation; Record the current resistance value of the resistive memory as R″ hmc .

12. A method for testing total dose radiation of a resistive random access memory, characterized in that: The method includes: grouping a plurality of resistive memory devices to obtain P groups of resistive state memories, wherein the P groups of resistive state memories correspond to the same low resistance state, the P groups of resistive state memories correspond to the same high resistance state, and the P groups of resistive state memories respectively correspond to P intermediate resistance states; Performing a total dose radiation experiment on the P group of resistive state memories; A cyclic tolerance test is performed on the P group of resistive memory devices, and a result of the cyclic tolerance test is used to indicate a test result of the resistive memory device related to total radiation dose.

13. A test device for total dose radiation of resistive random access memory, characterized in that: Used to perform the test method according to any one of claims 1 to 12.

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