High-density interconnect backplane, package structure and method of manufacturing the same
By embedding a local silicon interposer without through-silicon vias on the redistribution layer of an organic dielectric, and combining redistribution technology with temporary bonding wafer processes, high-density and sub-high-density interconnects are achieved, reducing manufacturing difficulty and cost, and solving the problems of high manufacturing difficulty and cost of traditional silicon interposers.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 上海为旌科技有限公司
- Filing Date
- 2022-09-28
- Publication Date
- 2026-07-24
AI Technical Summary
The manufacturing of high-density interconnect adapters in existing technologies is difficult and costly, and traditional silicon adapter processes are difficult to meet the needs of high-density and sub-high-density interconnects.
A local silicon interposer without through-silicon vias is embedded in the redistribution layer of an organic dielectric. The local silicon interposer is connected to the high-density interconnect region of the wafer, and the redistribution layer of the organic dielectric is used to connect to the second-highest density region of the wafer. By combining redistribution technology and temporary bonding wafer process, high-density and second-highest density interconnects are achieved.
It reduces manufacturing difficulty and cost, increases production capacity, solves the problems of high manufacturing difficulty and high cost of high-density interconnect adapter boards, and simultaneously meets the needs of high-density and sub-high-density interconnects.
Smart Images
Figure CN115547843B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip packaging manufacturing, and further to a high-density interconnect adapter board, packaging structure and manufacturing method thereof. Background Technology
[0002] As chips evolve towards miniaturization and high performance, high-density, multi-chip packaging technologies have become crucial solutions. Adapter boards have become one of the most effective means of connecting electrical signals between nanoscale integrated circuits and millimeter-scale macroscopic substrates. An adapter board typically refers to the functional layer for interconnection and pin redistribution between a chip and a packaging substrate. Through its redistribution layer, the adapter board can redistribute dense I / O leads.
[0003] To achieve high-density interconnect packaging, existing technologies typically use a single silicon interposer with through-silicon vias (TSVs) as the connection between the upper-layer wafer and the packaging substrate. Vertical connectivity is achieved by forming TSVs within the interposer, enabling high-bandwidth communication between chips and high-density interconnection between chips and the substrate. However, manufacturing the silicon interposer layer of a single silicon process interposer with TSVs is difficult, involves high stress, and has limited production capacity, resulting in high costs.
[0004] Some technologies use redistribution layers (RDLs) made of silicon-free organic materials as the dielectric, serving as the interfacing board. The RDL can rearrange the solder pad positions on the chip, ensuring the new solder pads meet the minimum solder ball spacing requirements and are arranged in an array. However, for high I / O chip package structures, the RDL imposes significant limitations on the linewidth and spacing of high-density interconnect regions, making it difficult to fabricate ultra-high-density interconnect solutions. Summary of the Invention
[0005] To address the aforementioned technical problems, this invention provides a novel method for manufacturing a high-density interconnect adapter board. By embedding a local silicon adapter board without through-silicon vias on a redistribution layer of an organic dielectric, a novel adapter board is achieved that can interconnect both the high-density interconnect regions of a wafer and the non-high-density interconnect regions of the wafer. At the same time, the production cost of the adapter board is reduced, solving the problem of the difficulty in manufacturing high-density interconnect adapter boards.
[0006] Specifically, the present invention provides a method for manufacturing a high-density interconnect adapter board, comprising the following steps:
[0007] Multiple individual silicon interposers are transferred onto a first temporary bonding wafer;
[0008] The gaps between the different silicon adapter plates are filled with filler.
[0009] Interconnects and bonding pads are fabricated on the second temporary bonding wafer;
[0010] The side of the silicon adapter plate opposite to the first temporary bonding wafer is attached to the second temporary bonding wafer;
[0011] Remove the first temporary bonded wafer;
[0012] Create connection holes in non-silicon areas;
[0013] The required metal interconnects and layers are laid out to the position of the solder pads using rewiring technology to form a hybrid adapter board.
[0014] In some embodiments, the step of transferring multiple individual silicon interposers onto a first temporary bonding wafer includes:
[0015] The individual silicon interposers are transferred to the first temporary bonding wafer according to the pitch on the high-density interconnect interposer that matches the hybrid interposer.
[0016] In some embodiments, after the step of removing the first temporary bonding wafer, the method further includes the step of:
[0017] The back of the silicon adapter is ground to a thinner thickness to the required thickness.
[0018] In some embodiments, the step of forming the hybrid adapter plate is further included:
[0019] The hybrid adapter board is directly diced on the second temporary bonding wafer, or
[0020] The hybrid adapter board is transferred to a conventional wafer film for conventional dicing.
[0021] According to another aspect of the present invention, a high-density interconnect adapter board is further provided, which can be manufactured using any of the above-described methods for manufacturing high-density interconnect adapter boards, comprising:
[0022] Redistribution layer for organic media;
[0023] A silicon adapter board without through-silicon vias, wherein the silicon adapter board is embedded in the redistribution layer and the silicon adapter board is provided with high-density interconnect lines.
[0024] In some embodiments, solder pads are welded to both the upper and lower surfaces of the high-density interconnect adapter board.
[0025] According to another aspect of the present invention, a method for fabricating a high-density interconnect packaging structure is further provided, comprising the following steps:
[0026] Cut the wafers that need to be connected into individual pieces;
[0027] The wafer is soldered onto an uncut hybrid adapter board using a high-precision soldering machine;
[0028] The hybrid adapter board with the attached wafers is transferred to the third temporary bonding wafer;
[0029] Remove the second temporary bonded wafer;
[0030] The required bumps on the bottom layer of the hybrid adapter plate;
[0031] The combined wafer is cut into individual pieces and transferred onto a wafer substrate;
[0032] Mounting and packaging substrate.
[0033] According to another aspect of the present invention, a packaged interconnect structure is further provided, comprising the high-density interconnect adapter board mentioned in any of the above, and further comprising:
[0034] Chips and packaging substrates;
[0035] The wafer is mounted on the high-density interconnect adapter board, and the high-density interconnect adapter board is mounted on the package substrate;
[0036] The wafer and the high-density interconnect adapter board, as well as the high-density interconnect adapter board and the packaging substrate, are connected by bumps.
[0037] The encapsulation substrate is connected to encapsulation solder balls.
[0038] In some embodiments, the bump includes a first bump and a second bump, the first bump being smaller than the second bump, the high-density region of the wafer being interconnected with the high-density interconnect adapter via the first bump, and the non-high-density region of the wafer being interconnected with the adapter via the second bump.
[0039] Compared with the prior art, the present invention has at least one of the following beneficial effects:
[0040] 1. This invention embeds a partial silicon adapter plate without through-silicon vias (TSVs) on a redistribution layer of an organic dielectric. The partial silicon adapter plate is connected to the high-density interconnect region of the wafer, and the redistribution layer of the organic dielectric is used to connect to this high-density region of the wafer. This enables interconnection of both high-density interconnect packages and second-highest-density interconnect packages. This solves the problems of limited manufacturing process, small design space, and difficult packaging and soldering when the partial silicon adapter plate without TSVs for high-density interconnects is independent of the packaging substrate.
[0041] 2. The partial silicon interposer without silicon vias of the present invention is independent of the packaging substrate and is not embedded in the packaging substrate. It only interconnects the high-density interconnection area of the chip. The interconnection between the chip and the packaging substrate is achieved through the redistribution layer of organic dielectric. This solves the problem that when the partial silicon interposer without silicon vias is connected to the packaging substrate, the requirements of the packaging substrate are high, which makes this type of interposer unsuitable for most packaging substrates on the market.
[0042] 3. This invention employs a simple and low-cost redistribution layer that is integrated with a local silicon interposer without through-silicon vias (TSVs). The local silicon interposer is fabricated by creating high-density interconnect lines on a silicon substrate. Then, temporary bonding wafers and redistribution and filler processes are used to integrate the local silicon interposer with the organic dielectric redistribution layer. This reduces manufacturing difficulty, lowers manufacturing costs, and increases production capacity. It solves the problems of high technical requirements for interconnection between wafers and substrates, as well as the high manufacturing difficulty and cost of traditional interposers used for high-density interconnection due to the need for TSV processes. In addition, it also solves the problem that low-cost organic dielectric redistribution layers are difficult to use for high-density interconnection.
[0043] 4. This invention combines the low cost of partial silicon interposers with the sustainable evolution of non-high-density components, simplifying the process flow. Attached Figure Description
[0044] The preferred embodiments will now be described in a clear and easy-to-understand manner, in conjunction with the accompanying drawings, to further explain the above-mentioned characteristics, technical features, advantages, and implementation methods of the present invention.
[0045] Figure 1 This is a flowchart of the manufacturing method of the high-density interconnect adapter board of the present invention;
[0046] Figure 2 This is a schematic diagram of the longitudinal section structure of the adapter plate of the present invention;
[0047] Figure 3 This is a flowchart of the manufacturing method of the high-density interconnect adapter board of the present invention;
[0048] Figure 4 This is a longitudinal cross-sectional view of the packaging interconnect structure of the present invention.
[0049] Explanation of icon numbers:
[0050] Packaging substrate 1, package body solder balls 11
[0051] Hybrid adapter board 2, redistribution layer 21, metal interconnect 22, local silicon adapter board 23, bump 24,
[0052] First protrusion 33, second protrusion 34,
[0053] Chip 4. Detailed Implementation
[0054] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.
[0055] To keep the drawings concise, each figure only schematically shows the parts relevant to the invention, and these do not represent the actual structure of the product. Furthermore, to facilitate understanding, in some figures, only one of components with the same structure or function is schematically depicted, or only one is labeled. In this document, "one" not only means "only one," but can also mean "more than one."
[0056] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.
[0057] In this document, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0058] Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0059] In one embodiment, refer to the appendix to the specification. Figure 1 This invention provides a method for manufacturing a high-density interconnect adapter board, comprising the following steps:
[0060] Transfer a single silicon interposer onto the first temporary bonding wafer;
[0061] Use filler to fill the gaps between different silicon adapter boards;
[0062] Interconnects and bonding pads are fabricated on the second temporary bonding wafer;
[0063] The side of the silicon interposer that is opposite to the first temporary bonding wafer is attached to the second temporary bonding wafer;
[0064] Remove the first temporary bonded wafer;
[0065] Create connection holes in non-silicon areas;
[0066] The required metal interconnects and layers are extended to the solder pads using rewiring technology.
[0067] For the fabrication of a single silicon interposer, various methods can be employed, including using a damascus process to create fine copper lines on the interposer, using traditional etching processes to create silicon-based dielectric metal interconnects, or using organic dielectrics and redistribution techniques to create metal interconnects on the silicon substrate. The silicon interposer is then cut into individual pieces at its original thickness. The fabrication of the interconnect lines can be based on the interconnection relationships of high-density interconnect regions between wafers.
[0068] In a preferred embodiment, transferring a single silicon interposer onto a first temporary bonding wafer further includes transferring the silicon interposers cut into individual pieces onto the first temporary bonding wafer according to the pitch designed on the high-density interconnect interposer.
[0069] In the step of filling the gap between different silicon interposers using fillers, materials such as polyimide, underfill, and molding compound can be used to fill the gap between the two interposers. The fillers mentioned above can not only fill the gap between the interposers, but also serve as an organic medium for the redistribution layer, enabling the redistribution layer and the local silicon interposer to bond more tightly, thus achieving the interlocking of the redistribution layer 21 and the local silicon interposer.
[0070] After removing the first temporary bonding wafer, the back of the silicon interposer can be ground to the required thickness to facilitate further modification of the silicon interposer surface, welding of bonding pads and other structures, and connection with the microbumps to be connected.
[0071] In the dicing step, dicing can be performed directly on the second temporary bonding wafer, or the hybrid adapter board formed above can be transferred to a conventional wafer substrate for dicing, thereby forming the final adapter board with high-density interconnect functionality. Afterwards, the high-density interconnect adapter board can be tested, and once testing is complete, it can be supplied for packaging.
[0072] According to another aspect of the invention, reference is made to the appended specification. Figure 2Furthermore, a high-density interconnect adapter board is provided, including a silicon adapter board and an organic dielectric redistribution layer 21, wherein the silicon adapter board is embedded on the organic dielectric redistribution layer 21, and the silicon adapter board is provided with metal interconnect lines 22 for interconnecting with the high-density interconnection area of the wafer 4. The redistribution layer 21 can interconnect with the previous high-density interconnection area of the wafer 4, realizing a novel adapter board that can simultaneously interconnect both the high-density interconnection area on the wafer 4 and the previous high-density interconnection area on the wafer 4.
[0073] In a preferred embodiment, refer to the appendix to the specification. Figure 4 The high-density interconnect board has solder pads on both the top and bottom layers. The solder pads on the top layer can be soldered to the connection points of the chip 4, such as bumps or solder pads. The solder pads on the bottom layer can be soldered to metal bumps 24 made of any material, and then soldered to the packaging substrate 1 through the metal bumps 24.
[0074] According to another aspect of the invention, reference is made to the appended specification. Figure 3 Furthermore, a method for fabricating a high-density packaged interconnect structure is provided, which mainly includes the following steps:
[0075] Cut the wafers that need to be connected into individual pieces;
[0076] On any of the above hybrid adapter boards, the wafers are soldered to the uncut hybrid adapter board using a high-precision soldering machine;
[0077] The hybrid adapter board with the attached wafers is transferred to the third temporary bonding wafer;
[0078] Remove the second temporary bonded wafer;
[0079] The required bumps on the bottom layer of the hybrid adapter plate;
[0080] The combined wafer is cut into individual pieces and transferred onto a wafer substrate;
[0081] Mounting and packaging substrate.
[0082] After the wafers are soldered onto the uncut hybrid adapter board using a high-precision soldering machine, fillers such as molding compound or underfill can be used to fill the gaps between the wafers. These fillers can both provide some fixation for the wafers and, if made of materials with good thermal conductivity, improve the heat dissipation performance of the packaging material.
[0083] In the bumping process required on the bottom layer of the hybrid adapter board, the bumps can be made using the traditional bumping process. The required bumps can be solder balls or copper blocks.
[0084] According to another aspect of the invention, reference is made to the appended specification. Figure 4Furthermore, a high-density interconnect packaging structure is provided, including a high-density interconnect adapter board, a chip 4, and a packaging substrate 1. The high-density interconnect adapter board includes a local silicon adapter board 23 without through-silicon vias (TSVs) and a redistribution layer 21 of organic dielectric. The local silicon adapter board 23 has embedded metal interconnects 22, which can interconnect the high-density interconnect areas of different chips. Signals can be transmitted from the chip to the local silicon adapter board 23 and then to another chip, realizing interconnection between different chips.
[0085] The local silicon interconnect 23 without through-silicon vias is embedded in the redistribution layer 21 of the organic dielectric, independent of the packaging substrate 1 and not embedded in the packaging substrate 1. It only interconnects the high-density interconnection area of the wafer 4. The interconnection between the wafer 4 and the packaging substrate 1 is achieved through the redistribution layer 21 of the organic dielectric.
[0086] In a preferred embodiment, bumps 24 are installed between the redistribution layer 21 of the organic dielectric and the packaging substrate 1. The bumps 24 are installed at the positions of the solder pads of the redistribution layer 21 to achieve interconnection between the redistribution layer 21 of the organic dielectric and the packaging substrate 1. Package solder balls 11 are mounted on the packaging substrate 1 for interconnection with other devices or signal transmission.
[0087] In a preferred embodiment, a first bump 33 is installed between the wafer 4 and the local silicon interposer 23, and a second bump 34 is installed between the wafer 4 and the redistribution layer 21. Both the first bump 33 and the second bump 34 are connected to the solder pads on the high-density interconnect interposer. The size of the first bump is smaller than that of the second bump to accommodate different packaging densities.
[0088] In summary, this invention provides a high-density interconnect adapter board, a manufacturing method thereof, and its application. By embedding a local silicon adapter board 23 capable of achieving high-density interconnection outside the redistribution layer 21 of an organic dielectric, it solves the problems of high manufacturing difficulty and high cost of traditional silicon adapter boards with through-silicon vias used for high-density interconnection. This invention achieves a low-cost and simple manufacturing method for a high-density interconnect adapter board, reducing the difficulty of chip packaging manufacturing and demonstrating significant progress.
[0089] It should be noted that the above embodiments can be freely combined as needed. The above are merely preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A method for manufacturing a high-density interconnect adapter board, characterized in that, Includes the following steps: Multiple individual silicon interposers are transferred onto a first temporary bonding wafer; The gaps between the different silicon adapter plates are filled with filler. Interconnects and bonding pads are fabricated on the second temporary bonding wafer; The side of the silicon adapter plate opposite to the first temporary bonding wafer is attached to the second temporary bonding wafer; Remove the first temporary bonded wafer; Create connection holes in non-silicon areas; The required metal interconnects and layers are laid out to the position of the solder pads using rewiring technology to form a hybrid adapter board.
2. The method for manufacturing a high-density interconnect adapter board according to claim 1, characterized in that, The step of transferring multiple individual silicon interposers onto the first temporary bonding wafer includes: The individual silicon interposers are transferred to the first temporary bonding wafer according to the pitch on the high-density interconnect interposer that matches the hybrid interposer.
3. The method for manufacturing a high-density interconnect adapter board according to claim 1, characterized in that, After the step of removing the first temporary bonded wafer, the method further includes the following step: The back of the silicon adapter is ground to a thinner thickness to the required thickness.
4. The method for manufacturing a high-density interconnect adapter board according to claim 1, characterized in that, The process after forming the hybrid adapter plate also includes the following steps: The hybrid adapter board is directly diced on the second temporary bonding wafer, or The hybrid adapter board is transferred to a conventional wafer film for conventional dicing.
5. A high-density interconnect adapter board, manufactured using the manufacturing method of a high-density interconnect adapter board as described in any one of claims 1-4, characterized in that, include: Redistribution layer for organic media; A silicon adapter board without through-silicon vias, wherein the silicon adapter board is embedded in the redistribution layer and the silicon adapter board is provided with high-density interconnect lines.
6. The high-density interconnect adapter board according to claim 5, characterized in that, The high-density interconnect adapter board has solder pads welded to both its upper and lower surfaces.
7. A method for fabricating a high-density interconnect packaging structure, characterized in that, include: Cut the wafers that need to be connected into individual pieces; The wafer is soldered to an uncut hybrid adapter board using a high-precision soldering machine. The hybrid adapter board is fabricated using the high-density interconnect adapter board fabrication method as described in any one of claims 1-4. The hybrid adapter board with the attached wafers is transferred to the third temporary bonding wafer; Remove the second temporary bonded wafer; The required bumps on the bottom layer of the hybrid adapter plate; The combined wafer is cut into individual pieces and transferred onto a wafer substrate; Mounting and packaging substrate.
8. An encapsulated interconnect structure, including the high-density interconnect adapter board as described in claim 5, characterized in that, Also includes: Chips and packaging substrates; The wafer is mounted on the high-density interconnect adapter board, and the high-density interconnect adapter board is mounted on the packaging substrate; The wafer and the high-density interconnect adapter board, as well as the high-density interconnect adapter board and the packaging substrate, are connected by bumps. The packaging substrate is connected to packaging solder balls.
9. The packaging interconnect structure according to claim 8, wherein the bump includes a first bump and a second bump, the first bump being smaller than the second bump, the high-density region of the wafer is interconnected with the high-density interconnect adapter through the first bump, and the non-high-density region of the wafer is interconnected with the adapter through the second bump.