Semiconductor element with contact points free of voids and method for producing same

Abstract

The present disclosure provides a semiconductor device without voids in a contact and a method of making the semiconductor device. The semiconductor device includes a source / drain structure disposed on a semiconductor substrate, a dielectric layer disposed on the source / drain structure, and a conductive contact through the dielectric layer and the source / drain structure. The conductive contact includes a conductive layer and a barrier layer covering a sidewall and an undersurface of the conductive layer, and wherein a first thickness of the barrier layer on the sidewall of the conductive layer is less than a second thickness of the barrier layer under the undersurface of the conductive layer.

Description

[0001] Cross-referencing

[0002] This application claims priority and benefits from U.S. Official Application No. 17 / 346,822, filed June 14, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor device and a method for fabricating the same. In particular, it relates to a semiconductor device with gapless contact points and a method for fabricating the same. Background Technology

[0004] Semiconductor components are indispensable for many modern applications. With advancements in electronic technology, semiconductor components have become increasingly smaller, while simultaneously offering superior functionality and incorporating a greater number of integrated circuits. Due to the miniaturization of semiconductor components, different forms and sizes of semiconductor components realizing different functions are integrated and packaged into a single module. Furthermore, numerous manufacturing steps are performed on the integration of various types of semiconductor devices.

[0005] However, the manufacturing and integration of these semiconductor devices involves many complex steps and operations. Integration within these semiconductor devices becomes increasingly complex. This increased complexity in the manufacturing and integration of semiconductor devices can lead to several defects. Therefore, there is a need for continuous improvement of the manufacturing processes for these semiconductor devices to address these defects and enhance their performance.

[0006] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0007] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a source / drain structure disposed on a semiconductor substrate; a dielectric layer disposed on the source / drain structure; and a conductive contact point passing through the dielectric layer and the source / drain structure. The conductive contact point includes a conductive layer and a barrier layer, the barrier layer covering a sidewall and a lower surface of the conductive layer; and wherein a first thickness of the barrier layer on the sidewall of the conductive layer is less than a second thickness of the barrier layer below the lower surface of the conductive layer.

[0008] In some embodiments, the first thickness is along a first direction, and the second thickness is along a second direction, which is perpendicular to the first direction.

[0009] In some embodiments, the conductive contact extends into the semiconductor substrate.

[0010] In some embodiments, the barrier layer comprises titanium, titanium nitride, or a combination thereof, and the conductive layer comprises tungsten.

[0011] In some embodiments, the source / drain structure includes an epitaxial layer and a silicide layer disposed on the epitaxial layer.

[0012] In some embodiments, the silicide layer comprises cobalt silicide.

[0013] In some embodiments, the semiconductor device further includes: a polysilicon stack disposed on the source / drain structure and surrounded by the dielectric layer, wherein the polysilicon stack includes a first polysilicon layer and a second polysilicon layer, the second polysilicon layer being disposed on the first polysilicon layer, the first polysilicon layer being undoped and the second polysilicon layer being doped; and a contact structure directly disposed on the polysilicon stack and surrounded by the dielectric layer.

[0014] In some embodiments, the polysilicon stack further includes: a third polysilicon layer disposed on the second polysilicon layer, wherein the third polysilicon layer is undoped; and a fourth polysilicon layer disposed on the third polysilicon layer, wherein the fourth polysilicon layer is doped.

[0015] In some embodiments, a doping concentration of the second polysilicon layer is greater than a doping concentration of the fourth polysilicon layer.

[0016] In some embodiments, the second polysilicon layer is separated from the dielectric layer by the first polysilicon layer.

[0017] In some embodiments, the second polysilicon layer is in direct contact with the dielectric layer.

[0018] In some embodiments, the contact structure includes a barrier layer and a conductive layer, the conductive layer being disposed on and surrounded by the barrier layer, wherein the barrier layer comprises titanium, titanium nitride, or a combination thereof, and the conductive layer comprises tungsten.

[0019] In some embodiments, the barrier layer has a lower portion surrounded by the polysilicon stack.

[0020] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes: forming a source / drain structure on a semiconductor substrate; forming a dielectric layer on the source / drain structure; etching the dielectric layer and the source / drain structure to form an opening; and forming a conductive contact in the opening. The step of forming the conductive contact includes: performing an anisotropic deposition process to form a barrier layer, thereby covering one sidewall and one lower surface of the opening; and after the barrier layer is formed, filling a remaining portion of the opening with a conductive layer.

[0021] In some embodiments, the anisotropic deposition process is a physical vapor deposition process.

[0022] In some embodiments, a first thickness of the barrier layer on the sidewall of the opening is less than a second thickness of the barrier layer on the lower surface of the opening, wherein the first thickness is along a first direction and the second thickness is along a second direction, and the second direction is perpendicular to the first direction.

[0023] In some embodiments, the source / drain structure includes an epitaxial layer and a silicide layer, the silicide layer being on the epitaxial layer, and the opening passing through the silicide layer and the epitaxial layer.

[0024] In some embodiments, the opening extends into the semiconductor substrate.

[0025] In some embodiments, the fabrication method further includes: etching the dielectric layer to form a recess, thereby exposing the source / drain structure; forming a polysilicon stack in the recess, wherein the step of forming the polysilicon stack includes: forming a polysilicon layer on the source / drain structure in the recess, wherein the first polysilicon layer is undoped; forming a second polysilicon layer on the first polysilicon layer in the recess, wherein the second polysilicon layer is doped; and forming a contact structure on the polysilicon stack in the recess.

[0026] In some embodiments, the step of forming the polysilicon stack further includes: forming a third polysilicon layer on the second polysilicon layer, wherein the third polysilicon layer is undoped; and forming a fourth polysilicon layer on the third polysilicon layer, wherein the fourth polysilicon layer is doped, wherein a doping concentration of the second polysilicon layer is greater than a doping concentration of the fourth polysilicon layer.

[0027] This disclosure provides some embodiments of a semiconductor device structure and its fabrication method. In some embodiments, the semiconductor device structure includes a polysilicon stack disposed on a source / drain structure and a contact structure directly disposed on the polysilicon stack. The polysilicon stack has an undoped polysilicon layer and a doped polysilicon layer disposed on the undoped polysilicon layer. By forming the polysilicon stack between the contact structure and the source / drain structure, contact resistance can be reduced, and device performance can be improved. Furthermore, in some embodiments, the semiconductor device includes a contact structure having a barrier layer and a conductive layer, the conductive layer being disposed on and surrounded by the barrier layer. The barrier layer has a first thickness on the sidewall of the conductive layer and a second thickness below the lower surface of the conductive layer. Since the first thickness is less than the second thickness, the conductive layer can be formed void-free, thereby improving device performance.

[0028] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, thereby enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0029] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0030] Figure 1 This is a cross-sectional schematic diagram illustrating semiconductor elements according to some embodiments of the present disclosure.

[0031] Figure 2 This is a cross-sectional schematic diagram illustrating semiconductor elements according to some embodiments of the present disclosure.

[0032] Figure 3 This is a cross-sectional schematic diagram illustrating semiconductor elements according to some embodiments of the present disclosure.

[0033] Figure 4 This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0034] Figure 5 This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0035] Figure 6 This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0036] Figure 7 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of an epitaxial layer, a silicide layer, and a dielectric layer on a semiconductor substrate during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0037] Figure 8 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure where multiple openings are formed during the formation of a semiconductor device to pass through the intermediate stages of the dielectric layer, the silicide layer, and the epitaxial layer.

[0038] Figure 9 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure in which a plurality of gate structures are formed in the plurality of openings during the formation of a semiconductor device to pass through the intermediate stage of the epitaxial layer, the silicide layer and the dielectric layer.

[0039] Figure 10 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure of etching the dielectric layer during the formation of a semiconductor element to form an opening in the intermediate stage between the plurality of gate structures.

[0040] Figure 11 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure during the intermediate stage of forming a first polysilicon layer and a second polysilicon layer in the opening and on the dielectric layer during the formation of a semiconductor device.

[0041] Figure 12 This is a cross-sectional schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure where the first polysilicon layer and the second polysilicon layer are etched back during the formation of a semiconductor device to form a polysilicon stack in the opening.

[0042] Figure 13 This is a cross-sectional schematic diagram illustrating an intermediate stage during the formation of a barrier layer in the opening and on the dielectric layer in some embodiments of the present disclosure.

[0043] Figure 14 This is a cross-sectional schematic diagram illustrating an intermediate stage of etching back the barrier layer during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0044] Figure 15 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure during the intermediate stages of forming a conductive layer in the opening and on the dielectric layer during the formation of a semiconductor element.

[0045] Figure 16 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure in the intermediate stage of sequentially forming an opening between the plurality of gate structures during the formation of a semiconductor element.

[0046] Figure 17 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a silicide layer and a first polysilicon layer in the opening during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0047] Figure 18 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a second polysilicon layer in the opening during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0048] Figure 19 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a third polysilicon layer in the opening during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0049] Figure 20 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a fourth polysilicon layer in the opening during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0050] Figure 21 This is a cross-sectional schematic diagram illustrating an intermediate stage during the formation of a barrier layer in the opening and on the dielectric layer in some embodiments of the present disclosure.

[0051] Figure 22 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure during the intermediate stages of forming a conductive layer in the opening and on the dielectric layer during the formation of a semiconductor element.

[0052] Figure 23 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure where multiple openings are formed during the formation of a semiconductor device to pass through the intermediate stages of the dielectric layer, the silicide layer, and the epitaxial layer.

[0053] Figure 24 This is a cross-sectional schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure where multiple barrier layers are formed during the formation of a semiconductor device to liner the multiple openings.

[0054] Explanation of reference numerals in the attached figures:

[0055] 10A: Preparation method

[0056] 10B: Preparation method

[0057] 10C: Preparation method

[0058] 100A: Semiconductor Components

[0059] 100B: Semiconductor Components

[0060] 100C: Semiconductor Components

[0061] 101: Semiconductor substrate

[0062] 103: Epitaxial layer

[0063] 103T: Upper surface

[0064] 105: Silicide layer

[0065] 105T: Upper surface

[0066] 107: Silicide layer

[0067] 109: Source / Drain Structure

[0068] 111: Source / Drain Structure

[0069] 113: Dielectric layer

[0070] 113T: Upper surface

[0071] 120: Opening

[0072] 125: Gate structure

[0073] 130: Opening

[0074] 133: First polycrystalline silicon layer

[0075] 135: Second polysilicon layer

[0076] 139: Polycrystalline silicon stacking

[0077] 141: First polycrystalline silicon layer

[0078] 143: Second polycrystalline silicon layer

[0079] 145: Third polycrystalline silicon layer

[0080] 147: Fourth polycrystalline silicon layer

[0081] 149: Polycrystalline silicon stacking

[0082] 153: Barrier Layer

[0083] 153L: lower part

[0084] 155: Conductive layer

[0085] 159: Contact point structure

[0086] 163: Barrier Layer

[0087] 163T: Upper surface

[0088] 165: Conductive layer

[0089] 165T: Top surface

[0090] 169: Contact point structure

[0091] 170: Opening

[0092] 170B: Lower surface

[0093] 170S: Sidewall

[0094] 173: Barrier Layer

[0095] 175: Conductive layer

[0096] 175B: Lower surface

[0097] 175S: Sidewall

[0098] 179: Contact Point Structure

[0099] S11: Steps

[0100] S13: Steps

[0101] S15: Steps

[0102] S17: Steps

[0103] S19: Steps

[0104] S21: Steps

[0105] S31: Steps

[0106] S33: Steps

[0107] S35: Steps

[0108] S37: Steps

[0109] S39: Steps

[0110] S41: Steps

[0111] S51: Steps

[0112] S53: Steps

[0113] S55: Steps

[0114] S57: Steps

[0115] S59: Steps

[0116] T1: First thickness

[0117] T2: Second thickness Detailed Implementation

[0118] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0119] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0120] Figure 1 This is a cross-sectional schematic diagram illustrating a semiconductor device 100A according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 100A includes a source / drain structure 109 disposed on a semiconductor substrate 101; and a dielectric layer 113 disposed on the source / drain structure 109. The source / drain structure 109 includes an epitaxial layer 103 and a silicide layer 105, wherein the silicide layer 105 is disposed on the epitaxial layer 103. In some embodiments, the epitaxial layer 103 is completely covered by the silicide layer 105, such that the epitaxial layer 103 is separated from the dielectric layer 113 by the silicide layer 109. In some embodiments, the epitaxial layer 103 comprises silicon (Si), and the silicide layer 105 comprises cobalt silicide (CoSi). x ).

[0121] Furthermore, the semiconductor device 100A also includes a plurality of gate structures 125 that penetrate the dielectric layer 113, the silicide layer 105, and the epitaxial layer 103. In some embodiments, the plurality of gate structures 125 extend into the semiconductor substrate 101. In some embodiments, the semiconductor device 100A also includes a polysilicon stack 139 disposed in the dielectric layer 113 and on the source / drain structure 109; and a contact structure 159 disposed directly on the polysilicon stack 139. In some embodiments, the polysilicon stack 139 and the contact structure 159 are surrounded by the dielectric layer 113. In some embodiments, the polysilicon stack 139 and the contact structure 159 are disposed between the plurality of gate structures 125.

[0122] The polysilicon stack 139 includes a first polysilicon layer 133 and a second polysilicon layer 135, wherein the second polysilicon layer 135 is disposed on and surrounded by the first polysilicon layer 133. In some embodiments, the second polysilicon layer 135 is separated from the dielectric layer 113 by the first polysilicon layer 133. It should be understood that, according to some embodiments, the first polysilicon layer 133 is undoped, and the second polysilicon layer 135 is doped. In some embodiments, the second polysilicon layer 135 is doped with arsenic (As), boron (B), or phosphorus (P).

[0123] Furthermore, in some embodiments, the contact structure 159 includes a barrier layer 153 and a conductive layer 155, wherein the conductive layer 155 is disposed on and surrounded by the barrier layer 153. In some embodiments, the barrier layer 153 comprises titanium (Ti), titanium nitride (TiN), or a combination thereof, while the conductive layer 155 comprises tungsten (W). In some embodiments, the conductive layer 155 is separated from the polysilicon stack 139 by the barrier layer 153. In some embodiments, the barrier layer 153 has a lower portion 153L surrounded by the polysilicon stack 139. In some embodiments, the contact structure 159 is electrically connected to the source / drain structure 109 through the polysilicon stack 139. In some embodiments, the semiconductor element 100A is part of a dynamic random access memory (DRAM).

[0124] Figure 2 This is a cross-sectional schematic diagram illustrating a semiconductor element 100B according to some embodiments of the present disclosure. Semiconductor element 100B may be similar to semiconductor element 100A, with the same element number indicating the same element, and certain details or descriptions of such same elements are not repeated.

[0125] In some embodiments, semiconductor device 100B includes a source / drain structure 111 disposed on a semiconductor substrate 101; and a dielectric layer 113 disposed on the source / drain structure 111. In some embodiments, the source / drain structure 111 includes an epitaxial layer 103 and a silicide layer 107, wherein the silicide layer 107 is disposed on the epitaxial layer 103. It should be understood that the silicide layer 111 partially covers the epitaxial layer 107, while the remaining portion of the epitaxial layer 107 not covered by the silicide layer 111 is covered by the dielectric layer 113, which is different from semiconductor device 100A. In some embodiments, the epitaxial layer 103 comprises silicon, and the silicide layer 105 comprises cobalt silicide.

[0126] Furthermore, the semiconductor device 100B also includes a plurality of gate structures 125 that penetrate the dielectric layer 113 and the epitaxial layer 103. In some embodiments, the plurality of gate structures 125 extend into the semiconductor substrate 101. In some embodiments, the semiconductor device 100B further includes a polysilicon stack 149 disposed in the dielectric layer 113 and on the silicide layer 107 of the source / drain structure 111; and a contact structure 169 disposed directly on the polysilicon stack 149. In some embodiments, the polysilicon stack 149 and the contact structure 169 are surrounded by the dielectric layer 113. In some embodiments, the polysilicon stack 149 and the contact structure 169 are disposed between the plurality of gate structures 125.

[0127] In some embodiments, the polysilicon stack 149 includes a first polysilicon layer 141; a second polysilicon layer 143 disposed on the first polysilicon layer 141; a third polysilicon layer 145 disposed on the second polysilicon layer 143; and a fourth polysilicon layer 147 disposed on the third polysilicon layer 145. In some embodiments, each of the first polysilicon layer 141, the second polysilicon layer 143, the third polysilicon layer 145, and the fourth polysilicon layer 147 directly contacts the dielectric layer 113.

[0128] It should be understood that the first polysilicon layer 141 and the third polysilicon layer 145 are undoped, while the second polysilicon layer 143 and the fourth polysilicon layer 147 are doped. In some embodiments, a doping concentration of the second polysilicon layer 143 is greater than a doping concentration of the fourth polysilicon layer 147. In some embodiments, the second polysilicon layer 143 and the fourth polysilicon layer 147 are doped with arsenic, boron, or phosphorus. In some embodiments, each of the first polysilicon layer 141, the second polysilicon layer 143, and the third polysilicon layer 145 has a concave upper surface facing the contact point structure 169. In some embodiments, the first polysilicon layer 141, the second polysilicon layer 143, and the third polysilicon layer 145 have a U-shaped or V-shaped profile.

[0129] Furthermore, in some embodiments, the contact structure 169 includes a barrier layer 163 and a conductive layer 165, wherein the conductive layer 165 is disposed on and surrounded by the barrier layer 163. In some embodiments, the barrier layer 163 comprises titanium, titanium nitride, or a combination thereof, while the conductive layer 165 comprises tungsten. In some embodiments, the conductive layer 165 is separated from the polysilicon stack 149 by the barrier layer 163. In some embodiments, the contact structure 169 is electrically connected to the source / drain structure 111 by the polysilicon stack 149. In some embodiments, the upper surface 113T of the dielectric layer 113 is higher than the upper surface 163T of the barrier layer 163 and the upper surface 165T of the conductive layer 165. Furthermore, the upper surface 163T of the barrier layer 163 is substantially coplanar with the upper surface 165T of the conductive layer 165. In some embodiments, the semiconductor element 100B is part of a dynamic random access memory (DRAM).

[0130] Figure 3 This is a cross-sectional schematic diagram illustrating a semiconductor element 100C according to some embodiments of the present disclosure. Semiconductor element 100C may be similar to semiconductor element 100A, and the same element number indicates the same element, without repeating certain details or descriptions of such same elements.

[0131] In some embodiments, the semiconductor device 100C includes a source / drain structure 109 disposed on a semiconductor substrate 101, and a dielectric layer 113 disposed on the source / drain structure 109. The source / drain structure 109 has an epitaxial layer 103 and a silicide layer 105, wherein the silicide layer 105 is disposed on the epitaxial layer 103. In some embodiments, the epitaxial layer 103 is completely covered by the silicide layer 105, such that the epitaxial layer 103 is separated from the dielectric layer 113 by the silicide layer 109. In some embodiments, the epitaxial layer 103 comprises silicon, and the silicide layer 105 comprises cobalt silicide.

[0132] Furthermore, the semiconductor device 100C also includes a plurality of contact structures 179 that penetrate the dielectric layer 113, the silicide layer 105, and the epitaxial layer 103. In some embodiments, the plurality of contact structures 179 extend into the semiconductor substrate 101. Each contact structure 179 includes a barrier layer 173 and a conductive layer 175, wherein the conductive layer 175 is disposed on and surrounded by the barrier layer 173. In some embodiments, the plurality of barrier layers 173 comprises titanium, titanium nitride, or a combination thereof, while the plurality of conductive layers 175 comprises tungsten. In some embodiments, the plurality of conductive layers 175 are separated from the dielectric layer 113, the source / drain structure 109, and the semiconductor substrate 101 by the plurality of barrier layers 173.

[0133] It should be understood that each barrier layer 173 has a first thickness T1 on each sidewall 175S of the corresponding conductive layer 175, and each barrier layer 173 has a second thickness T2 under each lower surface 175B of the corresponding conductive layer 175. In some embodiments, the fabrication technique of the plurality of barrier layers 173 includes an anisotropic deposition process to make the first thickness less than the second thickness. In some embodiments, the anisotropic deposition process for forming the plurality of barrier layers 173 includes a physical vapor deposition (PVD) process. In some embodiments, the semiconductor device 100C is part of a dynamic random access memory (DRAM).

[0134] Figure 4 This is a flowchart illustrating a method 10A for fabricating a semiconductor element (e.g., semiconductor element 100A) according to some embodiments of the present disclosure, and the fabrication method 10A includes steps S11, S13, S15, S17, S19 and S21. Figure 5 This is a flowchart illustrating a method 10B for fabricating a semiconductor element (e.g., semiconductor element 100B) according to some embodiments of the present disclosure, and the fabrication method 10B includes steps S31, S33, S35, S37, S39 and S41. Figure 6 This is a flowchart illustrating a method 10C for fabricating a semiconductor element (e.g., semiconductor element 100C) according to some embodiments of the present disclosure, and the fabrication method 10C includes steps S51, S53, S55, S57 and S59. Figure 4 Steps S11 to S21 Figure 5 Steps S31 to S41 and Figure 6 Steps S51 to S59 are described in detail with reference to the following figures.

[0135] Figures 7 to 15 This is a cross-sectional schematic diagram illustrating the intermediate stages in forming the semiconductor device 100A according to some embodiments of the present disclosure. For example... Figure 7 As shown, according to some embodiments, a source / drain structure 105, including an epitaxial layer 103 and a silicide layer 105, is formed on a semiconductor substrate 101. The various steps are described as follows: Figure 4 Step S11 in the preparation method 10A shown.

[0136] The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer. Additionally, the semiconductor substrate 101 may comprise elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP) and / or gallium arsenide phosphide (GaInAsP).

[0137] The source / drain structure 109 may be a raised (or elevated) source / drain structure formed on the semiconductor substrate 101. In some embodiments, the epitaxial layer 103 of the source / drain structure 109 comprises silicon, and the silicide layer 105 of the source / drain structure 109 comprises cobalt silicide. In some embodiments, the fabrication technique of the epitaxial layer 103 includes an epitaxial growth method, which may include metal-organic chemical vapor deposition (MOCVD), vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable processes. Furthermore, in some embodiments, the fabrication technique of the silicide layer 105 includes a process that includes depositing a metal layer, such as cobalt; and annealing the metal layer to make it react with the epitaxial layer 103 to form the silicide layer 105.

[0138] According to some embodiments, after the source / drain structure 109 is formed, a dielectric layer 113 is formed on the silicide layer 105 of the source / drain structure 109. The various steps are described in... Figure 4Step S13 of the fabrication method 10A shown. In some embodiments, the dielectric layer 113 comprises silicon oxide, silicon nitride, silicon oxynitride, a dielectric material having a low dielectric constant, or a combination thereof. The fabrication technique of the dielectric layer 113 may include a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or other suitable processes.

[0139] Next, as Figure 8 As shown, according to some embodiments, a plurality of openings 120 are formed to pass through the dielectric layer 113 and the source / drain structure 109. In some embodiments, the plurality of openings 120 extend into the upper portion of the semiconductor substrate 101, such that the lower surfaces of each of the plurality of openings 120 are disposed within the semiconductor substrate 101. The fabrication technique of the plurality of openings 120 may include an etching process, and the location of the plurality of openings 120 may be defined by a patterned mask (not shown) formed on the dielectric layer 113. The etching process may include a dry etching process, a wet etching process, or a combination thereof. The patterned mask may be removed after the etching process.

[0140] Next, as Figure 9 As shown, according to some embodiments, the plurality of gate structures 125 are formed in the plurality of openings 120. The various steps are described as follows: Figure 4 Step S15 of the fabrication method 10A shown. In some embodiments, the plurality of gate structures 125 are recessed gate structures of DRAM. Each gate structure 125 includes a gate dielectric (not shown) and a gate electrode (not shown), the gate electrode being disposed on and surrounded by the gate dielectric. Each gate dielectric may comprise silicon oxide, silicon nitride, silicon oxynitride, a dielectric material having a high dielectric constant, or a combination thereof, and each gate electrode may comprise a conductive material, such as aluminum, copper, tungsten, titanium, tantalum, or may be a multilayer structure comprising any combination of the above materials.

[0141] Furthermore, the formation of the plurality of gate structures 125 may include depositing a gate dielectric material (not shown) to clad the plurality of openings 120 (see reference). Figure 8 The process involves depositing a gate electrode material (not shown) in the remaining portions of the plurality of openings 120 and on the upper surface of the dielectric layer 113; and performing a planarization process on the gate dielectric material and the gate electrode material. The deposition process may include CVD, PVD, ALD, or other suitable processes. The planarization process may include a chemical mechanical polishing (CMP) process, an etching process, or other suitable processes.

[0142] like Figure 10As shown, according to some embodiments, after the plurality of gate structures 125 are formed, an opening 130 is formed to pass through the dielectric layer 113. In some embodiments, the opening 130 is disposed between the plurality of gate structures 125, and an upper surface 105T of the silicide layer 105 is exposed through the opening 130. The various steps are described in... Figure 4 Step S17 of the fabrication method 10A shown. The fabrication technique for the opening 130 may include an etching process, and the location of the opening 130 may be defined by a patterned mask (not shown) formed on the dielectric layer 113. The etching process may include a dry etching process, a wet etching process, or a combination thereof. The patterned mask may be removed after the etching process.

[0143] Then, as Figure 11 As shown, according to some embodiments, a first polysilicon layer 133 and a second polysilicon layer 135 are formed in the opening 130 and extend on the upper surface of the dielectric layer 113. In some embodiments, the fabrication technology of the first polysilicon layer 133 and the second polysilicon layer 135 includes a deposition process, such as a CVD process, a PVD process, an ALD process, or a combination thereof.

[0144] In some embodiments, the first polysilicon layer 133 is undoped, and the second polysilicon layer 135 is doped with arsenic, boron, or phosphorus. In some embodiments, the second polysilicon layer 135 is in-situ doped during the deposition process. In some embodiments, the second polysilicon layer 135 is not in-situ doped, but rather an implantation process is performed to dope the second polysilicon layer 135.

[0145] Next, as Figure 12 As shown, according to some embodiments, an etch-back process is performed on the first polysilicon layer 133 and the second polysilicon layer 135 to remove portions of the first polysilicon layer 133 and the second polysilicon layer 135 on the upper surface of the dielectric layer 113, and to remove portions of the first polysilicon layer 133 and the second polysilicon layer 135 occupying the upper portion of the opening 130. As shown, the plurality of remaining portions of the first polysilicon layer 133 and the second polysilicon layer 135 form a polysilicon stack 139. The etch-back process may include a dry etching process, a wet etching process, or a combination thereof. The various steps are described in... Figure 4 Step S19 in the preparation method 10A shown. Furthermore, the first polysilicon layer 133 may be etched back before the deposition process for forming the second polysilicon layer 135 is performed.

[0146] It should be understood that although only two polysilicon layers (e.g., first polysilicon layer 133 and second polysilicon layer 135) are displayed in the polysilicon stack 139, the polysilicon stack 139 may have more than two polysilicon layers. In some embodiments, the process of forming the first polysilicon layer 133 and the second polysilicon layer 136 is repeated in a cycle to form more polysilicon layers on the second polysilicon layer 135. For example, an undoped third polysilicon layer is formed on the second polysilicon layer 135, and a fourth polysilicon layer doped with arsenic, boron, or phosphorus is formed on the third polysilicon layer. In this example, the doping concentration of the second polysilicon layer 135 is greater than the doping concentration of the fourth polysilicon layer.

[0147] Next, as Figure 13 As shown, according to some embodiments, a barrier layer 153 is formed in the opening 130 and on the polysilicon stack 139, and the barrier layer 153 extends on the upper surface of the dielectric layer 113. In some embodiments, the barrier layer 153 comprises titanium, titanium nitride, or a combination thereof. Furthermore, the fabrication technique of the barrier layer 153 may include a deposition process, such as a CVD process, a PVD process, an ALD process, or a combination thereof.

[0148] Then, as Figure 14 As shown, according to some embodiments, an etching process is performed on the barrier layer 153 to remove excess portions of the barrier layer 153 on the upper surface of the dielectric layer 113. This excess portion of the barrier layer 153 can be removed by an etch-back process or a planarization process (e.g., CMP, polishing, or similar processes). In some embodiments, the lower portion 153L of the barrier layer 153 is surrounded by a second polysilicon layer 135. In some embodiments, the barrier layer 153 directly contacts the first polysilicon layer 133 and the second polysilicon layer 135.

[0149] Next, as Figure 15 As shown, the remaining portion of the opening 130 is filled with a conductive layer 155, and the conductive layer 155 extends on the upper surface of the dielectric layer 113. In some embodiments, the conductive layer 135 comprises tungsten. Furthermore, the fabrication technique of the conductive layer 155 may include a deposition process, such as a CVD process, a PVD process, an ALD process, or a combination thereof.

[0150] Next, as Figure 1 As shown, according to some embodiments, a planarization process is performed on the conductive layer 155 to remove excess portions of the conductive layer 155 on the upper surface of the dielectric layer 113. After the planarization process, a contact structure 159 including the barrier layer 153 and the conductive layer 155 is formed on the polysilicon stack 139 and surrounded by the dielectric layer 113. The various steps are described in... Figure 4 Step S21 in the preparation method 10A shown.

[0151] The planarization process may include a CMP process. After the contact structure 159 is formed, the semiconductor device 100A is obtained. Since a polysilicon stack 139 having an undoped polysilicon layer (e.g., a first polysilicon layer 133) and a doped polysilicon layer on top of the undoped polysilicon layer (e.g., a second polysilicon layer 135) is formed between the source / drain structure 109 and the contact structure 159, the contact resistance can be reduced. Therefore, the device performance of the semiconductor device 100A can be enhanced.

[0152] Figures 16 to 22 This is a cross-sectional schematic diagram, illustrating a semiconductor device 100B from a structure similar to... Figure 9 The steps shown are intermediate stages in a series of steps. As shown, one difference between semiconductor elements 100A and 100B is the location of the silicide layer. Figure 16 As shown, according to some embodiments, an epitaxial layer 103 is formed between a dielectric layer 113 and a semiconductor substrate 101, and the plurality of gate structures 125 are formed to pass through the dielectric layer 113 and the epitaxial layer 103 and extend into the upper portion of the semiconductor substrate 101. The various steps are described in... Figure 5 Steps S31 to S35 in the fabrication method 10B shown. Some materials and processes used to form the epitaxial layer 103, dielectric layer 113 and the plurality of gate structures 125 in the semiconductor device 100A are similar to or the same as those used to form the epitaxial layer 103, dielectric layer 113 and gate structures 125 in the semiconductor device 100A, and their detailed descriptions will not be repeated herein.

[0153] like Figure 16 As shown, according to some embodiments, after the plurality of gate structures 125 are formed, an opening 130 is formed to pass through the dielectric layer 113 and expose the upper surface 103T of the epitaxial layer 103. The various steps are described in... Figure 5 Step S37 in the fabrication method 10B shown. Some processes for forming the opening 130 in the semiconductor element 100B are similar to or the same as those for forming the opening 130 in the semiconductor element 100A, and their detailed descriptions will not be repeated herein.

[0154] Next, as Figure 17 As shown, according to some embodiments, a silicide layer 107 and a first polysilicon layer 141 are formed in the opening 130. In some embodiments, the silicide layer 107 includes cobalt silicide. The silicide layer 107 and the underlying epitaxial layer 103 together form the source / drain structure 111 of the semiconductor device 100B.

[0155] In some embodiments, during the formation of the first polysilicon layer 141, a silicide layer 107 is formed between the epitaxial layer 103 and the first polysilicon layer 141, and the silicide layer 107 is surrounded by a dielectric layer 113. In some embodiments, the first polysilicon layer 141 is undoped, and its fabrication technique includes a deposition process, such as a CVD process, a PVD process, an ALD process, or a combination thereof. After the deposition process, an etch-back process may be performed to remove excess portions of the first polysilicon layer 141 in the upper portion of the opening 130 and / or on the upper surface of the dielectric layer 113.

[0156] Next, as Figure 18 As shown, according to some embodiments, a second polysilicon layer 143 is formed in the opening 130 and on the first polysilicon layer 141. In some embodiments, the fabrication technique of the second polysilicon layer 143 includes a deposition process, such as a CVD process, a PVD process, an ALD process, or a combination thereof. In some embodiments, the second polysilicon layer 143 is doped with arsenic, boron, or phosphorus, and the second polysilicon layer 143 is in-situ doped during the deposition process. In some embodiments, the second polysilicon layer 143 is not in-situ doped, but rather an implantation process is performed to dope the second polysilicon layer 143. After the deposition process, an etch-back process may be performed to remove the removed portion of the second polysilicon layer 143 in the upper portion of the opening 130 and / or on the upper surface of the dielectric layer 113.

[0157] Then, as Figure 19 As shown, according to some embodiments, a third polysilicon layer 145 is formed in the opening 130 and on the second polysilicon layer 143. In some embodiments, the third polysilicon layer 145 is undoped, and its fabrication technique includes a deposition process, such as a CVD process, a PVD process, an ALD process, or a combination thereof. After the deposition process, an etching process may be performed to remove excess portions of the third polysilicon layer 145 on the upper portion of the opening 130 and / or on the upper surface of the dielectric layer 113.

[0158] Next, as Figure 20 As shown, according to some embodiments, a fourth polysilicon layer 147 is formed in the opening 130 and on the third polysilicon layer 145. In some embodiments, the fabrication technique of the fourth polysilicon layer 147 includes a deposition process, such as a CVD process, a PVD process, an ALD process, or a combination thereof. In some embodiments, the fourth polysilicon layer 147 is doped with arsenic, boron, or phosphorus, and the doping concentration of the second polysilicon layer 143 is greater than the doping concentration of the fourth polysilicon layer 147.

[0159] In some embodiments, the fourth polysilicon layer 147 is in-situ doped during the deposition process. In some embodiments, the fourth polysilicon layer 147 is not in-situ doped, but rather an implantation process is performed to dope the fourth polysilicon layer 147. After the deposition process, an etch-back process may be performed to remove excess portions of the fourth polysilicon layer 147 in the upper portion of the opening 130 and / or on the upper surface of the dielectric layer 113. After the etch-back process is performed, as shown, according to some embodiments, the excess portions of the fourth polysilicon layer 147, the third polysilicon layer 145, the second polysilicon layer 143, and the first polysilicon layer 141 form a polysilicon stack 149 occupying the lower portion of the opening 130. The various steps are described in... Figure 5 Step S39 in the fabrication method 10B shown. In some embodiments, the polysilicon stack 149 has a generally flat upper surface.

[0160] It should be understood that the polysilicon stack 149 may have more than four polysilicon layers. In some embodiments, the process of forming the third polysilicon layer 145 and the fourth polysilicon layer 147 is repeated in a cycle to form more polysilicon layers on the fourth polysilicon layer 147. For example, an undoped fifth polysilicon layer is formed on the fourth polysilicon layer 147, and a sixth polysilicon layer doped with arsenic, boron, or phosphorus is formed on the fifth polysilicon layer. In these examples, the doping concentration of the fourth polysilicon layer 147 is greater than the doping concentration of the sixth polysilicon layer, and the uppermost polysilicon layer has a generally flat upper surface.

[0161] Next, as Figure 21 As shown, according to some embodiments, a barrier layer 163 is formed in the opening 130 and on the polysilicon stack 149, and the barrier layer 163 extends on the upper surface of the dielectric layer 113. In some embodiments, the barrier layer 163 comprises titanium, titanium nitride, or a combination thereof. Furthermore, the fabrication technique of the barrier layer 163 may include a deposition process, such as a CVD process, a PVD process, an ALD process, or a combination thereof.

[0162] Then, as Figure 2 As shown, according to some embodiments, a conductive layer 165 is formed on the barrier layer 163, and the remaining portion of the opening 130 on the barrier layer 163 is filled by the conductive layer 165. In some embodiments, the conductive layer 165 comprises tungsten. Furthermore, the fabrication technique of the conductive layer 165 may include a deposition process, such as a CVD process, a PVD process, an ALD process, or a combination thereof.

[0163] Next, as Figure 2As shown, according to some embodiments, a planarization process can be performed to remove the plurality of excess portions of the barrier layer 163 and the conductive layer 165 on the upper surface of the dielectric layer 113. After the planarization process, a contact structure 169 including the barrier layer 163 and the conductive layer 165 is formed on the polysilicon stack 149 and surrounded by the dielectric layer 113. The various steps are described in... Figure 5 Step S41 in the preparation method 10B shown.

[0164] The planarization process may include a CMP process, a polishing process, an etch-back process, or similar methods. In some embodiments, after the planarization process, the upper surface 113T of the dielectric layer 113 is higher than the upper surface 163T of the barrier layer 163 and the upper surface 165T of the conductive layer 165. In some embodiments, after the planarization process, the upper surface 113T of the dielectric layer 113 is substantially coplanar with the upper surface of the barrier layer 163 and the upper surface 165T of the conductive layer 165. After the contact structure 169 is formed, the semiconductor device 100B is obtained.

[0165] Because a polysilicon stack 149 with multiple interleaved undoped polysilicon layers (e.g., the first polysilicon layer 141 and the third polysilicon layer 145) and multiple doped polysilicon layers (e.g., the second polysilicon layer 143 and the fourth polysilicon layer 147) is formed between the source / drain structure 111 and the contact structure 169, the contact resistance can be reduced. Therefore, the device performance of the semiconductor device 100B can be enhanced.

[0166] Figure 23 and Figure 24 This is a cross-sectional schematic diagram, illustrating a semiconductor device 100C from a structure similar to... Figure 7 The steps shown are intermediate stages in the sequence of steps that continue. For example... Figure 23 As shown, a source / drain structure 109, including an epitaxial layer 103 and a silicide layer 105, is formed on a semiconductor substrate 101, and a dielectric layer 113 is formed on the source / drain structure 109. The various steps are described in... Figure 6 Steps S51 and S53 in the fabrication method 10C shown. Some materials and processes used to form the epitaxial layer 103, silicide layer 105 and dielectric layer 113 in the semiconductor device 100C are similar to or the same as those used to form the epitaxial layer 103, silicide layer 105 and dielectric layer 113 in the semiconductor device 100A, and their detailed descriptions will not be repeated herein.

[0167] Please refer to the following: Figure 23 According to some embodiments, a plurality of openings 170 are formed to pass through the dielectric layer 113 and the source / drain structure 109. The various steps are described in... Figure 6Step S55 in the fabrication method 10C shown. Some processes for forming the plurality of openings 170 in semiconductor device 100C are similar to or the same as those for forming the plurality of openings 120 in semiconductor device 100A (see reference). Figure 8 The process described herein will not be repeated in detail. In some embodiments, the plurality of openings 170 extend into the upper portion of the semiconductor substrate 101.

[0168] Next, as Figure 24 As shown, according to some embodiments, an anisotropic deposition process is performed to form a plurality of barrier layers 173, thereby covering the sidewalls 170S and lower surfaces 170B of the plurality of openings 170. The various steps are described in... Figure 6 Step S57 of the preparation method 10C shown. In some embodiments, the plurality of barrier layers 173 comprises titanium, titanium nitride, or a combination thereof. In some embodiments, the anisotropic deposition process is performed to ensure that the first thickness T1 of the plurality of barrier layers 173 on each sidewall 170S of the plurality of openings 170 is less than the second thickness T2 of the plurality of barrier layers 173 on each lower surface 170B of the plurality of openings 170. In some embodiments, the anisotropic deposition process includes a physical vapor deposition (PVD) process.

[0169] Next, as Figure 3 As shown, according to some embodiments, a plurality of conductive layers 175 are formed in the plurality of redundant portions of the plurality of openings 170 on the plurality of barrier layers 173, and a plurality of contact point structures 179 including the plurality of barrier layers 173 and the plurality of conductive layers 175 are formed. The various steps are described in... Figure 6 Step S59 of the fabrication method 10C shown. In some embodiments, the plurality of conductive layers 175 comprise tungsten. Furthermore, the fabrication technique for the plurality of conductive layers 175 may include a deposition process and a subsequent planarization process. After the plurality of contact point structures 179 are formed, a semiconductor device 100C is obtained.

[0170] Since the first thickness of the plurality of barrier layers 173 is less than the second thickness T2 of the plurality of barrier layers 173, the plurality of barrier layers 173 can avoid hanging over the upper corners of the plurality of openings 170. Therefore, the device performance of the semiconductor device 100C can be enhanced.

[0171] This disclosure provides several embodiments of semiconductor devices 100A, 100B, 100C and methods for fabricating the same. In some embodiments, each semiconductor device 100A, 100B includes a polysilicon stack (e.g., polysilicon stacks 139, 149) disposed on a source / drain structure (e.g., source / drain structures 109, 111); and a contact point (e.g., contact point structures 159, 169) directly disposed on the polysilicon stack. The polysilicon stack includes an undoped polysilicon layer (e.g., polysilicon layers 133, 141, 145) and a doped polysilicon layer (e.g., polysilicon layers 135, 143, 147), the doped polysilicon layer being disposed on the undoped polysilicon layer. By forming a polysilicon stack between the contact point structure and the source / drain structure, contact resistance can be reduced, thereby improving device performance.

[0172] In some embodiments, the semiconductor device 100C includes a contact structure (e.g., contact structure 179) having a barrier layer (e.g., barrier layer 173) and a conductive layer (e.g., conductive layer 175), wherein the conductive layer is disposed on and surrounded by the barrier layer. The barrier layer has a first thickness on the sidewall of the conductive layer and a second thickness below the lower surface of the conductive layer. Because the first thickness is less than the second thickness, the conductive layer can be formed without pores, thereby improving device performance.

[0173] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a source / drain structure disposed on a semiconductor substrate; and a dielectric layer disposed on the source / drain structure. The semiconductor device also includes a polysilicon stack disposed on the source / drain structure and surrounded by the dielectric layer. The polysilicon stack includes a first polysilicon layer and a second polysilicon layer, the second polysilicon layer being disposed on the first polysilicon layer. The first polysilicon layer is undoped, and the second polysilicon layer is doped. The semiconductor device also includes a contact structure directly disposed on the polysilicon stack and surrounded by the dielectric layer.

[0174] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a source / drain structure disposed on a semiconductor substrate; and a dielectric layer disposed on the source / drain structure. The semiconductor device also includes a conductive contact point passing through the dielectric layer and the source / drain structure. The conductive contact point includes a conductive layer and a barrier layer, the barrier layer covering a sidewall and a lower surface of the conductive layer. A first thickness of the barrier layer on the sidewall of the conductive layer is less than a second thickness of the barrier layer below the lower surface of the conductive layer.

[0175] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming an epitaxial layer on a semiconductor substrate; and forming a dielectric layer on the epitaxial layer. The method also includes etching the dielectric layer to form an opening; and forming a polysilicon stack in the opening, wherein forming the polysilicon stack includes forming a first polysilicon layer; and forming a second polysilicon layer on the first polysilicon layer. The first polysilicon layer is undoped, and the second polysilicon layer is doped. The method further includes forming a contact structure in the opening and on the polysilicon stack.

[0176] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a source / drain structure on a semiconductor substrate; and forming a dielectric layer on the source / drain structure. The method also includes etching the dielectric layer and the source / drain structure to form an opening; and forming a conductive contact in the opening. The step of forming the conductive contact includes performing an anisotropic deposition process to form a barrier layer, thereby covering one sidewall and one lower surface of the opening; and after the barrier layer is formed, filling a remaining portion of the opening with a conductive layer.

[0177] The various embodiments disclosed herein have several advantageous features. In some embodiments, by forming a polysilicon stack between the source / drain structure and the contact structure, contact resistance can be reduced and device performance can be improved. In some embodiments, by forming a conductive contact with a barrier layer of different thicknesses, a conductive layer formed on the barrier layer can be non-porous and device performance can be enhanced.

[0178] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0179] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: A source / drain structure is disposed on a semiconductor substrate; A dielectric layer is disposed on the source / drain structure; as well as A conductive contact point passes through the dielectric layer and the source / drain structure, wherein the conductive contact point includes a conductive layer and a barrier layer, and the barrier layer covers one sidewall and one lower surface of the conductive layer. A polysilicon stack is disposed on the source / drain structure and surrounded by the dielectric layer, wherein the polysilicon stack includes a first polysilicon layer and a second polysilicon layer, the second polysilicon layer being disposed on the first polysilicon layer, the first polysilicon layer being undoped, and the second polysilicon layer being doped; and A contact point structure is directly disposed on the polysilicon stack and surrounded by the dielectric layer; The first thickness of the barrier layer on the sidewall of the conductive layer is less than the second thickness of the barrier layer below the lower surface of the conductive layer. The polycrystalline silicon stack also includes: A third polysilicon layer is disposed on the second polysilicon layer, wherein the third polysilicon layer is undoped; and A fourth polysilicon layer is disposed on the third polysilicon layer, wherein the fourth polysilicon layer is doped. The doping concentration of the second polysilicon layer is greater than that of the fourth polysilicon layer.

2. The semiconductor element of claim 1, wherein the first thickness is along a first direction and the second thickness is along a second direction, the second direction being perpendicular to the first direction.

3. The semiconductor element of claim 1, wherein the conductive contact extends into the semiconductor substrate.

4. The semiconductor device of claim 1, wherein the barrier layer comprises titanium, titanium nitride, or a combination thereof, and the conductive layer comprises tungsten.

5. The semiconductor device of claim 1, wherein the source / drain structure includes an epitaxial layer and a silicide layer, the silicide layer being disposed on the epitaxial layer.

6. The semiconductor device of claim 5, wherein the silicide layer comprises cobalt silicide.

7. The semiconductor device of claim 1, wherein the second polysilicon layer is separated from the dielectric layer by the first polysilicon layer.

8. The semiconductor device of claim 1, wherein the second polysilicon layer is in direct contact with the dielectric layer.

9. The semiconductor device of claim 1, wherein the contact structure includes a barrier layer and a conductive layer, the conductive layer being disposed on and surrounded by the barrier layer, wherein the barrier layer comprises titanium, titanium nitride, or a combination thereof, and the conductive layer comprises tungsten.

10. The semiconductor device of claim 1, wherein the barrier layer has a lower portion surrounded by the polysilicon stack.

11. A method for fabricating a semiconductor device, comprising: A source / drain structure is formed on a semiconductor substrate; A dielectric layer is formed on the source / drain structure; Etch the dielectric layer and the source / drain structure to form an opening; as well as A conductive contact point is formed in the opening, wherein the step of forming the conductive contact point includes: An anisotropic deposition process is performed to form a barrier layer, which then covers one sidewall and the lower surface of the opening. After the barrier layer is formed, a conductive layer is used to fill the remaining portion of the opening; The dielectric layer is etched to form a recess, thereby exposing the source / drain structure; and A polysilicon stack is formed in the recess, wherein the step of forming the polysilicon stack includes: A first polysilicon layer is formed on the source / drain structure in the recess, wherein the first polysilicon layer is undoped; A second polysilicon layer is formed on the first polysilicon layer in the recess, wherein the second polysilicon layer is doped; A contact point structure is formed on the polysilicon stack in the recess; The steps for forming the polycrystalline silicon stack also include: A third polysilicon layer is formed on the second polysilicon layer, wherein the third polysilicon layer is undoped; and A fourth polysilicon layer is formed on the third polysilicon layer, wherein the fourth polysilicon layer is doped, and the doping concentration of the second polysilicon layer is greater than the doping concentration of the fourth polysilicon layer.

12. The method for fabricating a semiconductor device as described in claim 11, wherein the anisotropic deposition process is a physical vapor deposition process.

13. The method for fabricating a semiconductor element as claimed in claim 11, wherein a first thickness of the barrier layer on the sidewall of the opening is less than a second thickness of the barrier layer on the lower surface of the opening, wherein the first thickness is along a first direction and the second thickness is along a second direction, and the second direction is perpendicular to the first direction.

14. The method for fabricating a semiconductor device as claimed in claim 11, wherein the source / drain structure includes an epitaxial layer and a silicide layer, the silicide layer being on the epitaxial layer, and the opening passing through the silicide layer and the epitaxial layer.

15. The method of fabricating a semiconductor element as claimed in claim 14, wherein the opening extends into the semiconductor substrate.

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