Method for manufacturing a semiconductor element

Abstract

A method for fabricating a semiconductor device includes forming a patterned mask layer on a surface of a semiconductor substrate. The patterned mask layer includes a plurality of sidewalls and a blanket portion, at least two adjacent sidewalls defining at least one first opening to expose a portion of the surface, and the blanket portion covering the surface of the substrate. A first patterned photoresist layer is formed on a portion of the blanket portion. A first etching process is performed to form a first trench in the semiconductor substrate, the first trench extending through the surface of the substrate and aligned with the first opening. A portion of the patterned mask layer is removed to form a second opening to expose another portion of the surface of the substrate. A second etching process is performed to form a second trench in the semiconductor substrate and to define an active region on the surface of the substrate, the first trench having a depth greater than a depth of the second trench.

Description

Technical Field

[0001] This invention relates to a method for fabricating an integrated circuit structure, and more particularly to a method for fabricating a semiconductor element. Background Technology

[0002] Typical integrated circuit (IC) structures require a sufficiently wide spacing (generally exceeding 100 micrometers) between low-voltage and high-voltage regions to withstand significant voltage drops and maintain the electronic properties of the IC structure. However, as semiconductor components in IC structures become increasingly dense, the critical dimensions of these components are becoming smaller and smaller. The presence of a wide spacing limits the scalability of IC structures.

[0003] To address this issue, existing technologies have proposed deep trench isolation structures to isolate different regions of a semiconductor substrate, thereby reducing the size of integrated circuit structures. However, in addition to the deep trench isolation structure between low-voltage and high-voltage regions, shallow trench isolation (STI) structures are also present between components within each region, making the fabrication process of integrated circuit structures significantly more complex. How to form two trench structures of different depths in a semiconductor substrate with fewer fabrication steps, thereby improving the fabrication efficiency of integrated circuit structures, has become an important topic for those with general knowledge in this field.

[0004] Therefore, there is a need to provide an advanced method for manufacturing semiconductor devices to address the problems faced by existing technologies. Summary of the Invention

[0005] One embodiment of this specification discloses a method for fabricating a semiconductor device, comprising the following steps: First, a patterned mask layer is formed on the surface of a semiconductor substrate, the patterned mask layer including a plurality of vertical walls and at least one cover portion, wherein at least two adjacent vertical walls define a first opening, exposing a portion of the semiconductor substrate surface, and the cover portion is blanketed on the surface of the semiconductor substrate. Next, a first patterned photoresist layer is formed, covering a portion of the cover portion. Then, a first etching process is performed to form at least one first trench in the substrate, penetrating the semiconductor substrate surface and aligned with the first opening. A portion of the patterned mask layer is then removed to form at least one second opening, exposing another portion of the semiconductor substrate surface. A second etching process is performed to form at least one second trench in the semiconductor substrate and define an active region on the surface of the semiconductor substrate, such that the depth of the first trench is greater than the depth of the two trenches.

[0006] According to the above embodiments, this specification provides a method for fabricating a semiconductor device. A patterned sacrificial layer with at least one mandrel unit is used to form a patterned mask layer with a three-dimensional opening structure on the surface of a semiconductor substrate. Using the patterned mask layer as an etching mask, the surface of the semiconductor substrate is etched. This is followed by another photoresist photolithography etching process. This allows the formation of two self-aligned trench structures of different depths in the semiconductor substrate and defines at least one active region on the surface of the semiconductor substrate for subsequent formation of semiconductor device units. This significantly reduces the number of fabrication steps, lowers the complexity of the fabrication process, and thus improves fabrication efficiency. Attached Figure Description

[0007] To provide a better understanding of the above and other aspects of this specification, specific embodiments are described below in conjunction with the accompanying drawings:

[0008] Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this specification; and

[0009] Figures 2A to 2L In accordance with Figure 1 The method describes a series of fabrication process structure cross-sectional views for semiconductor devices.

[0010] Symbol Explanation

[0011] 100: Semiconductor components

[0012] 101: Semiconductor substrate

[0013] 101a semiconductor substrate

[0014] 101b: Silicon oxide layer

[0015] 101s: Semiconductor substrate surface

[0016] 102: Patterned Mask Layer

[0017] 102a: Vertical wall

[0018] 102b: Covering section

[0019] 103: First Opening

[0020] 103w: Width of the first opening

[0021] 104: Patterned Sacrifice Layer

[0022] 104a: Mandrel Unit

[0023] 104s: Sidewall of the spindle unit

[0024] 104t: Top surface

[0025] 104w: Width of the spindle unit

[0026] 105: Blanket Covering

[0027] 106: Overlay

[0028] 108: First Etching Manufacturing Process

[0029] 109: First trench

[0030] 110: First patterned photoresist layer

[0031] 110a, 110b: Photoresist bumps,

[0032] 101H: High-voltage zone

[0033] 101L: Low-pressure area

[0034] 111: Deep trench isolation structure

[0035] 112: Shallow trench isolation structure

[0036] 113: Second opening

[0037] 113w: The width of the second opening

[0038] 118: Second Etching Process

[0039] 119: Second trench

[0040] 120a, 120b: Active (Powered) Region

[0041] W2: Opening width of the second groove

[0042] G: Gap

[0043] W1: Opening width of the first groove

[0044] D1: Depth of the first trench

[0045] D2: Depth of the second trench

[0046] θ: non-180° angle

[0047] S11: Provide a semiconductor substrate

[0048] S12: A patterned mask layer is formed on the surface of a semiconductor substrate, wherein the patterned mask layer includes a plurality of gaps and at least one cover portion.

[0049] S121: A patterned sacrificial layer is formed on the surface of a semiconductor substrate, giving it multiple mandrel units.

[0050] S122: Form a blanket layer conformally covering the core unit and the portion of the semiconductor substrate surface not covered by the core unit.

[0051] S123: Remove a portion of the blanket layer to expose the top of the mandrel unit.

[0052] S124: Remove the patterned sacrificial layer to form a first opening, exposing a portion of the semiconductor substrate surface to the outside.

[0053] S13: Form a first patterned photoresist layer, covering a portion of the patterned mask layer.

[0054] S14: Perform a first etching process to form at least one first trench in the semiconductor substrate, which extends through the surface of the semiconductor substrate and aligns with the first opening.

[0055] S15: Remove a portion of the patterned mask layer to form at least one second opening, exposing another portion of the semiconductor substrate surface to the outside.

[0056] S16: Perform a second etching process to form at least one second trench in the semiconductor substrate and define at least one active region on the surface of the semiconductor substrate.

[0057] S17: Form deep trench isolation structures and shallow trench structures in the first trench and the second trench respectively.

[0058] S18: Forming semiconductor element units in the active region Detailed Implementation

[0059] This specification provides a method for manufacturing a semiconductor device, which can improve the efficiency of semiconductor device manufacturing processes. To make the above-described embodiments and other objects, features, and advantages of this specification more apparent and understandable, several embodiments are described below in conjunction with the accompanying drawings.

[0060] However, it must be noted that these specific implementation examples and methods are not intended to limit the present invention. The present invention can still be implemented using other features, elements, methods, and parameters. The proposed preferred embodiments are merely illustrative of the technical features of the present invention and are not intended to limit the scope of the patent application. Those skilled in the art will be able to make equivalent modifications and variations based on the description in the following specification without departing from the spirit and scope of the present invention. In different embodiments and drawings, the same elements will be represented by the same element symbols.

[0061] Please refer to Figure 1 and Figures 2A to 2L , Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor element 100 according to one embodiment of this specification. Figures 2A to 2L It is drawn according to Figure 1 The method produces a series of fabrication process structure cross-sectional views of the semiconductor device 100.

[0062] The fabrication of semiconductor element 100 includes the following steps. First, as described in step S11: a semiconductor substrate 101 is provided. In some embodiments of this specification, the semiconductor substrate 101 may be made of, for example, silicon (Si), germanium (Ge), or a compound semiconductor material (e.g., gallium arsenide (GaAs)). However, in other embodiments, the semiconductor substrate 101 may be a silicon on insulator (SOI) substrate. In yet another embodiment of this specification, the substrate 101 is preferably a silicon wafer. In this embodiment, the semiconductor substrate 101 includes a semiconductor base layer 101a (e.g., a silicon base layer) and a pad oxide layer 101b (e.g., a silicon wafer) located on the semiconductor base layer 101a. Figure 2A shown).

[0063] Next, as described in step S12: a patterned mask layer 102 is formed on the semiconductor substrate surface 101s, such that the patterned mask layer 102 includes a plurality of vertical walls 102a and at least one cover portion 102b. At least two adjacent vertical walls 102a define at least one first opening 103, exposing a portion of the semiconductor substrate surface 101s. The cover portion 102b of the patterned mask layer 102 is blanketed on the semiconductor substrate surface 101s and forms a non-180° angle θ (e.g., 90° angle) with the vertical walls 102a connected thereto.

[0064] The formation of the patterned mask layer 102 includes the following steps: First, as described in step S121, a patterned sacrificial layer 104 is formed on the surface 101s of the semiconductor substrate 101, which has a plurality of mandrel units 104a (see [reference]). Figure 2BIn this embodiment, the patterned sacrificial layer 104 is formed by first depositing an amorphous silicon (a-Si) layer on the semiconductor substrate surface 101s using a deposition process, such as physical vapor deposition, chemical vapor deposition (CVD), sputtering, or other suitable processes; then removing a portion of the amorphous silicon layer using a dry etching process, such as reactive ion etching (RIE), leaving multiple three-dimensional amorphous silicon bumps on the semiconductor substrate surface 101s as mandrel units 104a. Each mandrel unit 104a has a substantially flat top surface 104t and a wedge-shaped, rectangular, regular, or irregular polygonal vertical cross-section.

[0065] Then, as described in step S122: a blanket layer 105 is formed, conformally covering the mandrel units 104a and a portion of the semiconductor substrate surface 101s not covered by the mandrel units 104a (e.g., ...). Figure 2C (As illustrated). In some embodiments of this specification, the blanket layer 105 may include silicon nitride. In this embodiment, because the thickness of the blanket layer 105 is less than the height of the mandrel unit 104a, it is not possible to fill the gap G between two adjacent mandrel units 104a.

[0066] Next, as described in step S123: a portion of the blanket 105 is removed to expose the top surface 104t of the mandrel unit 104a. In some embodiments of this specification, a cover layer 106 may be formed first on the blanket 105, covering the blanket 105 and completely filling the gap G between two adjacent mandrel units 104a (e.g., Figure 2D (As illustrated). In this embodiment, the cover layer 106 can be a photoresist coating.

[0067] The step of removing a portion of the blanket covering 105 may include performing an etch-back process on the blanket covering 105 to remove a portion of the blanket covering 105 located on the top surface 104t of the mandrel unit 104a, thereby exposing the top surface 104t of the mandrel unit 104a to the outside (e.g., Figure 2E shown).

[0068] However, the step of removing a portion of the blanket covering 105 is not limited to this. In other embodiments of this specification, the step of removing the portion of the blanket covering 105 includes planarizing the cover layer 106 and the blanket covering 105, for example, by a chemical mechanical polishing (CMP) process, stopping at the top surface 104t of the mandrel unit 104a.

[0069] After removing the capping layer 106, the remaining portion of the blanket layer 105 constitutes a plurality of vertical walls 102a and a plurality of covering portions 102b of the patterned mask layer 102. Each vertical wall 102a of the patterned mask layer 102 is located on at least one side wall 104s of the mandrel unit 104a. The covering portions 102b of the patterned mask layer 102 cover a portion of the semiconductor substrate surface 101s not covered by the mandrel unit 104a.

[0070] However, it is worth noting that the material and form of the pattern mask layer 102 are not limited thereto. In other embodiments, any material layer that is different from the semiconductor substrate 101, can form a three-dimensional pattern on the surface 101s of the semiconductor substrate 101, and can be removed in subsequent fabrication processes is not outside the spirit of the pattern mask layer 102 described herein.

[0071] Next, as described in step S124: the patterned sacrificial layer 104 is removed, and the space originally occupied by each mandrel unit 104a is hollowed out to form a first opening 103, exposing a portion of the semiconductor substrate surface 101s to the outside (e.g. Figure 2F shown).

[0072] Then, as described in step S13: a first patterned photoresist layer 110 is formed, covering a portion of the cover portion 102b of the patterned mask layer 102. In some embodiments of this specification, the first patterned photoresist layer 110 includes photoresist bumps 110a and 110b, respectively covering the cover portion 102b located above the high-voltage region 101H and the low-voltage region 101L (e.g., Figure 2G shown).

[0073] As described in step S14: a first etching process 108 is performed to form at least one first trench 109 in the semiconductor substrate 101, passing through the semiconductor substrate surface 101s and aligned with the first opening 103. In some embodiments of this specification, the first etching process 108 may be a dry etching process, such as a reactive ion etching process, using a combination of a patterned mask layer 102 and a first patterned photoresist layer 110 as an etching mask, removing a portion of the semiconductor substrate 101 through the first opening 103 to form the first trench 109 in the semiconductor substrate 101, dividing the semiconductor substrate surface 101s into at least a high-voltage region 101H and a low-voltage region 101L.

[0074] like Figure 2H As illustrated, each first groove 109 is aligned with a first opening 103, and the opening width W1 of the first groove 109 is substantially equal to the opening width 103w of the corresponding first opening 103. Since the first opening 103 is formed by removing the mandrel unit 104a, in other words, the opening width W1 of each first groove 109 is substantially equal to the width 104w of the mandrel unit 104a (see...). Figure 2B ).

[0075] Next, as described in step S15: a portion of the patterned mask layer 102 is removed to form at least one second opening 113 that exposes another portion of the semiconductor substrate surface 101s. Each second opening 113 is defined by at least one vertical wall 102a and the remaining cover portion 102b (covered by the first patterned photoresist layer 110).

[0076] In some embodiments of this specification, the step of removing a portion of the patterned mask layer 102 to form the second opening 113 includes using a first patterned photoresist layer 110 as an etching mask to perform a dry etching process, removing the cover portion 102b not covered by the first patterned photoresist layer 110. Simultaneously with removing a portion of the patterned mask layer 102 (cover portion 102b), a portion of the semiconductor substrate 101 is also removed through the first opening 103 to deepen the depth of the first trench 109 (e.g., ...). Figure 2I shown).

[0077] As described in step S16: a second etching process 118 is then performed to form at least one second trench 119 in the semiconductor substrate 101, aligning the second trench 119 with the second opening 113. Active regions 120a and 120b are defined on the high-voltage region 101H and low-voltage region 101L of the semiconductor substrate surface 101s, respectively, and the depth D1 of the first trench 109 is greater than the depth D2 of the second trench 119.

[0078] In some embodiments of this specification, the second etching process 118 may use a combination of the remaining patterned mask layer 102 and the first patterned photoresist layer 110 as an etching mask to perform a dry etching process, such as a reactive ion etching process. A portion of the semiconductor substrate 101 is removed through the second opening 113 to form multiple second trenches 119 in the high-voltage region 101H and the low-voltage region 101L, respectively. Simultaneously, another portion of the semiconductor substrate 101 is removed through the first opening 103, further deepening the first trenches 109.

[0079] like Figure 2J As illustrated, each second trench 119 is aligned with a second opening 113, and the opening width W2 of the second trench 119 is substantially equal to the opening width 113w of the corresponding second opening 113. Active regions 120a and 120b are aligned with the photoresist bumps 110a and 110b of the first patterned photoresist layer 110, respectively, and are surrounded by the second trenches 119.

[0080] After removing the remaining patterned mask layer 102 and the first patterned photoresist layer 110, as described in step S17: a deep trench isolation structure 111 and a shallow trench isolation structure 112 are formed respectively in the first trench 109 and the second trench 119 (e.g. Figure 2K (As illustrated). In some embodiments of this specification, the formation of the deep trench isolation structure 111 and the shallow trench isolation structure 112 includes filling the first trench 109 and the second trench 119 with a dielectric material, such as silicon oxide, silicon nitride, silicon oxycarbide, etc., and planarizing (e.g., chemical mechanical polishing) with the surface 101s of the semiconductor substrate 101 as a stop layer to remove the pad silicon oxide layer 101b and a portion of the dielectric material located above the semiconductor substrate layer 101a.

[0081] The subsequent steps are as described in step S18: logic element units 100b and high-voltage element units 100a are formed in the active regions 120a and 120b of the low-voltage region 101L and high-voltage region 101H above the semiconductor substrate layer 101a, respectively. Figure 2L (As illustrated). After a series of downstream processes, the semiconductor device 100 is fabricated.

[0082] According to the above embodiments, this specification provides a method for fabricating a semiconductor element 100. A patterned sacrificial layer 104 with at least one mandrel unit 104a is used to form a patterned mask layer 102 with a three-dimensional opening (e.g., a first opening 103) on the surface 101s of a semiconductor substrate. Using the patterned mask layer as an etching mask, the surface of the semiconductor substrate is etched 108. This is followed by another photoresist (e.g., a first patterned photoresist layer 110) photolithography etching process 118. This allows the formation of two self-aligned trench structures (e.g., the first patterned photoresist layer 110) of different depths in the semiconductor substrate 101, and defines at least one active region on the surface 101s for subsequent formation of semiconductor element units (e.g., logic element unit 100b and high-voltage element unit 100a). This significantly reduces the number of fabrication steps, lowers the complexity of the fabrication process, and thus improves fabrication efficiency.

[0083] Although the present invention has been disclosed in conjunction with the above preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: A patterned mask layer is formed on the surface of a semiconductor substrate, such that the patterned mask layer includes a plurality of vertical walls and at least one cover portion, wherein at least two adjacent members of the plurality of vertical walls define at least one first opening, exposing a portion of the surface to the outside, and the at least one cover portion is blanketed on the surface. A first patterned photoresist layer is formed and covers a portion of the at least one covered portion; Using the combination of the patterned mask layer and the first patterned photoresist layer as an etching mask, a first etching process is performed to form at least one first trench in the substrate, which passes through the surface and is aligned with the at least one first opening. A portion of the patterned mask layer is removed to form at least one second opening, exposing another portion of the surface to the outside; as well as Using the remaining patterned mask layer and the first patterned photoresist layer as an etching mask, a second etching process is performed to form at least one second trench in the substrate and define an active region on the surface, such that the at least one first trench has a depth greater than the at least one second trench.

2. The method for fabricating a semiconductor device as claimed in claim 1, wherein forming the pattern mask layer comprises: A patterned sacrificial layer is formed on this surface, having at least one mandrel unit; A blanket covering is formed, conformally covering the at least one mandrel unit and a portion of the surface not covered by the at least one mandrel unit; A portion of the blanket is removed to expose the top of the at least one mandrel unit, and the remaining portion of the blanket includes the plurality of uprights and the at least one covering portion, the plurality of uprights being located on at least one side wall of the at least one mandrel unit, and the at least one covering portion covering the surface. as well as Remove the patterned sacrifice layer.

3. The method of manufacturing a semiconductor element as claimed in claim 2, wherein the at least one mandrel unit has a width substantially equal to the opening width of the first trench.

4. The method for fabricating a semiconductor device as claimed in claim 2, wherein the patterned sacrificial layer comprises polysilicon; and the blanket layer comprises silicon nitride.

5. The method for fabricating a semiconductor device as claimed in claim 2, wherein before removing a portion of the blanket coating, the method further comprises: A covering layer is formed to cover the blanket covering layer.

6. The method for fabricating a semiconductor device as claimed in claim 5, wherein the covering layer is a photoresist coating, and the step of removing a portion of the blanket coating includes etching back the blanket coating.

7. The method of fabricating a semiconductor element as claimed in claim 5, wherein the step of removing a portion of the blanket layer includes performing a planarization process on the cover layer and the blanket layer, stopping at the top of the at least one mandrel unit.

8. The method of fabricating a semiconductor element as claimed in claim 1, wherein the at least one second opening is defined by at least one of the plurality of vertical walls and the remaining patterned mask layer, and the at least one second trench is aligned with the at least one second opening.

9. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the semiconductor substrate comprises: Semiconductor substrate; and A pad oxide layer is located on the semiconductor substrate layer, and the pad oxide layer provides the surface of the semiconductor substrate.

10. The method of manufacturing a semiconductor element as claimed in claim 1, wherein the at least one cover portion forms a non-180° angle with one of the plurality of uprights.

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