A semiconductor device

Abstract

The application provides a semiconductor device, comprising: a P-type substrate, an N-type doped epitaxial layer is arranged on the P-type substrate, a high-voltage region and a low-voltage region are arranged on the N-type doped epitaxial layer, a high-low voltage junction terminal region is arranged between the high-voltage region and the low-voltage region, a first P-type isolation column is arranged between the low-voltage region and the high-low voltage junction terminal region, a second P-type isolation column is arranged between the high-voltage region and the high-low voltage junction terminal region, the first P-type isolation column is connected with the second P-type isolation column, the first P-type isolation column and the second P-type isolation column form one or more closed regions, and a high-voltage device is arranged in the closed region. The high-voltage device is one or more of a JFET device, an LDMOS device, an LIGBT device and a power diode device. The application improves the utilization rate of the chip area, thereby reducing the cost of the integrated circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device, in particular, a power semiconductor device easy to integrate. BACKGROUND

[0002] With the rapid development of integrated circuit technology, integrated circuits are increasingly developing towards high density, high performance, high reliability and so on.

[0003] High density requires that various different circuits and devices can be integrated in an integrated circuit, and the limited area of the integrated circuit is fully utilized to realize as many functions as possible. For integrated circuits, especially analog integrated circuits, the inside of the chip is generally divided into a high-voltage region, a low-voltage region, and a high-low voltage junction terminal region separating the high-voltage region and the low-voltage region. Some more complex analog circuits, due to different working voltages of each region, the entire chip will also be divided into more voltage working regions, and appropriate isolation needs to be set between different voltage working regions.

[0004] The commonly used isolation technology suitable for the inside of a single-chip integrated chip at present includes PN junction isolation and SOI isolation technology. Among them, since the PN junction isolation technology realizes the best trade-off between cost and performance, the PN junction isolation technology is the most widely used isolation technology in power integrated circuits. However, when the PN junction isolation technology is used for higher voltage isolation, a larger area is often needed to bear high voltage, which is contrary to the development needs of high density of integrated circuits. SUMMARY

[0005] The purpose of the present application is to overcome the problem that the PN junction isolation occupies too much area and is contrary to the development needs of high density of integrated circuits in the prior art, and to provide a new type of semiconductor device. The device of the present application can fully utilize the area of the high-low voltage junction terminal region to prepare various power devices, improve the utilization rate of the chip area, and improve the density of the integrated circuit, thereby reducing the cost of the integrated circuit.

[0006] To achieve the above technical purpose, the technical scheme adopted by the present application is:

[0007] An embodiment of the present application proposes a semiconductor device, comprising: a P-type substrate, an N-type doped epitaxial layer is provided on the P-type substrate, a high-voltage region and a low-voltage region are provided on the N-type doped epitaxial layer, a high-low voltage junction terminal region is provided between the high-voltage region and the low-voltage region, a first P-type isolation column is provided between the low-voltage region and the high-low voltage junction terminal region, a second P-type isolation column is provided between the high-voltage region and the high-low voltage junction terminal region, the first P-type isolation column is connected to the second P-type isolation column, and the first P-type isolation column and the second P-type isolation column form one or more closed regions, and a high-voltage device is arranged in the closed region.

[0008] The high-voltage device is one or more of a JFET device, an LDMOS device, an LIGBT device, and a power diode device.

[0009] Embodiments of the present application also provide a method for manufacturing a semiconductor device, comprising the following steps:

[0010] Step one: select a P-type substrate material, implant boron ions through a mask window and anneal to form a P-type buried layer;

[0011] Step two: grow an N-type doped epitaxial layer on the P-type substrate, the P-type buried layer diffuses upward due to high temperature, implant P-type deep wells through a mask window by means of ion implantation and anneal;

[0012] Step three: grow a layer of silicon nitride on the silicon surface, etch out the field oxide layer region through a mask window, and grow a field oxide layer in the region not covered by the silicon nitride on the surface;

[0013] Step four: grow a gate oxide layer on the device surface and deposit gate polysilicon, etch away the excess gate oxide layer and gate polysilicon through a mask window;

[0014] Step five: implant heavily doped N-type high-concentration contacts and P-type high-concentration contacts through a mask window to form gates, sources and drains;

[0015] Step six: deposit an insulating medium layer, then selectively etch through holes in the insulating medium layer, then deposit metal and selectively etch the metal to form source metal, drain metal and gate metal;

[0016] Embodiments of the present application also provide a method for manufacturing a semiconductor device, comprising the following steps:

[0017] Step one: select a P-type substrate material, implant boron ions through a mask window and anneal to form a P-type buried layer;

[0018] Step two: grow an N-type doped epitaxial layer on the P-type substrate, the P-type buried layer diffuses upward due to high temperature, implant P-type deep wells through a mask window by means of ion implantation and anneal;

[0019] Step three: selectively etch out longitudinal trenches on the N-type doped epitaxial layer, grow an oxide layer in the longitudinal trenches, and deposit polysilicon to fill the trenches to form gate polysilicon;

[0020] Step four: grow a layer of silicon nitride on the silicon surface, etch out the field oxide layer region through a mask window, and grow a field oxide layer in the region not covered by the silicon nitride on the surface;

[0021] Step 5: Using a mask window, heavily doped N-type high-concentration contacts and P-type high-concentration contacts are implanted to form the gate, source, and drain;

[0022] Step 6: Deposit an insulating dielectric layer, then selectively etch through-holes on the insulating dielectric layer, followed by depositing and selectively etching the metal to form the source metal, drain metal, and gate metal.

[0023] In the two fabrication methods described above, in step two, during ion implantation, P-type regions and P-type deep traps are selectively implanted and then annealed.

[0024] Compared with the prior art, the main advantages of the present invention are as follows:

[0025] Integrated circuits, especially power integrated circuits, often require the integration of power devices to meet the demands of high-voltage, high-current applications. Traditional integrated circuits typically have separate low-voltage and high-voltage regions, as well as high- and low-voltage junction termination regions responsible for isolating the high- and low-voltage regions. If the voltage difference between the high- and low-voltage regions is too large, the high- and low-voltage junction termination regions may occupy a significant area to withstand the voltage. This invention fully utilizes the area of ​​the high- and low-voltage junction termination regions to fabricate various power semiconductor devices, eliminating the need for additional chip area and improving chip area utilization, thereby reducing the cost of integrated circuits. Attached Figure Description

[0026] Appendix Figure 1 This is a schematic diagram of the layout of the present invention;

[0027] Appendix Figure 2 This is a cross-sectional view along AA' of the first type of structure in the present invention where the high-voltage device is a JFET and no P-type region is provided;

[0028] Appendix Figure 3 This is a second cross-sectional view along AA' when the high-voltage device in the structure of this invention is a JFET;

[0029] Appendix Figure 4 This is a third cross-sectional view along AA' when the high-voltage device in the structure of this invention is a JFET;

[0030] Appendix Figure 5 This is a fourth cross-sectional view along AA' when the high-voltage device in the structure of this invention is a JFET;

[0031] Appendix Figure 6 This is a three-dimensional structural diagram of the fifth type along AA' when the high-voltage device in the structure of this invention is a JFET;

[0032] Appendix Figure 7 This is a three-dimensional structural diagram of the sixth type along AA' when the high-voltage device in the structure of this invention is a JFET;

[0033] Appendix Figure 8 This is a cross-sectional view along AA' when the high-voltage device in the structure of this invention is an LDMOS;

[0034] Appendix Figure 9 This is a cross-sectional view along AA' when the high-voltage device in the structure of this invention is a LIGBT;

[0035] Appendix Figure 10 This is a cross-sectional view along AA' when the high-voltage device in the structure of this invention is a power diode;

[0036] Appendix Figure 11 This is a cross-sectional view of the structure after the P-type embedded layer is injected in the manufacturing method of the present invention;

[0037] Appendix Figure 12 This is a cross-sectional view of the structure after the formation of the P-type buried layer, the P-type region, and the P-type deep well in the manufacturing method of the present invention.

[0038] Appendix Figure 13 This is a cross-sectional view of the structure after the field oxide layer is formed in the manufacturing method of the present invention;

[0039] Appendix Figure 14 This is a cross-sectional view of the gate polysilicon after it has been formed in the fabrication method of the present invention.

[0040] Appendix Figure 15 This is a cross-sectional view of the N-type high-concentration contact and the P-type high-concentration contact formed in the manufacturing method of the present invention.

[0041] Appendix Figure 16 This is a cross-sectional view of the trench gate JFET fabrication method of the present invention after the longitudinal trench is formed;

[0042] Appendix Figure 17 This is a cross-sectional view of the trench gate JFET fabrication method of the present invention after the formation of the field oxide layer;

[0043] Appendix Figure 18 This is a cross-sectional view of the trench gate JFET fabrication method of the present invention after forming N-type high-concentration contacts and P-type high-concentration contacts;

[0044] Appendix Figure 19 This is the layout structure of the present invention, which contains a single high-voltage device;

[0045] Appendix Figure 20 This is the layout structure of the present invention, which contains multiple high-voltage devices;

[0046] Explanation of reference numerals: 001 - P-type substrate; 002 - P-type buried layer; 003 - P-type region; 004 - P-type deep well; 005 - N-type high concentration contact; 006 - P-type high concentration contact; 008 - N-type doped epitaxial layer; 010 - gate oxide layer; 011 - source metal; 012 - gate polysilicon; 013 - drain metal; 014 - gate metal; 015 - emitter metal; 016 - collector metal; 017 - anode metal; 018 - cathode metal; 020 - longitudinal trench; 110 - high voltage region; 120 - high-low voltage junction termination region; 130a - first P-type isolation column; 130b - second P-type isolation column; 140 - low voltage region; I - first high voltage device; II - second high voltage device; III - third high voltage device. DETAILED DESCRIPTION

[0047] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0048] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and embodiments.

[0049] In order to make those skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work should belong to the protection scope of the present application.

[0050] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0051] The embodiments of the present application provide a semiconductor device structure, which refers to Figure 1, P-type substrate 001, N-type doped epitaxial layer 008 is arranged on the P-type substrate 001, high-voltage region 110 and low-voltage region 140 are arranged on the N-type doped epitaxial layer 008, high-low voltage junction terminal region 120 is arranged between the high-voltage region 110 and the low-voltage region 140, the first P-type isolation column 130a is arranged between the low-voltage region 140 and the high-low voltage junction terminal region 120, and the second P-type isolation column 130b is arranged between the high-voltage region 110 and the high-low voltage junction terminal region 120. The first P-type isolation column 130a and the second P-type isolation column 130b are connected, and form one or more closed areas, and a high-voltage device is arranged in each closed area.

[0052] In Figure 1 the example shown, the first P-type isolation column 130a and the second P-type isolation column 130b form three closed areas, and the first high-voltage device I, the second high-voltage device II and the third high-voltage device III are arranged in the three closed areas respectively; in Figure 19 the example shown, the first P-type isolation column 130a and the second P-type isolation column 130b form one closed area, and the first high-voltage device I is arranged in the one closed area; in Figure 20 the example shown, the first P-type isolation column 130a and the second P-type isolation column 130b form four closed areas, and the first high-voltage device I, the second high-voltage device II, the third high-voltage device III and the fourth high-voltage device IV are arranged in the four closed areas respectively;

[0053] The high-voltage devices I, II and III described above can be one of JFET, LDMOS, LIGBT or high-voltage power diode, wherein the JFET device has various structures, the high-voltage device of the embodiment can be the same type of high-voltage device, or can be different types of high-voltage devices;

[0054] The areas of different high-voltage devices can be changed according to actual needs, and the area of the closed area isolated by the P-type isolation column can be changed according to the area of the high-voltage device;

[0055] In one embodiment, as Figure 2As shown, the high-voltage device is a JFET device, including a P-type substrate 001. The first P-type isolation pillar 130a and the second P-type isolation pillar 130b each include a P-type buried layer 002 and a P-type deep well 004 arranged sequentially from bottom to top. The P-type buried layer 002 is located at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001, and the P-type buried layer 002 is led to the surface through the P-type deep well 004. The P-type deep well 004 of the first P-type isolation pillar 130a is connected to the gate metal 014 through a P-type high-concentration contact 006. The N-type doped epitaxial layer 008 region between the first P-type isolation pillar 130a and the second P-type isolation pillar 130b... The region serves as the drift region of the high-voltage device. On the side of the drift region closest to the gate metal 014, an N-type high-concentration contact 005 is provided, connected to the source metal 011. On the other side away from the gate metal 014, an N-type high-concentration contact 005 is provided, connected to the drain metal 013. A field oxide layer is provided above the N-type doped epitaxial layer 008. Above the field oxide layer, on the side closest to the source metal 011 towards the center, a gate polysilicon 012 is provided. A gate oxide layer 010 is provided between the gate polysilicon 012 and the field oxide layer. An island-shaped P-type buried layer 002 is also provided at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001 below the gate polysilicon 012.

[0056] In one embodiment, such as Figure 3 As shown, the high-voltage device is a JFET device, including a P-type substrate 001. The first P-type isolation pillar 130a and the second P-type isolation pillar 130b each include a P-type buried layer 002, a P-type region 003, and a P-type deep well 004 arranged sequentially from bottom to top. The P-type buried layer 002 is located at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001, and is led to the surface through the P-type region 003 and the P-type deep well 004. The P-type deep well 004 of the first P-type isolation pillar 130a is connected to the gate metal 014 through a P-type high-concentration contact 006. The N-type doped epitaxial layer 008 region between the first P-type isolation pillar 130a and the second P-type isolation pillar 130b serves as a high-concentration contact. The drift region of the voltage device has an N-type high-concentration contact 005 connected to the source metal 011 on the side near the gate metal 014 and an N-type high-concentration contact 005 connected to the drain metal 013 on the other side away from the gate metal 014. A field oxide layer is provided above the N-type doped epitaxial layer 008. A gate polysilicon 012 is provided above the field oxide layer on the side of the source metal 011 facing towards the middle. A gate oxide layer 010 is provided between the gate polysilicon 012 and the field oxide layer. An island-shaped P-type buried layer 002 is also provided at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001 below the gate polysilicon 012. A P-type region 003 is provided above the island-shaped P-type buried layer 002.

[0057] In one embodiment, such as Figure 4As shown, the high-voltage device is a JFET device, comprising a P-type substrate 001, the first P-type isolation column 130a and the second P-type isolation column 130b each comprising a P-type buried layer 002, a P-type region 003 and a P-type deep well 004 arranged in sequence from bottom to top; the P-type buried layer 002 is located at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001, and the P-type buried layer 002 is led to the surface through the P-type region 003 and the P-type deep well 004; the P-type deep well 004 of the first P-type isolation column 130a is connected with the gate metal 014 through the P-type high-concentration contact 006; the region of the N-type doped epitaxial layer 008 between the first P-type isolation column 130a and the second P-type isolation column 130b serves as a drift region of the high-voltage device, an N-type high-concentration contact 005 connected with the source metal 011 is arranged on the side of the drift region close to the gate metal 014, and an N-type high-concentration contact 005 connected with the drain metal 013 is arranged on the side of the drift region away from the gate metal 014; a field oxide layer is arranged above the N-type doped epitaxial layer 008, a gate polysilicon 012 is arranged on the side of the field oxide layer close to the middle of the source metal 011, and a gate oxide layer 010 is arranged between the gate polysilicon 012 and the field oxide layer; wherein the P-type buried layer 002 and the P-type region 003 of the first P-type isolation column 130a extend laterally to the middle and below the gate polysilicon 012;

[0058] In one embodiment, as shown in Figure 5 As shown, the high-voltage device is a JFET device, comprising a P-type substrate 001, the first P-type isolation column 130a and the second P-type isolation column 130b each comprising a P-type buried layer 002, a P-type region 003 and a P-type deep well 004 arranged in sequence from bottom to top; the P-type buried layer 002 is located at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001, and the P-type buried layer 002 is led to the surface through the P-type region 003 and the P-type deep well 004; the P-type deep well 004 of the first P-type isolation column 130a is connected with the gate metal 014 through the P-type high-concentration contact 006; the region of the N-type doped epitaxial layer 008 between the first P-type isolation column 130a and the second P-type isolation column 130b serves as a drift region of the high-voltage device, an N-type high-concentration contact 005 connected with the source metal 011 is arranged on the side of the drift region close to the gate metal 014, and an N-type high-concentration contact 005 connected with the drain metal 013 is arranged on the side of the drift region away from the gate metal 014; a field oxide layer is arranged above the N-type doped epitaxial layer 008; a longitudinal trench 020 is arranged in the drift region on the side close to the source metal 011 towards the middle, and the longitudinal trench 020 is provided with a gate polysilicon 012 wrapped by an oxide layer; the junction of the N-type doped epitaxial layer 008 below the gate polysilicon 012 and the P-type substrate 001 is further provided with an island-shaped P-type buried layer 002, and the island-shaped P-type buried layer 002 is provided with a P-type region 003 above it;

[0059] In one embodiment, such as Figure 6 As shown, the high-voltage device is a JFET device, including a P-type substrate 001. The first P-type isolation pillar 130a and the second P-type isolation pillar 130b each include a P-type buried layer 002, a P-type region 003, and a P-type deep well 004 arranged sequentially from bottom to top. The P-type buried layer 002 is located at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001, and is led to the surface through the P-type region 003 and the P-type deep well 004. The P-type deep well 004 of the first P-type isolation pillar 130a is connected to the gate metal 014 through a P-type high-concentration contact 006. The first P-type isolation pillar 130a and the second P-type isolation pillar 130b... The N-type doped epitaxial layer 008 region between the N-type isolation pillars 130b serves as the drift region of the high-voltage device. In the drift region, an N-type high-concentration contact 005 is provided on the side near the gate metal 014, connecting to the source metal 011. On the other side away from the gate metal 014, an N-type high-concentration contact 005 is provided, connecting to the drain metal 013. A field oxide layer is provided above the N-type doped epitaxial layer 008. A longitudinal trench 020 is provided on the side of the drift region near the source metal 011 towards the center. A gate polysilicon 012 encased in an oxide layer is provided within the longitudinal trench 020. The longitudinal trenches 020 are spaced apart in the Y direction.

[0060] In one embodiment, such as Figure 7 As shown, the high-voltage device is a JFET device, including a P-type substrate 001. The first P-type isolation pillar 130a and the second P-type isolation pillar 130b each include a P-type buried layer 002, a P-type region 003, and a P-type deep well 004 arranged sequentially from bottom to top. The P-type buried layer 002 is located at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001, and is led to the surface through the P-type region 003 and the P-type deep well 004. The P-type deep well 004 of the first P-type isolation pillar 130a is connected to the gate metal 014 through a P-type high-concentration contact 006. The first P-type isolation pillar 130a and the second P-type isolation pillar 130b... The N-type doped epitaxial layer 008 region between the pillar 130b serves as the drift region of the high-voltage device. In the drift region, an N-type high-concentration contact 005 is provided on the side near the gate metal 014, which is connected to the source metal 011. On the other side away from the gate metal 014, an N-type high-concentration contact 005 is provided, which is connected to the drain metal 013. A field oxide layer is provided above the N-type doped epitaxial layer 008. In the drift region, on the side near the source metal 011 towards the middle, from the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001, P-type buried layer 002, P-type region 003 and P-type deep well 004 are sequentially provided along the Y direction at intervals.

[0061] It should be noted that, in Figure 6 and Figure 7Gate metal 014, source metal 011, and drain metal 013 are not shown; please refer to [the provided text]. Figures 2 to 5 ;

[0062] In one embodiment, such as Figure 8 As shown, the high-voltage device is an LDMOS device, including a P-type substrate 001. The first P-type isolation pillar 130a and the second P-type isolation pillar 130b each include a P-type buried layer 002, a P-type region 003, and a P-type deep well 004 arranged sequentially from bottom to top. The P-type buried layer 002 is located at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001. The P-type buried layer 002 is led to the surface through the P-type region 003 and the P-type deep well 004. The surface of the P-type deep well 004 of the first P-type isolation pillar 130a is provided with a P-type high-concentration contact 006 and an N-type high-concentration contact 005, and is connected to the source metal... The N-type doped epitaxial layer 008 region between the first P-type isolation pillar 130a and the second P-type isolation pillar 130b serves as the drift region of the high-voltage device. A field oxide layer is provided above the N-type doped epitaxial layer 008. The gate polysilicon 012 extends from the N-type high-concentration contact 005 on the surface of the P-type deep well 004 of the first P-type isolation pillar 130a toward the middle to one end above the field oxide layer of the drift region. A gate oxide layer 010 is also provided below the gate polysilicon 012. An N-type high-concentration contact 005 is provided on the other side of the drift region away from the source metal 011 and is connected to the drain metal 013.

[0063] In one embodiment, such as Figure 9 As shown, the high-voltage device is a LIGBT device, including a P-type substrate 001. The first P-type isolation pillar 130a and the second P-type isolation pillar 130b each include a P-type buried layer 002, a P-type region 003, and a P-type deep well 004 arranged sequentially from bottom to top. The P-type buried layer 002 is located at the interface between the N-type doped epitaxial layer 008 and the P-type substrate 001, and is led to the surface through the P-type region 003 and the P-type deep well 004. The surface of the P-type deep well 004 of the first P-type isolation pillar 130a is provided with a P-type high-concentration contact 006 and an N-type high-concentration contact 005, which are connected to the emitter metal. 015 are connected; the N-type doped epitaxial layer 008 region between the first P-type isolation pillar 130a and the second P-type isolation pillar 130b serves as the drift region of the high-voltage device; a field oxide layer is provided above the N-type doped epitaxial layer 008; the gate polysilicon 012 extends from the N-type high-concentration contact 005 on the surface of the P-type deep well 004 of the first P-type isolation pillar 130a toward the middle to one end above the field oxide layer of the drift region, and a gate oxide layer 010 is also provided below the gate polysilicon 012; an N-type high-concentration contact 005 is provided on the other side of the drift region away from the emitter metal 015 and connected to the collector metal 016;

[0064] In one embodiment, such as Figure 10As shown, the high-voltage device is a power diode device, including a P-type substrate 001, the first P-type isolation column 130a and the second P-type isolation column 130b each including a P-type buried layer 002, a P-type region 003 and a P-type deep well 004 arranged in sequence from bottom to top; the P-type buried layer 002 is located at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001, and is led to the surface through the P-type region 003 and the P-type deep well 004; the surface of the P-type deep well 004 of the first P-type isolation column 130a is provided with a P-type high-concentration contact 006 and is connected with an anode metal 017; the region of the N-type doped epitaxial layer 008 between the first P-type isolation column 130a and the second P-type isolation column 130b serves as a drift region of the high-voltage device; an N-type high-concentration contact 005 is provided on the other side of the drift region away from the anode metal 017 and is connected with a cathode metal 018;

[0065] As shown in the drawings, Figures 11 to 15 the embodiment of the present application also proposes a manufacturing method of a semiconductor device, including the following steps:

[0066] Step one: selecting a P-type substrate 001 material, implanting boron ions through a mask window and annealing to form a P-type buried layer 002;

[0067] Step two: growing an N-type doped epitaxial layer 008 on the P-type substrate 001, the P-type buried layer 002 diffuses upward due to high temperature, and P-type regions 003 and P-type deep wells 004 are selectively implanted through a mask window by means of ion implantation and annealing;

[0068] Step three: growing a layer of silicon nitride on the silicon surface, etching out a field oxide layer region through a mask window, and oxidizing and growing a field oxide layer in the region not covered by the silicon nitride on the surface;

[0069] Step four: growing a gate oxide layer 010 and depositing a gate polysilicon 012 on the surface of the device, and etching away the excess gate oxide layer 010 and gate polysilicon 012 through a mask window;

[0070] Step five: implanting heavily doped N-type high-concentration contacts 005 and P-type high-concentration contacts 006 through a mask window to form gates, sources and drains;

[0071] Step six: depositing an insulating medium layer, then selectively etching a via hole on the insulating medium layer, then depositing a metal and selectively etching the metal to form a source metal 011, a drain metal 013 and a gate metal 014;

[0072] Optionally, referring to Figure 2 , the P-type deep well 004 can be directly connected with the P-type buried layer 002, and the above embodiment does not implant the P-type region 003 during device preparation.

[0073] As shown in the drawings,Figures 16 to 18 As shown in the drawings, the embodiments of the present application also propose a manufacturing method of a semiconductor device, comprising the following steps:

[0074] Step one: select P-type substrate 001 material, inject boron ions through a mask window and anneal to form P-type buried layer 002;

[0075] Step two: grow N-type doped epitaxial layer 008 on the P-type substrate 001, the P-type buried layer 002 diffuses upward due to high temperature, selectively inject P-type region 003 and P-type deep well 004 through a mask window by means of ion implantation and anneal;

[0076] Step three: selectively etch longitudinal trench 020 on the N-type doped epitaxial layer 008, grow oxide layer in the longitudinal trench 020, and deposit polysilicon to fill the trench to form gate polysilicon 012;

[0077] Step four: grow a layer of silicon nitride on the silicon surface, etch field oxide layer region through a mask window, and oxidize and grow field oxide layer in the region not covered by the silicon nitride on the surface;

[0078] Step five: inject heavily doped N-type high concentration contact 005 and P-type high concentration contact 006 through a mask window to form gate, source and drain;

[0079] Step six: deposit insulating medium layer, then selectively etch through hole on the insulating medium layer, then deposit metal and selectively etch metal to form source metal 011, drain metal 013 and gate metal 014.

[0080] Optionally, referring to Figure 2 P-type deep well 004 can be directly connected with P-type buried layer 002, and the above embodiments no longer inject P-type region 003 when the device is prepared.

[0081] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present application and not to limit it, although the present application has been described in detail with reference to examples, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced equivalently without departing from the spirit and scope of the technical solutions of the present application, and they should be covered in the scope of the claims of the present application.

Claims

1. A semiconductor device, comprising: P-type substrate (001), wherein an N-type doped epitaxial layer (008) is arranged on the P-type substrate (001), a high-voltage region (110) and a low-voltage region (140) are arranged on the N-type doped epitaxial layer (008), and a high-low voltage junction terminal region (120) is arranged between the high-voltage region (110) and the low-voltage region (140), characterized in that a first P-type isolation column (130a) is arranged between the low-voltage region (140) and the high-low voltage junction terminal region (120), a second P-type isolation column (130b) is arranged between the high-voltage region (110) and the high-low voltage junction terminal region (120), the first P-type isolation column (130a) is connected to the second P-type isolation column (130b), and the first P-type isolation column (130a) and the second P-type isolation column (130b) form one or more closed regions, and a high-voltage device is arranged in the closed region. The high-voltage device is a power diode device, comprising a P-type substrate (001), wherein the first P-type isolation column (130a) and the second P-type isolation column (130b) each comprise a P-type buried layer (002), a P-type region (003) and a P-type deep well (004) arranged in turn from bottom to top; the P-type buried layer (002) is located at the junction of the N-type doped epitaxial layer (008) and the P-type substrate (001), and the P-type buried layer (002) is led to the surface through the P-type region (003) and the P-type deep well (004); wherein the P-type deep well (004) of the first P-type isolation column (130a) is provided with a P-type high-concentration contact (006) on the surface and is connected to an anode metal (017); the region of the N-type doped epitaxial layer (008) between the first P-type isolation column (130a) and the second P-type isolation column (130b) serves as a drift region of the high-voltage device; an N-type high-concentration contact (005) is arranged on the other side of the drift region away from the anode metal (017) and is connected to a cathode metal (018).

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