A gallium nitride power device, its fabrication method, and a chip

Abstract

This application belongs to the field of semiconductor technology and provides a gallium nitride (GaN) power device, its fabrication method, and a chip. The GaN power device includes: a semiconductor substrate, a channel layer, a first barrier layer, a second barrier layer, a first P-pillar, a second P-pillar, a source electrode, a drain electrode, and a gate electrode. By setting the gate electrode to Schottky metal and making the gate electrode contact with the first P-pillar and the second P-pillar, a high Schottky barrier height can be achieved between the gate electrode and the first and second P-pillars, thereby reducing the leakage current of the gate electrode, providing a higher forward threshold voltage, improving the performance of the GaN power device, and expanding the application range of GaN power devices.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a gallium nitride power device, a preparation method and a chip. BACKGROUND

[0002] As a representative of the third generation semiconductor material, gallium nitride (GaN) has many excellent properties, such as high critical breakdown field, high electron mobility, high two-dimensional electron gas density and good high-temperature working ability. The third generation semiconductor devices based on gallium nitride, such as high electron mobility transistors (HEMTs), heterojunction field effect transistors (HFETs) and the like, have been applied, and have obvious advantages in the fields of radio frequency, microwave and the like which require high power and high frequency.

[0003] For HEMT (High Electron Mobility Transistor), the channel conduction from the source to the drain is mainly realized through the two-dimensional electron gas (2DEG) at the interface between AlGaN (gallium aluminum nitride) and GaN (gallium nitride). However, the surface defects of the power device and the limited barrier height will cause current leakage, further reducing the drain breakdown voltage of the device.

[0004] In summary, the existing power device has the problem of large gate leakage current which affects the application range of the power device. SUMMARY

[0005] In order to solve the above technical problems, the embodiments of the present application provide a gallium nitride power device, a preparation method and a chip, which are aimed at solving the technical problem of large gate leakage current of the power device in the prior art which affects the application range of the power device.

[0006] A first aspect of the embodiments of the present application provides a gallium nitride power device, which comprises:

[0007] a semiconductor substrate;

[0008] a channel layer provided on the semiconductor substrate;

[0009] a first barrier layer provided on the semiconductor substrate and in contact with a first surface of the channel layer;

[0010] a second barrier layer provided on the semiconductor substrate and in contact with a second surface of the channel layer;

[0011] a first P column provided on the semiconductor substrate, and the first barrier layer is provided between the first P column and the channel layer;

[0012] a second P column provided on the semiconductor substrate, and the second barrier layer is provided between the second P column and the channel layer;

[0013] a source electrode disposed on the semiconductor substrate and contacting the first end of the channel layer, the first end of the first barrier layer, and the first end of the second barrier layer, respectively;

[0014] a drain electrode disposed on the semiconductor substrate and contacting the second end of the channel layer, the second end of the first barrier layer, and the second end of the second barrier layer, respectively;

[0015] a gate electrode disposed on the channel layer, the first barrier layer, the second barrier layer, the first P-pillar, and the second P-pillar;

[0016] wherein the gate electrode is a Schottky metal.

[0017] In one embodiment, the source electrode is a Schottky metal, and the drain electrode is an Ohmic metal.

[0018] In one embodiment, the first P-pillar and the second P-pillar are oppositely disposed.

[0019] In one embodiment, the distance from the first P-pillar to the source electrode is the same as the distance from the first P-pillar to the drain electrode.

[0020] In one embodiment, the length of the gate electrode is greater than the length of the source electrode, and the length of the source electrode is the same as the length of the drain electrode.

[0021] In one embodiment, the length of the first P-pillar is less than the length of the first barrier layer.

[0022] In one embodiment, the length of the first P-pillar is 1 / 3 of the length of the first barrier layer.

[0023] In one embodiment, the width of the first P-pillar is the same as the width of the first barrier layer.

[0024] A second aspect of the embodiments of the present application provides a multi-channel enhanced gallium nitride chip, comprising a plurality of gallium nitride power devices as described in any one of the above embodiments, the plurality of gallium nitride power devices being disposed on the same semiconductor substrate, and the source electrodes of the plurality of gallium nitride power devices being connected in common, the gate electrodes of the plurality of gallium nitride power devices being connected in common, and the drain electrodes of the plurality of gallium nitride power devices being connected in common.

[0025] A third aspect of the embodiments of the present application provides a preparation method of a gallium nitride power device, comprising:

[0026] forming a first P-pillar, a channel layer, and a second P-pillar on a semiconductor substrate in sequence and at intervals;

[0027] forming a first barrier layer on the semiconductor substrate; wherein the first barrier layer is between the first P-pillar and the channel layer;

[0028] forming a second barrier layer on the semiconductor substrate; wherein the second barrier layer is between the second P-pillar and the channel layer;

[0029] forming a source electrode on the semiconductor substrate; wherein the source electrode contacts a first end of the channel layer, a first end of the first barrier layer and a first end of the second barrier layer respectively;

[0030] forming a drain electrode on the semiconductor substrate; wherein the drain electrode contacts a second end of the channel layer, a second end of the first barrier layer and a second end of the second barrier layer respectively;

[0031] forming a gate electrode on the channel layer, the first barrier layer, the second barrier layer, the first P-pillar and the second P-pillar; wherein the gate electrode is a Schottky metal.

[0032] Compared with the prior art, the embodiment has the beneficial effects that: in the embodiment, the gate electrode is a Schottky metal, and the gate electrode contacts the first P-pillar and the second P-pillar, so that the gate electrode and the first P-pillar are in Schottky contact, and the gate electrode and the second P-pillar are in Schottky contact, which can make the gate electrode and the first P-pillar and the second P-pillar have a higher Schottky barrier height, thereby reducing the leakage current of the gate electrode, providing a higher forward threshold voltage, and thus improving the performance of the gallium nitride power device and expanding the application range of the gallium nitride power device. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a vertical sectional structure schematic diagram of a gallium nitride power device provided by an embodiment of the present application;

[0034] Figure 2 is a top view structure schematic diagram of a gallium nitride power device provided by an embodiment of the present application;

[0035] Figure 3 is a structure schematic diagram of a gallium nitride power device provided by an embodiment of the present application;

[0036] Figure 4 is a structure schematic diagram of a multi-channel enhanced gallium nitride chip provided by an embodiment of the present application;

[0037] Figure 5 is a preparation method step schematic diagram of a gallium nitride power device provided by an embodiment of the present application;

[0038] Figure 6 is a schematic view after forming a first P-pillar, a channel layer, and a second P-pillar according to an embodiment of the present application;

[0039] Figure 7 is a schematic view after forming a first barrier layer and a second barrier layer according to an embodiment of the present application;

[0040] Figure 8 is a schematic view after forming a source electrode and a drain electrode according to an embodiment of the present application;

[0041] Figure 9 is a schematic view after forming a gate electrode according to an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the technical problems solved by the present application, the technical solutions and beneficial effects clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and not used to limit the present application.

[0043] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0044] It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0045] In addition, the terms "first", "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is one or more than one, unless otherwise specifically limited.

[0046] Reference to "one embodiment", "some embodiments", "an embodiment" or "embodiments" in the present application description means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrases "in one embodiment", "in some embodiments", "in other embodiments", "in additional embodiments", "in one specific embodiment", "in one particular aspect" and the like in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily referring to one specific embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0047] As a representative of the third generation semiconductor material, gallium nitride (GaN) has many excellent properties, such as high critical breakdown field, high electron mobility, high two-dimensional electron gas density, and good high-temperature working ability. Third-generation semiconductor devices based on gallium nitride, such as high electron mobility transistors (HEMTs), heterojunction field effect transistors (HFETs), etc., have been applied, especially in the fields of radio frequency, microwave, etc. that require high power and high frequency.

[0048] For HEMT (High Electron Mobility Transistor), the channel conduction from the source to the drain is mainly realized by the two-dimensional electron gas (2DEG) at the interface between AlGaN (gallium aluminum nitride) and GaN (gallium nitride). However, the surface defects of the power device and the limited barrier height will cause current leakage, further reducing the drain breakdown voltage of the device.

[0049] In summary, the existing power device has the problem of large gate leakage current, which affects the application range of the power device.

[0050] To solve the above technical problems, the embodiments of the present application provide a gallium nitride power device, as shown in Figure 1 、 Figure 2 , Figure 1 is a schematic diagram of a vertical section structure of the gallium nitride power device from the gate electrode, Figure 2 is a schematic diagram of a top view structure of the gallium nitride power device, the gallium nitride power device comprising: a semiconductor substrate 10, a channel layer 20, a first barrier layer 30, a second barrier layer 40, a first P column 50, a second P column 60, a source electrode 80, a drain electrode 90, and a gate electrode 70.

[0051] Specifically, the channel layer 20 is arranged on the semiconductor substrate 10. The first barrier layer 30 is arranged on the semiconductor substrate 10, and the first barrier layer 30 is in contact with the first surface of the channel layer 20. The second barrier layer 40 is arranged on the semiconductor substrate 10, and the second barrier layer 40 is in contact with the second surface of the channel layer 20. The first P column 50 is arranged on the semiconductor substrate 10, and the first barrier layer 30 is arranged between the first P column 50 and the channel layer 20. The second P column 60 is arranged on the semiconductor substrate 10, and the second barrier layer 40 is arranged between the second P column 60 and the channel layer 20. The source electrode 80 is arranged on the semiconductor substrate 10, and the source electrode 80 is in contact with the first end of the channel layer 20, the first end of the first barrier layer 30 and the first end of the second barrier layer 40 respectively. The drain electrode 90 is arranged on the semiconductor substrate 10, and the drain electrode 90 is in contact with the second end of the channel layer 20, the second end of the first barrier layer 30 and the second end of the second barrier layer 40 respectively. The gate electrode 70 is arranged on the channel layer 20, the first barrier layer 30, the second barrier layer 40, the first P column 50 and the second P column 60. The gate electrode 70 is a Schottky metal.

[0052] In the embodiment, the first barrier layer 30 is in contact with the first surface of the channel layer 20, and the second barrier layer 40 is in contact with the second surface of the channel layer 20. It can be understood that the channel layer 20 is arranged between the first barrier layer 30 and the second barrier layer 40, the first barrier layer 30 and the second barrier layer 40 are arranged on both sides of the channel layer 20, and the first barrier layer 30 and the second barrier layer 40 are arranged oppositely. In the embodiment, by arranging the first barrier layer 30 and the second barrier layer 40 on both sides of the channel layer 20, a double-layer two-dimensional electron gas (2DEG) can be formed on both sides of the channel layer 20, and the communication between the source electrode 80 and the drain electrode 90 is realized.

[0053] In the embodiment, the first barrier layer 30 is arranged between the first P column 50 and the channel layer 20. It can be understood that the first P column 50 is in contact with the first barrier layer 30, and the second barrier layer 40 is arranged between the second P column 60 and the channel layer 20, and the second P column 60 is in contact with the second barrier layer 40. In the embodiment, by arranging the first P column 50 and the second P column 60 to be in contact with the first barrier layer 30 and the second barrier layer 40 respectively, the double-layer two-dimensional electron gas can be offset by the first P column 50 and the second P column 60, so that the gallium nitride power device has a smaller two-dimensional electron gas when it is turned off, and the generation of leakage current is avoided, so that the device is completely controlled and a higher forward threshold voltage is provided.

[0054] In this embodiment, the source electrode 80 is in contact with the first end of the channel layer 20, the first end of the first barrier layer 30, and the first end of the second barrier layer 40, respectively. The drain electrode 90 is in contact with the second end of the channel layer 20, the second end of the first barrier layer 30, and the second end of the second barrier layer 40, respectively. It can be understood that the source electrode 80 and the drain electrode 90 are respectively located at both ends of the channel layer 20, the first barrier layer 30, and the second barrier layer 40.

[0055] In this embodiment, the channel layer 20, the first barrier layer 30, and the second barrier layer 40 are all vertically disposed on the semiconductor substrate 10, and the gate electrode 70 is disposed on the channel layer 20, the first barrier layer 30, the second barrier layer 40, the first P-pillar 50, and the second P-pillar 60. The gate electrode 70 is made of Schottky metal. Compared to conventional semiconductor devices where the channel layer 20 and the barrier layer are disposed parallel to each other on the semiconductor substrate 10, this provides a higher Schottky barrier height, thereby reducing the leakage current of the gate electrode 70 and providing a higher forward threshold voltage.

[0056] In one embodiment, the channel layer 20 is GaN.

[0057] In this embodiment, the channel layer 20 can be made of gallium nitride material, for example, by depositing gallium nitride material on the semiconductor substrate 10 or by epitaxially growing gallium nitride material.

[0058] In one embodiment, both the first barrier layer 30 and the second barrier layer 40 are AlGaN.

[0059] In this embodiment, the first barrier layer 30 and the second barrier layer 40 can both be made of aluminum gallium nitride material, for example, by depositing aluminum gallium nitride material on the semiconductor substrate 10 or by epitaxially growing aluminum gallium nitride material to form the first barrier layer 30 and the second barrier layer 40.

[0060] In one embodiment, the first P-pillar 50 and the second P-pillar 60 are P-GaN.

[0061] In this embodiment, P-GaN is formed by doping GaN with a p-type dopant, wherein the p-type dopant can be boron, gallium, aluminum, etc.

[0062] In one embodiment, the semiconductor substrate 10 is a sapphire substrate.

[0063] In one embodiment, the source electrode 80 is a Schottky metal and the drain electrode 90 is an ohmic metal.

[0064] Specifically, Schottky metals can be layers of platinum, gold, or silver, or conductive semiconductor layers, etc. Ohmic metals are combinations of Ti, Al, Ti, and Au materials.

[0065] In a specific application, Schottky metal is a combination of Ni and Au materials.

[0066] In one embodiment, the thicknesses of the ohmic metals Ti, Al, Ti, and Au are 15 nm, 250 nm, 50 nm, and 150 nm, respectively, and the thicknesses of the Schottky metals Ni and Au are 70 nm and 30 nm, respectively.

[0067] In this embodiment, by setting the gate electrode 70 to Schottky metal, the gate becomes a Schottky contact, which can provide a higher Schottky barrier height. By setting the thicknesses of Ni and Au in the Schottky metal to 70nm and 30nm respectively, the leakage current of the gate electrode 70 is further reduced, a higher forward threshold voltage is provided, and the overall performance of the gallium nitride power device is improved.

[0068] In one embodiment, reference Figure 1 As shown, the first P-pillar 50 and the second P-pillar 60 are positioned opposite each other.

[0069] Specifically, the first P-pillar 50 and the second P-pillar 60 are respectively disposed on both sides of the first barrier layer 30 and the second barrier layer 40. This can better cancel the two-dimensional electron gas on both sides of the channel layer 20. Furthermore, by setting the first P-pillar 50 and the second P-pillar 60 to be opposite each other, the areas where the two-dimensional electron gas on both sides of the channel layer 20 is canceled are the same, which can improve the stability of the power device. If the first P-pillar 50 and the second P-pillar 60 are not opposite each other, for example, if they are staggered, the areas where the two-dimensional electron gas on both sides of the channel layer 20 is canceled will be different, which will lead to unstable performance of the power device during operation and thus shorten the service life of the power device.

[0070] In one embodiment, reference Figure 3 As shown, for ease of observation, Figure 3 This is a schematic diagram of a gallium nitride power device without the gate electrode 70. The distance L1 from the first P-pillar 50 to the source electrode 80 is the same as the distance L2 from the first P-pillar 50 to the drain electrode 90. The distance from the second P-pillar 60 to the source electrode 80 is the same as the distance from the second P-pillar 60 to the drain electrode 90. Specifically, both the first P-pillar 50 and the second P-pillar 60 are located at the midpoint between the source electrode 80 and the drain electrode 90. This ensures that the areas where the two-dimensional electron gas is canceled on both sides of the channel layer 20 are the same, which can improve the stability of the power device.

[0071] In one embodiment, reference Figure 2As shown, the length L3 of the gate electrode 70 is greater than the length L4 of the source electrode 80, and the length L4 of the source electrode 80 is the same as the length L5 of the drain electrode 90. Because the gate electrode 70 is made of Schottky metal, and the gate electrode 70 contacts the first P-pillar 50, forming a Schottky contact between the gate electrode 70 and the first P-pillar 50, by setting the length L3 of the gate electrode 70 to be greater than the length L4 of the source electrode 80 and the length L5 of the drain electrode 90, a higher Schottky barrier height can be achieved between the gate electrode 70 and the first P-pillar 50, thereby reducing the leakage current of the gate electrode 70, providing a higher forward threshold voltage, and thus improving the performance of gallium nitride power devices and expanding the application range of gallium nitride power devices.

[0072] In one embodiment, because the gate electrode 70 is made of Schottky metal and is in contact with the second P-pillar 60, a Schottky contact is formed between the gate electrode 70 and the second P-pillar 60. By setting the length of the gate electrode 70 to be greater than the length of the source electrode 80 and the length of the gate electrode 70 to be greater than the length of the drain electrode 90, a higher Schottky barrier height can be achieved between the gate electrode 70 and the second P-pillar 60, thereby reducing the leakage current of the gate electrode 70, providing a higher forward threshold voltage, and thus improving the performance of gallium nitride power devices and expanding the application range of gallium nitride power devices.

[0073] In one embodiment, reference Figure 2 As shown, the length of the gate electrode 70 is the sum of the lengths of the drain electrode 90 and the source electrode 80.

[0074] In this embodiment, by setting the length of the gate electrode 70 to be the sum of the lengths of the drain electrode 90 and the source electrode 80, the length of the gate electrode 70 is made larger, which can make the gate electrode 70 and the first P-pillar 50 and the second P-pillar 60 have a higher Schottky barrier height, thereby reducing the leakage current of the gate electrode 70, providing a higher forward threshold voltage, thereby improving the performance of gallium nitride power devices and expanding the application range of gallium nitride power devices.

[0075] In one embodiment, reference Figure 3 As shown, the first P-pillar 50 and the second P-pillar 60 have the same length, both denoted by L6. The length of the channel layer 20 is the same as the length of the first barrier layer 30 and the second barrier layer 40, both denoted by L7. Specifically, the length of the channel layer 20 is equal to the length of the first barrier layer 30 and the length of the second barrier layer 40. By setting the lengths of the first P-pillar 50 and the second P-pillar 60 to be the same, the areas where the two-dimensional electron gas on both sides of the channel layer 20 is canceled out are the same, which can improve the stability of the power device, make the gallium nitride power device work more stably, and expand the application range of gallium nitride power devices.

[0076] In one embodiment, reference Figure 3 As shown, the length L6 of the first P-pillar 50 is less than the length L7 of the first barrier layer 30. Specifically, the length L6 of the first P-pillar 50 is less than the length L7 of the first barrier layer 30 because both the first P-pillar 50 and the second P-pillar 60 are used to cancel the two-dimensional electron gas. The two-dimensional electron gas is used to realize communication between the source electrode 80 and the drain electrode 90. By setting the length of the first P-pillar 50 to be less than the length of the first barrier layer 30 and the length of the second P-pillar 60 to be less than the length of the second barrier layer 40, the two-dimensional electron gas will not be completely canceled. This not only enables the function of gallium nitride power devices but also allows for complete control of the devices and provides a higher forward threshold voltage.

[0077] In one embodiment, the length of the first P-pillar 50 is one-third the length of the first barrier layer 30. Specifically, the length of the second P-pillar 60 is one-third the length of the second barrier layer 40. Since both the first P-pillar 50 and the second P-pillar 60 are used to cancel the two-dimensional electron gas, which is used to achieve communication between the source electrode 80 and the drain electrode 90, by setting the length of the first P-pillar 50 to one-third the length of the first barrier layer 30 and the length of the second P-pillar 60 to one-third the length of the second barrier layer 40, the two-dimensional electron gas is not completely canceled out. This not only enables the function of gallium nitride power devices but also allows for complete control of the devices and provides a higher forward threshold voltage.

[0078] In one embodiment, the heights of the first P-pillar 50, the second P-pillar 60, the channel layer 20, the first barrier layer 30, and the second barrier layer 40 are all the same. In this embodiment, by setting the heights of the first P-pillar 50, the second P-pillar 60, the channel layer 20, the first barrier layer 30, and the second barrier layer 40 to be identical, the performance of the gallium nitride power device can be made more stable, the lifespan of the gallium nitride power device can be extended, and the application range of gallium nitride power devices can be expanded.

[0079] In one embodiment, reference Figure 2 As shown, the width W2 of the first P-pillar 50 is greater than the width W1 of the first barrier layer 30, and the width of the second P-pillar 60 is the same as the width of the first P-pillar 50. Because the first P-pillar 50 and the second P-pillar 60 can cancel out the two-dimensional electron gas, by setting the width of the first P-pillar 50 to be greater than the width of the first barrier layer 30, the first P-pillar 50 and the second P-pillar 60 can better cancel out the two-dimensional electron gas of the double layer. This results in a smaller two-dimensional electron gas in the gallium nitride power device when it is turned off, avoiding leakage current. This achieves complete control of the device and provides a higher forward threshold voltage.

[0080] In one embodiment, the width of the first P-pillar 50 is the same as the width of the first barrier layer 30. Specifically, the width of the second P-pillar 60 is the same as the width of the first barrier layer 30, and the width of the first barrier layer 30 is the same as the width of the second barrier layer 40. In this embodiment, by setting the width of the first P-pillar 50 to be the same as the width of the first barrier layer 30, the performance of the gallium nitride power device can be made more stable, and the lifespan of the gallium nitride power device can be extended.

[0081] A second aspect of this application provides a multi-channel enhanced gallium nitride chip, with reference to... Figure 4 As shown, the device includes a plurality of gallium nitride power devices 100 as described above. The plurality of gallium nitride power devices 100 are disposed on the same semiconductor substrate 10, and the source electrodes 80 of the plurality of gallium nitride power devices 100 are connected in common, the gate electrodes 70 of the plurality of gallium nitride power devices 100 are connected in common, and the drain electrodes 90 of the plurality of gallium nitride power devices 100 are connected in common.

[0082] Specifically, multiple gallium nitride (GaN) power devices 100 are connected together via adjacent first P-pillars 50 and second P-pillars 60. For example, the first P-pillar 50 of the first GaN power device 100 is connected to the second P-pillar 60 of the second GaN power device 100, the first P-pillar 50 of the second GaN power device 100 is connected to the second P-pillar 60 of the third GaN power device 100, and so on, forming a multi-channel enhancement-mode GaN chip. The biggest advantage of the multi-channel enhancement-mode GaN chip is that it can reduce the gate leakage current and provide a higher forward threshold voltage by using the high Schottky barrier height between the gate electrode 70, the first P-pillar 50, and the second P-pillar 60. By setting multiple gallium nitride power devices 100 together on the same semiconductor substrate 10, and connecting the source electrodes 80, gate electrodes 70, and drain electrodes 90 of the multiple gallium nitride power devices 100 together, the multiple gallium nitride power devices 100 can be used in parallel. The first P-pillar 50 and the second P-pillar 60 can be used as the connection between two adjacent gallium nitride power devices 100, which can realize the control of multiple devices, effectively avoid the generation of leakage current, and generate higher forward conduction current.

[0083] This application also provides a method for fabricating a gallium nitride power device, referring to... Figure 5 As shown, it includes steps S10 to S50.

[0084] Step S10: Reference Figure 6 As shown, a first P-pillar 50, a channel layer 20, and a second P-pillar 60 are sequentially and spaced apart on a semiconductor substrate 10.

[0085] In a specific application, selective etching is performed on the semiconductor substrate 10 to etch out the positions of the first P-pillar 50, the channel layer 20, and the second P-pillar 60, respectively. Then, the corresponding semiconductor materials are filled in the corresponding positions of the first P-pillar 50, the channel layer 20, and the second P-pillar 60. For example, P-GaN material is filled in the first P-pillar 50 and the second P-pillar 60 regions, and GaN material is filled in the channel layer 20 region.

[0086] In one specific application, the semiconductor substrate 10 is a sapphire substrate.

[0087] Step S20: Reference Figure 7 As shown, a first barrier layer 30 is formed on a semiconductor substrate 10; wherein the first barrier layer 30 is located between the first P-pillar 50 and the channel layer 20, and a second barrier layer 40 is formed on the semiconductor substrate 10; wherein the second barrier layer 40 is located between the second P-pillar 60 and the channel layer 20.

[0088] In a specific application, selective etching is performed on the semiconductor substrate 10 to etch out the positions of the first barrier layer 30 and the second barrier layer 40, respectively. Then, the corresponding semiconductor materials are filled into the corresponding positions of the first barrier layer 30 and the second barrier layer 40. For example, AlGaN material is filled into the positions of the first barrier layer 30 and the second barrier layer 40.

[0089] In one embodiment, the heights of the first P-pillar 50, the channel layer 20, the second P-pillar 60, the first barrier layer 30, and the second barrier layer 40 can be determined by repeatedly extending the first P-pillar 50, the channel layer 20, the second P-pillar 60, the first barrier layer 30, and the second barrier layer 40.

[0090] Step S30: Reference Figure 8 As shown, a source electrode 80 is formed on a semiconductor substrate 10; wherein the source electrode 80 is in contact with the first end of the channel layer 20, the first end of the first barrier layer 30 and the first end of the second barrier layer 40, respectively.

[0091] In one embodiment, a mask is used to determine the shape of the source electrode 80, and metal is deposited on the mask to form the source electrode 80.

[0092] Step S40: Reference Figure 8 As shown, a drain electrode 90 is formed on the semiconductor substrate 10; wherein the drain electrode 90 is in contact with the second end of the channel layer 20, the second end of the first barrier layer 30 and the second end of the second barrier layer 40.

[0093] In one embodiment, a mask is used to determine the shape of the drain electrode 90, and metal is deposited on the mask to form the drain electrode 90.

[0094] Step S50: Reference Figure 9 As shown, a gate electrode 70 is formed on the channel layer 20, the first barrier layer 30, the second barrier layer 40, the first P-pillar 50, and the second P-pillar 60; wherein, the gate electrode 70 is Schottky metal.

[0095] In one embodiment, a mask is used to determine the shape of the gate electrode 70, and metal is deposited on the mask to form the gate electrode 70. Because the gate electrode 70 is Schottky metal, the gate electrode 70 contacts the first P-pillar 50, making a Schottky contact between the gate electrode 70 and the first P-pillar 50. By setting the length of the gate electrode 70 to be greater than the length of the source electrode 80 and the length of the gate electrode 70 to be greater than the length of the drain electrode 90, a higher Schottky barrier height can be achieved between the gate electrode 70 and the first P-pillar 50, thereby reducing the leakage current of the gate electrode 70, providing a higher forward threshold voltage, thereby improving the performance of gallium nitride power devices and expanding the application range of gallium nitride power devices.

[0096] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0097] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A gallium nitride power device, characterized by, The gallium nitride power device comprises: a semiconductor substrate; a channel layer disposed on the semiconductor substrate; a first barrier layer disposed on the semiconductor substrate and in contact with a first surface of the channel layer; a second barrier layer disposed on the semiconductor substrate and in contact with a second surface of the channel layer; a first P-pillar disposed on the semiconductor substrate, and the first barrier layer is disposed between the first P-pillar and the channel layer; a second P-pillar disposed on the semiconductor substrate, and the second barrier layer is disposed between the second P-pillar and the channel layer; a source electrode disposed on the semiconductor substrate, and the source electrode is in contact with a first end of the channel layer, a first end of the first barrier layer, and a first end of the second barrier layer, respectively; a drain electrode disposed on the semiconductor substrate, and the drain electrode is in contact with a second end of the channel layer, a second end of the first barrier layer, and a second end of the second barrier layer, respectively; a gate electrode disposed on the channel layer, the first barrier layer, the second barrier layer, the first P-pillar, and the second P-pillar; wherein the gate electrode is a Schottky metal; the distance from the first P-pillar to the source electrode is the same as the distance from the first P-pillar to the drain electrode.

2. The gallium nitride power device of claim 1, wherein, The source electrode is a Schottky metal, and the drain electrode is an ohmic metal.

3. The gallium nitride power device of claim 1, wherein, The first P-pillar and the second P-pillar are oppositely disposed.

4. The gallium nitride power device of claim 1, wherein, The length of the gate electrode is greater than the length of the source electrode, and the length of the source electrode is the same as the length of the drain electrode.

5. The gallium nitride power device of claim 1 wherein, The length of the first P-pillar is less than the length of the first barrier layer.

6. The gallium nitride power device of claim 5, wherein, The length of the first P-pillar is 1 / 3 of the length of the first barrier layer.

7. The gallium nitride power device of any one of claims 1-6, wherein, The width of the first P-pillar is the same as the width of the first barrier layer.

8. A multi-channel enhanced gallium nitride chip, characterized by, The gallium nitride power device comprises:

9. A method of fabricating a gallium nitride power device, comprising: a semiconductor substrate; a channel layer disposed on the semiconductor substrate; a first barrier layer disposed on the semiconductor substrate and in contact with a first surface of the channel layer; a second barrier layer disposed on the semiconductor substrate and in contact with a second surface of the channel layer; a first P-pillar disposed on the semiconductor substrate, and the first barrier layer is disposed between the first P-pillar and the channel layer; a second P-pillar disposed on the semiconductor substrate, and the second barrier layer is disposed between the second P-pillar and the channel layer; a source electrode disposed on the semiconductor substrate, and the source electrode is in contact with a first end of the channel layer, a first end of the first barrier layer, and a first end of the second barrier layer, respectively; a drain electrode disposed on the semiconductor substrate, and the drain electrode is in contact with a second end of the channel layer, a second end of the first barrier layer, and a second end of the second barrier layer, respectively; a gate electrode disposed on the channel layer, the first barrier layer, the second barrier layer, the first P-pillar, and the second P-pillar; wherein the gate electrode is a Schottky metal; the distance from the first P-pillar to the source electrode is the same as the distance from the first P-pillar to the drain electrode. The source electrode is a Schottky metal, and the drain electrode is an ohmic metal. The first P-pillar and the second P-pillar are oppositely disposed. The length of the gate electrode is greater than the length of the source electrode, and the length of the source electrode is the same as the length of the drain electrode. The length of the first P-pillar is less than the length of the first barrier layer. The length of the first P-pillar is 1 / 3 of the length of the first barrier layer. The width of the first P-pillar is the same as the width of the first barrier layer. The gallium nitride power device comprises: a semiconductor substrate; a channel layer disposed on the semiconductor substrate; a first barrier layer disposed on the semiconductor substrate and in contact with a first surface of the channel layer; a second barrier layer disposed on the semiconductor substrate and in contact with a second surface of the channel layer; a first P-pillar disposed on the semiconductor substrate, and the first barrier layer is disposed between the first P-pillar and the channel layer; a second P-pillar disposed on the semiconductor substrate, and the second barrier layer is disposed between the second P-pillar and the channel layer; a source electrode disposed on the semiconductor substrate, and the source electrode is in contact with a first end of the channel layer, a first end of the first barrier layer, and a first end of the second barrier layer, respectively; a drain electrode disposed on the semiconductor substrate, and the drain electrode is in contact with a second end of the channel layer, a second end of the first barrier layer, and a second end of the second barrier layer, respectively; a gate electrode disposed on the channel layer, the first barrier layer, the second barrier layer, the first P-pillar, and the second P-pillar; wherein the gate electrode is a Schottky metal; The distance of the first P-pillar to the source electrode is the same as the distance of the first P-pillar to the drain electrode.

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