A method and system for preventing maloperation of direct current ground relay protection

Abstract

The application discloses a method and system for preventing DC grounding relay protection misoperation, and according to the characteristics of capacitor charging and discharging and the fault characteristics of a power system, different anti-interference strategies are executed for intelligent discrimination tripping loop and non-discrimination direct tripping loop as follows: for the intelligent discrimination tripping loop, time delay and fault discrimination are combined to prevent DC grounding relay protection misoperation; for the non-discrimination direct tripping loop, time delay and high-power starting tripping are combined to prevent DC grounding relay protection misoperation. The application is used for the grounding of a DC system of a power system substation, can prevent the grounding from being affected by a grounding capacitor, and can prevent the protection mis-tripping caused by the short-time conduction of cable loops such as a substation failure starting loop, an operating box tripping loop and a protection remote tripping loop.

Description

Technical Field

[0001] This invention belongs to the field of power system relay protection technology, and relates to a method and system for preventing DC grounding relay protection from malfunctioning. Background Technology

[0002] Relay protection devices need to distinguish between various faults or abnormal operating states of the protected equipment, thus requiring the collection of status information from the protected equipment. This status information includes analog quantities such as voltage and current, as well as switching quantities such as transformer gas tripping. Furthermore, to ensure the safety of the power system under complex accident conditions, such as circuit breaker failure, different protection devices also have coordination relationships; for example, a failure trip activation between a semi-main bus protection and circuit breaker protection. Therefore, relay protection devices often introduce some external switching quantities (contact quantities) as auxiliary criteria for their logic to act on tripping or signaling.

[0003] Currently, most relay protection devices and many automation devices in my country use opto-isolated switch inputs in their input circuits. This method effectively isolates the microprocessor-based device from electromagnetic interference from external high-voltage electricity. Using external high-voltage DC ensures the reliability of the input and avoids the unsafe and unstable factors caused by long-distance lead-out of internal low-voltage electricity, while also being relatively inexpensive. However, in field applications, relay protection devices frequently malfunction due to DC grounding, especially in high-voltage substations of 220kV and 500kV, seriously threatening the safe and economical operation of the power system. The direct cause of these accidents is the long input circuit cable and large grounding capacitance, leading to false starting of the input due to the charging and discharging of the DC grounding capacitor.

[0004] The principle behind DC grounding causing malfunction of the input circuit is as follows: Figure 2 As shown, the input terminal of the opto-isolation device uses an external DC power supply as the input drive power supply. However, the external DC system is not pure DC; it is equipped with an insulation monitoring device. Figure 2As shown, in this insulation monitoring device, R1 = R2 = 1kΩ, and R3 = R4 are the positive / negative pole insulation resistances to ground, with resistance values ​​above 0.5MΩ. The resistance value R0 of resistor kVI is relatively large; for a 220V DC system, R0 is 20-30kΩ, for a 110V DC system, R0 is 6-10kΩ, and for a 48V DC system, R0 is 1.5kΩ. The operating current is generally 2mA. For a 220V DC system, during normal operation, the voltage to ground at point +KM is +110V, and the voltage to ground at point -KM is -110V. Because of the insulation monitoring device, the DC system can be considered to be grounded through a high-resistance point during normal operation. When another grounding occurs, a two-point grounding system is formed. At this time, current flows between the two grounding points, causing a false connection of the input. Furthermore, due to the influence of the DC cable, the +KM and -KM of the DC system can be considered to be connected to the ground via capacitors C1 and C3, while the opto-isolated input can be considered to be connected to the ground via capacitor C2. The capacitance value of C2 is affected by the length of the input cable; the longer the cable, the larger the capacitance. For a 500kV substation with a small bay layout, the measured capacitance of the input cable for failure protection activation can be approximately 0.15μF larger. When the DC system is grounded at point K, according to... Figure 2 It can be seen that this is equivalent to the DC system charging through capacitor C2 and the input optocoupler, which may cause the optocoupler to mis-circuit. For the aforementioned 500kV substation, assuming the capacitance of the malfunctioning input optocoupler is 0.155μF, the resistance of the input optocoupler is 100kΩ, and the return voltage of the optocoupler is 110V, then in the event of a single-point ground fault in this DC system:

[0005]

[0006]

[0007] The return value U represents the operating return voltage of the input optocoupler, the initial value U refers to the initial voltage applied to the input optocoupler, which is equal to the rated voltage of the DC circuit, R is the resistance of the input optocoupler, and C is the capacitance of the input optocoupler.

[0008] The voltage will only drop below the return voltage after t = 10ms, so the input optocoupler will flip. If no measures are taken, it will lead to the malfunction protection falsely starting and outputting, but the relay protection input circuit or protection program does not have corresponding anti-interference measures. Summary of the Invention

[0009] To address the shortcomings of existing technologies, this invention provides a method and system for preventing false tripping of DC grounding relay protection. This method is used for grounding of DC systems in power substations and can prevent false tripping of protection caused by short-term conduction of cable circuits such as substation malfunction start-up circuits, control box tripping circuits, and protection remote tripping circuits due to the influence of grounding capacitance.

[0010] To achieve the above objectives, the present invention adopts the following technical solution:

[0011] A method for preventing maloperation of DC grounding relay protection, based on the characteristics of capacitor charging and discharging and the fault characteristics of the power system, implements the following different anti-interference strategies for intelligent discrimination tripping circuits and non-discrimination direct tripping circuits:

[0012] For intelligent tripping circuits, a combination of time delay and fault diagnosis is used to prevent false tripping of DC grounding relay protection.

[0013] For direct tripping circuits without discrimination, delay and high-power tripping are used to prevent false tripping of DC grounding relay protection.

[0014] The present invention further includes the following preferred embodiments:

[0015] Preferably, for the intelligent tripping circuit, after the fault detection action, the relay protection is briefly opened before the intelligent tripping detection is initiated. After the short-term opening delay reaches the set time, the protection is locked, waiting for the next opening. Specifically, this includes the following steps:

[0016] Step 1: The substation relay protection device collects the current and voltage data of the branch circuit;

[0017] Step 2: Calculate fault identification indicators based on the current and voltage data of the branch, and combine them with fault criteria to identify power system faults;

[0018] Step 3: If a power system fault occurs, the protection will be briefly activated, proceed to step 4; otherwise, return to step 1.

[0019] Step 4: Determine if the relay protection has tripped. If it has, proceed to step 5 after the intelligent tripping; otherwise, return to step 1.

[0020] Step 5: Determine whether the protection short-term opening delay time has reached the set time. If yes, proceed to step 6; otherwise, return to step 4 within the protection opening time period.

[0021] Step 6: Protection interlock, return to step 1, and re-execute the intelligent trip circuit anti-interference strategy.

[0022] Preferably, in step 2, the fault discrimination indicators include zero-sequence current, negative-sequence current, differential current, braking current, zero-sequence voltage, and negative-sequence voltage, and their calculation formulas are as follows:

[0023] I0=(I A +I B +I C ) / 3

[0024] I2=(I A +IB e j240 +I C e j120 ) / 3

[0025] I d =I1+I2+…+I n

[0026] I f =|I1|+|I2|+…+|I n |

[0027] U0=(U A +U B +U C ) / 3

[0028] U2=(U A +U B e j240 +U C e j120 ) / 3

[0029] Among them, I A I B I C The currents are for the three phases A, B, and C.

[0030] I0 and I2 are the zero-sequence current and the negative-sequence current, respectively;

[0031] I1, I2 and I n The currents in the first to nth paths of the differential element;

[0032] I d I f These are the differential current and the braking current, respectively.

[0033] U A U B U C The voltages are for phases A, B, and C.

[0034] U0 and U2 are the zero-sequence voltage and the negative-sequence voltage, respectively.

[0035] Preferably, the fault criteria include overcurrent fault criteria, undervoltage fault criteria, voltage cycle change fault criteria, and current cycle change fault criteria, and each fault criterion adopts an "OR" logical relationship.

[0036] Preferably, the overcurrent fault criterion is:

[0037] I c >I set

[0038] In the formula, I c It can be phase current, zero-sequence current, negative-sequence current, or differential current;

[0039] I set This is the action threshold.

[0040] Preferably, the low-voltage fault criterion is:

[0041] |U ph |≤U Pzd

[0042] |U2|≥U 2zd

[0043] |3U0|≥U 0zd

[0044] In the formula, U ph Let be the phase voltage of any phase;

[0045] U Pzd This is the phase voltage setting value;

[0046] U2 is a negative sequence voltage;

[0047] U 2zd This is the negative sequence voltage setting value;

[0048] U0 is the zero-sequence voltage;

[0049] U 0zd This is the zero-sequence voltage setting value.

[0050] Preferably, the voltage cycle sudden change fault criterion is:

[0051] U ph >3V and ΔU ph >U set

[0052] In the formula, U ph This represents the phase voltage of the current cycle;

[0053] ΔU ph Let ΔU be the single-cycle voltage change, satisfying ΔU ph =|U ph -U ph-T |-|U ph-T -U ph-2T |;

[0054] Among them, U ph-T This is the phase voltage of the previous cycle;

[0055] U ph-2T This represents the phase voltage of the first two cycles;

[0056] U set Set a value for voltage fluctuation.

[0057] Preferably, the fault criterion for sudden current cycle changes is:

[0058] ||I d -I d-T |-|I d-T -I d-2T ||>I dset

[0059] ||I f -I f-T |-|I f-T -I f-2T ||>I fset

[0060] Among them, I d This is the current differential current;

[0061] I d-T This is the differential current of the previous cycle;

[0062] I d-2T This is the differential current for the first two cycles;

[0063] I dset Set a value for the differential mutation amount;

[0064] I f This is the current braking current;

[0065] I f-T This is the braking current for the previous cycle;

[0066] I f-2T This is the braking current for the first two cycles;

[0067] I fset Set a value for the sudden change in braking current.

[0068] Preferably, for direct tripping circuits without discrimination, the DC grounding relay protection is prevented from maloperating by delay and high-power initiation tripping. The delay and high-power initiation tripping are implemented through a physical circuit. The process includes connecting the initiation circuit, starting the initiation circuit with high power, starting the relay, performing anti-interference through the anti-interference circuit, reactivating the relay, and tripping the tripping circuit. Anti-interference is achieved through high-power initiation conditions and the delay time of the relay operation.

[0069] A system for preventing maloperation of DC grounding relay protection, the system comprising a trip circuit discrimination module, an intelligent discrimination trip circuit anti-interference module, and a non-discrimination direct trip circuit anti-interference module;

[0070] Among them, the tripping circuit discrimination module is used to distinguish between intelligent discrimination tripping circuits and non-discrimination direct tripping circuits, and enable the anti-interference module of the corresponding circuit according to the discrimination result;

[0071] The intelligent tripping circuit anti-interference module is used to prevent DC grounding relay protection from maloperating by combining time delay and fault judgment tripping for intelligent tripping circuits.

[0072] The interference suppression module for non-discriminatory direct tripping circuits is used to prevent DC grounding relay protection from maloperating by delaying and initiating tripping with high power for non-discriminatory direct tripping circuits.

[0073] The beneficial effects of this invention are compared with those of the prior art:

[0074] This invention incorporates existing relay protection optical isolation input circuit technology and addresses the issue of relay protection device maloperation caused by DC grounding in long cable and large capacitor situations. It proposes different solutions tailored to the different applications of relay protection input circuits, thus preventing catastrophic accidents such as faultless power system tripping and load shedding, and eliminating hidden defects in the safe operation of existing substations. Specifically:

[0075] Based on the characteristics of capacitor charging and discharging and the fault features of power systems, this invention proposes different solutions for protection fault initiation and high-power delayed initiation for intelligent tripping circuits and direct tripping circuits:

[0076] For intelligent tripping circuits, maloperation is prevented by a combination of time delay and fault diagnosis: fault diagnosis is performed based on overcurrent fault criteria, undervoltage fault criteria, voltage cycle change fault criteria, and current cycle change fault criteria. After the fault diagnosis is activated, the relay protection is briefly opened before the intelligent tripping diagnosis is initiated. After the short-term opening delay of the protection reaches the set time, the protection is locked and waits for the next opening.

[0077] For non-discriminatory direct tripping circuits, maloperation is prevented by delay and high-power start-up tripping: delay and high-power start-up tripping are implemented through physical circuits. The process includes connecting the start-up circuit, starting the start-up circuit with high power, starting the start-up relay, performing anti-interference through the anti-interference circuit, re-operating the re-operating relay, and tripping the tripping circuit. Anti-interference is achieved through high-power start-up conditions and the delay time of relay operation.

[0078] Based on the above scheme, even if a substation experiences a DC grounding and has long cables with large capacitance, the correct operation of the relay protection can be ensured through time delay, fault start-up, and power start-up measures, thus avoiding large-scale power outages caused by incorrect tripping. Attached Figure Description

[0079] Figure 1 This is the logic diagram of the intelligent tripping circuit anti-interference strategy;

[0080] Figure 2 This is a schematic diagram illustrating the principle of DC grounding causing malfunction of the input circuit.

[0081] Figure 3 This is the logic diagram for preventing malfunction of the intelligent trip circuit;

[0082] Figure 4 The logic of the non-discriminatory tripping circuit is shown in the diagram;

[0083] Figure 5 This is a schematic diagram of a high-power anti-interference circuit design. Detailed Implementation

[0084] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The embodiments described in this application are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, other embodiments obtained by those skilled in the art without creative effort are all within the protection scope of this invention.

[0085] Embodiment 1 of the present invention provides a method for preventing maloperation of DC grounding relay protection. In a preferred but non-limiting embodiment of the present invention, the method implements the following different anti-interference strategies for intelligent discrimination tripping circuits and non-discrimination direct tripping circuits based on the characteristics of capacitor charging and discharging and the fault characteristics of power systems:

[0086] For intelligent tripping circuits, a combination of time delay and fault diagnosis is used to prevent false tripping of DC grounding relay protection.

[0087] For direct tripping circuits without discrimination, delay and high-power tripping are used to prevent false tripping of DC grounding relay protection.

[0088] Among them, intelligent tripping circuit refers to the following: in the tripping circuit, there is a CPU processing intermediate link between the start input and the protection trip output. After the relay protection device receives the tripping signal of the circuit, it does not trip directly.

[0089] A direct tripping circuit without discrimination refers to a circuit that is entirely physical, where the protection device trips directly without intelligent CPU signal processing.

[0090] More preferably, for the intelligent tripping circuit, after the fault detection action, the relay protection is briefly opened before the intelligent tripping detection is initiated. After the short-term opening delay of the protection reaches the set time, the protection continues to be blocked and waits for the next opening.

[0091] More preferably, such as Figure 1 As shown, for the intelligent tripping circuit, the DC grounding relay protection is prevented from maloperating by combining time delay and fault diagnosis tripping. Specifically, the steps include:

[0092] Step 1: The substation relay protection device collects the current and voltage data of the branch circuit;

[0093] Step 2: Calculate fault identification indicators based on the current and voltage data of the branch, and combine them with fault criteria to identify power system faults;

[0094] The fault discrimination indicators include zero-sequence current, negative-sequence current, differential current, braking current, zero-sequence voltage, and negative-sequence voltage, and their calculation formulas are as follows:

[0095] I0=(I A +I B +I C ) / 3

[0096] I2=(I A +I B e j240 +I C e j120 ) / 3

[0097] I d =I1+I2+…+I n

[0098] I f =|I1|+|I2|+…+|I n |

[0099] U0=(U A +U B +U C ) / 3

[0100] U2=(U A +U B e j240 +U C e j120 ) / 3

[0101] Among them, I A I B I C The three-phase currents A, B, and C of the branch are given.

[0102] I0 and I2 are the zero-sequence current and the negative-sequence current, respectively;

[0103] I1, I2 and I n The currents in the first to nth paths of the differential element;

[0104] I d I f These are the differential current and the braking current, respectively.

[0105] U A U B U C The voltages of the three phases A, B, and C of the busbar;

[0106] U0 and U2 are the zero-sequence voltage and the negative-sequence voltage, respectively.

[0107] The fault criteria include overcurrent fault criteria, undervoltage fault criteria, voltage cycle change fault criteria, and current cycle change fault criteria. Each fault criterion adopts an "OR" logic relationship, that is, if any criterion is activated, the relay protection will be opened for a short time, and the intelligent tripping judgment will be initiated. After the delay, the protection will be re-locked and wait for the next opening.

[0108] 1) The overcurrent fault criterion is:

[0109] I c >I set

[0110] In the formula, I c It can be phase current, zero-sequence current, negative-sequence current, or differential current;

[0111] I set This is the action threshold, with a value ranging from 0.1 to 20I. n , where I n The rated current is 5A or 1A.

[0112] The setting of the operating threshold value varies depending on the type of protection. Zero-sequence current, negative-sequence current, and differential current reflect the fault state of the current system. The setting value is relatively small, only needing to be greater than the error current of the normal system operation. Overcurrent protection needs to avoid the load current of normal operation.

[0113] 2) The criterion for low voltage fault is:

[0114] |U ph |≤U Pzd

[0115] |U2|≥U 2zd

[0116] |3U0|≥U 0zd

[0117] In the formula, U ph Let be the phase voltage of any phase;

[0118] U Pzd This is the phase voltage setting value;

[0119] U2 is the negative sequence voltage of the bus;

[0120] U 2zd This is the negative sequence voltage setting value;

[0121] U0 is the zero-sequence voltage of the bus;

[0122] U 0zd This is the zero-sequence voltage setting value.

[0123] Furthermore, the multi-cycle fluctuations of braking current, differential current, and voltage can be used to sensitively reflect the occurrence of power system faults and eliminate the impact of grid interference.

[0124] 3) Taking a 2-cycle example, the fault criterion for voltage cycle abrupt change is:

[0125] U ph >3V and ΔU ph >U set

[0126] In the formula, U ph This represents the phase voltage of the current cycle;

[0127] ΔU ph Let ΔU be the single-cycle voltage change, satisfying ΔU ph =|U ph -U ph-T |-|U ph-T -U ph-2T |;

[0128] Among them, U ph This represents the phase voltage of the current cycle;

[0129] U ph-T This is the phase voltage of the previous cycle;

[0130] U ph-2T This represents the phase voltage of the first two cycles;

[0131] U set A value is set for the voltage surge, ranging from 0.1 to 1U. n U n The rated voltage is 57.7V or 100V.

[0132] 4) The fault criterion for sudden change in current cycle is:

[0133] ||I d -I d-T |-|I d-T -I d-2T ||>I dset

[0134] ||I f -I f-T |-|I f-T -I f-2T ||>I fset

[0135] Among them, I d This is the differential current for the current cycle;

[0136] I d-T This is the differential current of the previous cycle;

[0137] I d-2T This is the differential current for the first two cycles;

[0138] I dset The differential mutation amount is set to a value ranging from 0.1 to 0.5I. n , where I n The rated current is 5A or 1A.

[0139] I f This represents the braking current for the current cycle.

[0140] I f-T This is the braking current for the previous cycle;

[0141] I f-2T This is the braking current for the first two cycles;

[0142] I fset A set value is set for the sudden change in braking current, with a range of 0.1 to I. n , where I n The rated current is 5A or 1A. The braking current includes the load current and its value range is greater than that of the differential current.

[0143] Step 3: If a power system fault occurs, the protection will be briefly activated, proceed to step 4; otherwise, return to step 1.

[0144] Step 4: Determine if the relay protection has tripped. If it has, proceed to step 5 after the intelligent tripping; otherwise, return to step 1.

[0145] Step 5: Determine whether the protection short-term opening delay time has reached the set time. If yes, proceed to step 6; otherwise, return to step 4 within the protection opening time period.

[0146] The set time is based on the duration from the occurrence of a power system fault to its clearing, and is generally set to no more than 10 seconds, preferably 2 seconds.

[0147] Step 6: The protection is re-locked, return to step 1, and re-execute the intelligent judgment trip circuit anti-interference strategy.

[0148] The anti-maloperation logic of the intelligent trip circuit is as follows: Figure 3 As shown, Tset1 is the short-term opening time of the protection after the fault criterion is activated. It is generally considered based on the maximum fault time of the power system, and a time of 2-10 seconds is recommended. Tset2 is the anti-malfunction delay time, generally less than 50ms. The protection can only trip under the condition that the relay protection criterion operates and the input initiation is effective. Here, the relay protection criterion refers to protection that requires input initiation for discrimination, such as circuit breaker failure protection, remote tripping with local discrimination protection, etc. It generally includes fault discrimination based on voltage, current, and zero-sequence current, and its initiation sensitivity is lower than that of fault discrimination initiation elements.

[0149] For direct tripping circuits without discrimination, time-delay and high-power initiation tripping are achieved through physical circuits:

[0150] The entire process includes connecting the start-up circuit, starting the start-up circuit with high power, activating the start-up relay, using the anti-interference circuit for anti-interference, activating the re-operation relay, and tripping the trip circuit. Anti-interference is achieved through high-power start-up conditions and the delay time of relay operation.

[0151] Undiscriminate tripping circuit logic, such as Figure 4 As shown, the starting circuit has its own power and delay circuit. The starting relay starts the re-operating relay through the anti-interference circuit. After the re-operating relay operates, the contacts trip directly.

[0152] The design principle of high-power anti-interference circuit is as follows: Figure 5 As shown, its loop parameters are:

[0153] R1 = R3 = J1 = J2 = 35KΩ, R2 = 6.2KΩ, R4 = 200Ω, relay average operating time 16ms, average return time 16ms, operating voltage 136V, return voltage 44V, relay starting power 8.8W, return power 2W. The technical specifications exceed the required standards and prevent AC / DC aliasing.

[0154] 1) When the external contact is closed, the starting circuit is connected first, and at this time the shunt resistor R2 plays the role of shunt.

[0155] When operating at rated voltage, the starting power is 8-9W.

[0156] 2) The relay's contact actuation time is approximately 5ms. On the one hand, the relay's actuation time can be used to avoid system interference; on the other hand, the interference must reach the starting power for the starting circuit to operate reliably.

[0157] 3) If the starting circuit is activated, contact J1-2 closes, starting relay J2 and outputting the reactivation contact. Normally closed contact J1-1 opens, cutting off the shunt circuit to prevent long-term shunt operation during normal operation.

[0158] When operating at rated voltage, the operating power is 1.60W.

[0159] 4) When the J1-2 contact closes, the J2 relay is activated. The J2 relay has an operating time of 5ms, which can be further delayed to avoid system interference.

[0160] 5) R4 and capacitor C form an anti-interference circuit to control the input return time.

[0161] Embodiment 2 of the present invention provides a system for preventing DC grounding relay protection from maloperating in order to implement the above method. The system includes a trip circuit discrimination module, an intelligent discrimination trip circuit anti-interference module, and a non-discrimination direct trip circuit anti-interference module.

[0162] Among them, the tripping circuit discrimination module is used to distinguish between intelligent discrimination tripping circuits and non-discrimination direct tripping circuits, and enable the anti-interference module of the corresponding circuit according to the discrimination result;

[0163] The intelligent tripping circuit anti-interference module is used to prevent DC grounding relay protection from maloperating by combining time delay and fault judgment tripping for intelligent tripping circuits.

[0164] The interference suppression module for non-discriminatory direct tripping circuits is used to prevent DC grounding relay protection from maloperating by delaying and initiating tripping with high power for non-discriminatory direct tripping circuits.

[0165] The beneficial effects of this invention are compared with those of the prior art:

[0166] This invention incorporates existing relay protection optical isolation input circuit technology and addresses the issue of relay protection device maloperation caused by DC grounding in long cable and large capacitor situations. It proposes different solutions tailored to the different applications of relay protection input circuits, thus preventing catastrophic accidents such as faultless power system tripping and load shedding, and eliminating hidden defects in the safe operation of existing substations. Specifically:

[0167] Based on the characteristics of capacitor charging and discharging and the fault features of power systems, this invention proposes different solutions for protection fault initiation and high-power delayed initiation for intelligent tripping circuits and direct tripping circuits:

[0168] For intelligent tripping circuits, maloperation is prevented by a combination of time delay and fault diagnosis: fault diagnosis is performed based on overcurrent fault criteria, undervoltage fault criteria, voltage cycle change fault criteria, and current cycle change fault criteria. After the fault diagnosis is activated, the relay protection is briefly opened before the intelligent tripping diagnosis is initiated. After the short-term opening delay of the protection reaches the set time, the protection is locked and waits for the next opening.

[0169] For non-discriminatory direct tripping circuits, maloperation is prevented by delay and high-power start-up tripping: delay and high-power start-up tripping are implemented through physical circuits. The process includes connecting the start-up circuit, starting the start-up circuit with high power, starting the start-up relay, performing anti-interference through the anti-interference circuit, re-operating the re-operating relay, and tripping the tripping circuit. Anti-interference is achieved through high-power start-up conditions and the delay time of relay operation.

[0170] Based on the above scheme, even if a substation experiences a DC grounding and has long cables with large capacitance, the correct operation of the relay protection can be ensured through time delay, fault start-up, and power start-up measures, thus avoiding large-scale power outages caused by incorrect tripping.

[0171] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this disclosure.

[0172] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0173] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0174] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0175] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0176] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0177] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0178] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0179] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A method for preventing maloperation of DC grounding relay protection, characterized in that: Based on the characteristics of capacitor charging and discharging and the fault characteristics of power systems, the following different anti-interference strategies are implemented for intelligent tripping circuits and non-discriminatory direct tripping circuits: For intelligent tripping circuits, a combination of time delay and fault diagnosis is used to prevent false tripping of DC grounding relay protection. For direct tripping circuits without discrimination, delay and high-power tripping are used to prevent false tripping of DC grounding relay protection. The fault discrimination combination includes overcurrent fault criteria, undervoltage fault criteria, voltage periodic change fault criteria, and current periodic change fault criteria, and each fault criterion adopts an "OR" logical relationship; The low-voltage fault criterion is as follows: In the formula, Let be the phase voltage of any phase; This is the phase voltage setting value; It is a negative sequence voltage; This is the negative sequence voltage setting value; It is the zero-sequence voltage; This is the zero-sequence voltage setting value; The fault criterion for voltage periodic sudden change is: In the formula, This represents the phase voltage of the current cycle; The voltage single-cycle change amount satisfies ;in, This is the phase voltage of the previous cycle; This represents the phase voltage of the first two cycles; Set a value for voltage surge; The fault criterion for sudden current cycle change is: in, This is the current differential current; This is the differential current of the previous cycle; This is the differential current for the first two cycles; Set a value for the differential mutation amount; This is the current braking current; This is the braking current for the previous cycle; This is the braking current for the first two cycles; Set a value for the sudden change in braking current.

2. The method for preventing maloperation of DC grounding relay protection according to claim 1, characterized in that: For intelligent tripping circuits, after fault detection, the relay protection briefly opens before intelligent tripping is initiated. After the short-term opening delay reaches the set time, the protection is locked, waiting for the next opening. The specific steps include: Step 1: The substation relay protection device collects the current and voltage data of the branch circuit; Step 2: Calculate fault identification indicators based on the current and voltage data of the branch, and combine them with fault criteria to identify power system faults; Step 3: If a power system fault occurs, the protection will be briefly activated, proceed to step 4; otherwise, return to step 1. Step 4: Determine if the relay protection has tripped. If it has, proceed to step 5 after the intelligent tripping; otherwise, return to step 1. Step 5: Determine whether the protection short-term opening delay time has reached the set time. If yes, proceed to step 6; otherwise, return to step 4 within the protection opening time period. Step 6: Protection interlock, return to step 1, and re-execute the intelligent trip circuit anti-interference strategy.

3. The method for preventing maloperation of DC grounding relay protection according to claim 2, characterized in that: In step 2, the fault discrimination indicators include zero-sequence current, negative-sequence current, differential current, braking current, zero-sequence voltage, and negative-sequence voltage, and their calculation formulas are as follows: in, , , The three-phase currents are A, B, and C. , These are the zero-sequence current and the negative-sequence current, respectively. , and The current of the differential element from the first to the nth path , These are the differential current and the braking current, respectively. , , The voltages are for phases A, B, and C. These are the zero-sequence voltage and the negative-sequence voltage.

4. The method for preventing maloperation of DC grounding relay protection according to claim 1, characterized in that: The overcurrent fault criterion is as follows: In the formula, Phase current, zero-sequence current, negative-sequence current, or differential current This is the action threshold.

5. A method for preventing maloperation of DC grounding relay protection according to claim 1, characterized in that: For direct tripping circuits without discrimination, delay and high-power start-up tripping are used to prevent false tripping of DC grounding relay protection. The delay and high-power start-up tripping are implemented through a physical circuit. The process includes connecting the start-up circuit, starting the start-up circuit with high power, starting the start-up relay, performing anti-interference through the anti-interference circuit, re-operating the re-operating relay, and tripping the tripping circuit. Anti-interference is achieved through high-power start-up conditions and the delay time of the relay operation.

6. A system for preventing maloperation of DC grounding relay protection for implementing the method according to any one of claims 1-5, characterized in that: The system includes a trip circuit discrimination module, an intelligent trip circuit discrimination anti-interference module, and a direct trip circuit anti-interference module without discrimination. Among them, the tripping circuit discrimination module is used to distinguish between intelligent discrimination tripping circuits and non-discrimination direct tripping circuits, and enable the anti-interference module of the corresponding circuit according to the discrimination result; The intelligent tripping circuit anti-interference module is used to prevent DC grounding relay protection from maloperating by combining time delay and fault judgment tripping for intelligent tripping circuits. The interference suppression module for non-discriminatory direct tripping circuits is used to prevent DC grounding relay protection from maloperating by delaying and initiating tripping with high power for non-discriminatory direct tripping circuits.

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