A power element topology circuit

Abstract

The present application relates to the technical field of electricity, and especially relates to a power element topology circuit, which comprises a multi-stage decoupling capacitor loop, a semiconductor switch module and at least two pins; the multi-stage decoupling capacitor loop is connected with the semiconductor switch module; the semiconductor switch module comprises at least two switches; the at least two pins are short-circuited between the at least two switches, and are used for providing a current flowing function in the case that the semiconductor switch module is turned on. The problem of fast power switch loss can be solved. Due to the current flowing effect of the at least two pins, the inductance in the turned-off loop in the semiconductor switch module is reduced, and then the peak voltage in the loop can be lowered, the safety of a working system in which the power element is located during working is improved, the high-frequency electromagnetic interference is inhibited, the inductance in the turned-on loop in the semiconductor switch module is larger than that in the turned-off loop, and the loss of the switch in the semiconductor switch module can be reduced.

Description

Technical Field

[0001] This invention relates to the field of electrical technology, and more particularly to a power element topology circuit. Background Technology

[0002] Power components are devices in an apparatus that reflect or detect the electrical power of a particular device or circuit. They are generally used in power electrical systems to form different circuit topologies and are the core components for realizing power conversion. To achieve higher power levels in power electronic systems, more switching devices are connected in parallel to achieve larger output current and power levels. Taking the basic unit of circuit topology, the half-bridge topology, as an example, each power component contains two power switches. Due to the increasingly faster switching speed of power switches and the existence of parasitic parameters (mainly parasitic inductance), each switching process causes severe voltage spikes on the device.

[0003] Therefore, in order to protect the power switch, the circuit containing the power switch is usually designed to be as short as possible in traditional power components, so as to reduce parasitic parameters in the circuit and thus reduce peak voltage.

[0004] However, designing the power switch circuit to be as short as possible results in a shorter distance between power switches, which leads to higher temperatures during rapid switching and causes faster power switch losses. Summary of the Invention

[0005] This application provides a power element topology circuit that can solve the problem of rapid power switching losses. This application provides the following technical solution:

[0006] In a first aspect, this application provides a semiconductor module, including: a multi-stage decoupling capacitor circuit, a semiconductor switch module, and at least two pins;

[0007] The multi-stage decoupling capacitor circuit is connected to the semiconductor switch module; the semiconductor switch module includes at least two switches.

[0008] The at least two pins are shorted between the at least two switches to provide current flow when the semiconductor switch module is turned on.

[0009] Optionally, the at least two switches include a first switch Q1, a second switch Q2, and a unidirectional conducting device D1 disposed between the first switch Q1 and the second switch Q2;

[0010] The at least two pins include pin AC1 and pin AC2;

[0011] The at least two pins are shorted between the at least two switches, including:

[0012] The pin AC1 is shorted to the semiconductor switch module and is located between the first switch Q1 and the unidirectional conduction device D1;

[0013] The pin AC2 is shorted to the semiconductor switch module and is located between the second switch Q2 and the unidirectional conduction device D1.

[0014] Optionally, pin AC1 is used to provide current flow when the first switch Q1 is turned on;

[0015] Accordingly, pin AC2 is used to provide current flow when the second switch Q2 is turned on.

[0016] Optionally, the type of pin AC1 is the same as the type of pin AC2.

[0017] Optionally, the multi-stage decoupling capacitor circuit includes: a first branch, a second branch, and a third branch; the second branch is connected to the semiconductor switch module to form a first circuit; the second branch is also connected to the semiconductor switch module to form a second circuit.

[0018] Optionally, the first branch includes a capacitor Cbus, which includes an electrolytic capacitor or a film capacitor;

[0019] The second branch includes capacitor Ce2, which may be a film capacitor or a ceramic capacitor;

[0020] The third branch includes capacitor Ce1, which is a ceramic capacitor.

[0021] Optionally, the at least two switches further include a third switch Q3, a fourth switch Q4, and unidirectional conducting devices D2 and D3 disposed between the first switch Q1 and the second switch Q2;

[0022] Optionally, the at least two pins further include pin AC3, pin AC4, and pin AC5;

[0023] The pin AC3 is located between the first switch Q1 and the unidirectional conducting device D2;

[0024] The pin AC4 is positioned between the unidirectional conducting device D2 and the unidirectional conducting device D3.

[0025] The pin AC5 is positioned between the unidirectional conducting device D3 and the second switch Q2.

[0026] Optionally, the third branch is encapsulated inside the semiconductor switching module.

[0027] Optionally, the at least two switches include one of the following: silicon carbide metal-oxide-semiconductor field-effect transistors, insulated-gate bipolar transistors, silicon metal-oxide-semiconductor field-effect transistors, or gallium nitride transistors.

[0028] The beneficial effects of this application are as follows: A multi-stage decoupling capacitor circuit, a semiconductor switching module, and at least two pins are used; the multi-stage decoupling capacitor circuit is connected to the semiconductor switching module; the semiconductor switching module includes at least two switches; at least two pins are shorted between the at least two switches to provide current-carrying functionality when the semiconductor switching module is on. This solves the problem of rapid power switch losses. By shorting at least two pins to the semiconductor switching module, the inductance in the off-circuit of the semiconductor switching module is reduced due to the current-carrying effect of the at least two pins, thereby lowering the peak voltage in the circuit, improving the safety of the operating system where the power element is located, and suppressing high-frequency electromagnetic interference. The inductance in the on-circuit of the semiconductor switching module is larger than the inductance in the off-circuit, which can reduce the switching losses in the semiconductor switching module; at the same time, it can fully utilize the high-speed characteristics of the switches and improve the system conversion efficiency. Attached Figure Description

[0029] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0030] Figure 1 This is a circuit diagram of a power element topology circuit provided in one embodiment of this application;

[0031] Figure 2 This is a circuit diagram of another power element topology circuit provided in one embodiment of this application;

[0032] Figure 3 This is a circuit diagram of another power element topology circuit provided in one embodiment of this application;

[0033] Figure 4 This is a line graph of the power element topology circuit provided in one embodiment of this application. Detailed Implementation

[0034] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. The application will be described in detail below with reference to the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0035] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0036] In this application, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used in relation to the direction shown in the accompanying drawings, or in relation to the vertical, perpendicular, or gravitational direction of the component itself; similarly, for ease of understanding and description, "inner" and "outer" refer to the inner and outer contours of each component itself, but the above directional terms are not used to limit this application.

[0037] First, let me introduce some of the terms used in this application.

[0038] Electromagnetic interference (EMI) refers to the interference that electronic products can cause to other electronic products in the vicinity. Related to this are EMC standards. It is a common problem encountered by electronic and electrical products. Types of interference include conducted interference and radiated interference.

[0039] Inductance: Inductance is a property of a closed circuit and a physical quantity. When current flows through a coil, it induces a magnetic field in the coil, which in turn generates an induced current that opposes the current flowing through the coil. It is a circuit parameter describing the induced electromotive force effect in the same coil or another coil caused by a change in coil current. Inductance is a general term for self-inductance and mutual inductance.

[0040] Lead finger: Also called a pin. It's the connection between the internal circuitry of an integrated circuit (chip) and the external circuitry; all the leads constitute the chip's interface. The end of the lead is soldered to a pad on the printed circuit board to form a solder joint. Leads can be divided into bottom, toe, and side sections.

[0041] Parasitic parameters include parasitic resistance, parasitic capacitance, and parasitic inductance. At high frequencies, each component in a converter possesses certain parasitic parameters. These parameters interact, causing a series of complex circuit operating mode changes, slowing down the circuit's operation and altering its frequency response. The resulting energy loss is called parasitic loss.

[0042] The power element topology circuit provided in this application will be described in detail below.

[0043] like Figures 1 to 2 As shown, the power element topology circuit provided in the embodiments of this application includes at least: a multi-stage decoupling capacitor circuit 110, a semiconductor switching module 120, and at least two pins. The multi-stage decoupling capacitor circuit 110 is connected to the semiconductor switching module 120.

[0044] In this embodiment, the semiconductor switch module 120 includes at least two switches; at least two pins are shorted between the at least two switches to provide current flow when the semiconductor switch module is turned on.

[0045] Among them, at least two switches can be of the same or different types.

[0046] Optionally, at least two switches include one of the following: silicon carbide metal-oxide-semiconductor field-effect transistors, insulated-gate bipolar transistors, silicon metal-oxide-semiconductor field-effect transistors, or gallium nitride transistors.

[0047] In actual implementation, at least two switches can also be other types of transistors. This embodiment does not limit the type of at least two switches.

[0048] In this embodiment, reference Figure 1 The multi-stage decoupling capacitor circuit 110 includes a first branch, a second branch, and a third branch. The first branch includes capacitor Cbus, the second branch includes capacitor Ce2, and the third branch includes capacitor Ce1.

[0049] Among them, capacitor Cbus includes electrolytic capacitors or film capacitors; capacitor Ce2 includes film capacitors or ceramic capacitors; capacitor Ce1 includes ceramic capacitors.

[0050] In actual implementation, capacitors Cbus, Ce2, and Ce1 can also be other types of capacitors. This embodiment does not limit the capacitor types of capacitors Cbus, Ce2, and Ce1.

[0051] The second branch is connected to the semiconductor switch module 120 to form the first circuit; the second branch is connected to the semiconductor switch module 120 to form the second circuit.

[0052] Optionally, the third branch is packaged inside the semiconductor switching module.

[0053] In this embodiment, reference Figure 2 The semiconductor switch module 120 includes a first switch Q1, a second switch Q2, and a unidirectional conducting device D1 disposed between the first switch Q1 and the second switch Q2.

[0054] Accordingly, at least two pins include pin AC1 and pin AC2. Pin AC1 and pin AC2 are of the same type.

[0055] Specifically, at least two pins are shorted between at least two switches, including: pin AC1 is shorted to the semiconductor switch module and is located between the first switch Q1 and the unidirectional conducting device D1; pin AC2 is shorted to the semiconductor switch module 120 and is located between the second switch Q2 and the unidirectional conducting device D1.

[0056] Pin AC1 is used to provide current flow when the first switch Q1 is turned on; correspondingly, pin AC2 is used to provide current flow when the second switch Q2 is turned on.

[0057] In this embodiment, the difference between the power element's circuit being on and off can be achieved through pin AC1 and the parasitic inductances Lpin3 and Lpin4 introduced onto AC2. For example... Figure 4 As shown, the turn-on loss can be reduced by more than 60%, and the total switching loss can be reduced by more than 40%.

[0058] Due to the current-carrying effect of pins AC1 and AC2, the inductance in the off-circuit of the semiconductor switch module 120 is reduced, thereby lowering the peak voltage in the circuit, improving the safety of the operating system containing the power components, and suppressing high-frequency electromagnetic interference. Simultaneously, the inductance in the on-circuit of the semiconductor switch module 120 is larger than that in the off-circuit, reducing the switching losses in the semiconductor switch module 120, thus fully utilizing the high-speed characteristics of the switch and improving system switching efficiency.

[0059] In addition, in this embodiment, parasitic inductance also includes parasitic inductance caused by the internal wiring of the semiconductor switch module 120, parasitic inductance on the module package pins of the semiconductor switch module 120, and parasitic inductance on the multilayer circuit board or the stacked busbar.

[0060] refer to Figure 1 The parasitic inductances caused by the internal wiring of the semiconductor switch module 120 include inductors LDL, LSL, LO1, and LO2; the parasitic inductances on the module package pins include inductors Lpin1, Lpin2, and Lpin3; and the parasitic inductances on the multilayer circuit board or stacked busbar include inductors LDL, LSL, LO1, and LO2.

[0061] The module package pins include pins DC+, DC-, and AC, which represent different power leads on the module package.

[0062] In other embodiments, reference is made to Figure 4The semiconductor switch module 120 also includes a third switch Q3, a fourth switch Q4, and unidirectional conducting devices D2 and D3 disposed between the first switch Q1 and the second switch Q2.

[0063] Accordingly, at least two pins also include pins AC3, AC4, and AC5. Pin AC3 is positioned between the first switch Q1 and the unidirectional conducting device D2, pin AC4 is positioned between the unidirectional conducting device D2 and the unidirectional conducting device D3, and pin AC5 is positioned between the unidirectional conducting device D3 and the second switch Q2. Pins AC3, AC4, and AC5 are of the same type.

[0064] In summary, the power element topology circuit provided in this embodiment, through a multi-stage decoupling capacitor circuit, a semiconductor switching module, and at least two pins; the multi-stage decoupling capacitor circuit is connected to the semiconductor switching module; the semiconductor switching module includes at least two switches; at least two pins are shorted between the at least two switches to provide current-carrying functionality when the semiconductor switching module is on. This can solve the problem of rapid power switch losses. By shorting at least two pins to the multi-stage decoupling capacitor circuit or the semiconductor switching module, the inductance in the off-circuit of the semiconductor switching module is reduced due to the current-carrying effect of the at least two pins, thereby reducing the peak voltage in the circuit, improving the safety of the operating system where the power element is located, and suppressing high-frequency electromagnetic interference. The inductance in the on-circuit of the semiconductor switching module is larger than the inductance in the off-circuit, which can reduce the switching losses in the semiconductor switching module; at the same time, it can also fully utilize the high-speed characteristics of the switches and improve the system conversion efficiency.

[0065] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0066] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A power element topology circuit, characterized in that, include: Multi-stage decoupling capacitor circuit, semiconductor switch module, and at least two pins; The multi-stage decoupling capacitor circuit is connected to the semiconductor switch module; the semiconductor switch module includes at least two switches. The at least two pins are shorted between the at least two switches to provide current flow when the semiconductor switch module is turned on. The semiconductor switch module includes a first switch Q1, a second switch Q2, and a unidirectional conducting device D1 disposed between the first switch Q1 and the second switch Q2. The cathode of the unidirectional conducting device D1 is connected to the first switch Q1, and the anode of the unidirectional conducting device D1 is connected to the second switch Q2. The at least two pins include pin AC1 and pin AC2. The at least two pins are shorted between the at least two switches, including: pin AC1 is shorted to the semiconductor switch module and disposed between the first switch Q1 and the unidirectional conducting device D1; pin AC2 is shorted to the semiconductor switch module and disposed between the second switch Q2 and the unidirectional conducting device D1. Alternatively, the semiconductor switch module includes a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4, and two unidirectional conducting devices D2 and D3 disposed between the first switch Q1 and the second switch Q2. The cathode of the unidirectional conducting device D2 is connected to the first switch Q1, the anode of the unidirectional conducting device D2 is connected to the cathode of the unidirectional conducting device D3, and the anode of the unidirectional conducting device D3 is connected to the second switch Q2. The at least two pins include pin AC3, pin AC4, and pin AC5. Pin AC3 is disposed between the first switch Q1 and the unidirectional conducting device D2, pin AC4 is disposed between the unidirectional conducting device D2 and the unidirectional conducting device D3, and pin AC5 is disposed between the unidirectional conducting device D3 and the second switch Q2.

2. The power element topology circuit according to claim 1, characterized in that, The pin AC1 is used to provide current flow when the first switch Q1 is turned on. Accordingly, pin AC2 is used to provide current flow when the second switch Q2 is turned on.

3. The power element topology circuit according to claim 1, characterized in that, The type of pin AC1 is the same as the type of pin AC2.

4. The power element topology circuit according to claim 1, characterized in that, The multi-stage decoupling capacitor circuit includes: a first branch, a second branch, and a third branch; the first branch is connected to the semiconductor switch module to form a first circuit; the second branch is connected to the semiconductor switch module to form a second circuit.

5. The power element topology circuit according to claim 4, characterized in that, The first branch includes a capacitor Cbus, which includes an electrolytic capacitor or a film capacitor; The second branch includes capacitor Ce2, which may be a film capacitor or a ceramic capacitor; The third branch includes capacitor Ce1, which is a ceramic capacitor.

6. The power element topology circuit according to claim 5, characterized in that, The third branch is encapsulated inside the semiconductor switching module.

7. The power element topology circuit according to claim 1, characterized in that, The at least two switches include one of the following: silicon carbide metal-oxide-semiconductor field-effect transistors, insulated-gate bipolar transistors, silicon metal-oxide-semiconductor field-effect transistors, or gallium nitride transistors.

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