Asynchronous clock generation apparatus and analog-to-digital converter
By working together with the signal generation module, current source module, asynchronous clock bias module, and hysteresis clock generation module in the asynchronous clock generation device, the problem of low delay adjustment accuracy in the prior art is solved, and high-precision linear delay adjustment and improved analog-to-digital converter sampling rate are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG GEOFORCECHIP TECH CO LTD
- Filing Date
- 2022-09-29
- Publication Date
- 2026-06-09
AI Technical Summary
In existing technologies, voltage-controlled delay and capacitor charging/discharging delay cannot be linearly adjusted, resulting in low accuracy of asynchronous clock frequency adjustment and inaccurate control of delay amount, leading to power waste and reduced sampling rate of analog-to-digital converter.
An asynchronous clock generation device is adopted, including a signal generation module, a current source module, an asynchronous clock bias module, and a hysteresis clock generation module. The target electrical signal is generated through handshake signals and control commands, and the output voltage is adjusted to generate the target clock signal, thereby achieving linear adjustment of the delay and high-precision control.
It improves the accuracy of delay adjustment, achieves linear delay adjustment, reduces power consumption waste, and increases the sampling rate of the analog-to-digital converter.
Smart Images
Figure CN115549658B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic circuit technology, and more specifically, to an asynchronous clock generating device and a method for generating an asynchronous clock. Background Technology
[0002] In successive approximation analog-to-digital converters, a delay unit is usually added at the output to adjust the frequency of the asynchronous clock. The frequency of the asynchronous clock is adjusted by adjusting the delay unit.
[0003] In existing technologies, the delay unit is usually implemented using a voltage-controlled delay circuit or a capacitor charging and discharging circuit to achieve adjustable delay in the circuit.
[0004] However, since neither voltage-controlled delay adjustment nor capacitor charging / discharging delay can achieve linear adjustment of the delay, it is often impossible to accurately adjust the delay amount to the required amount during the adjustment process, resulting in low adjustment accuracy. Summary of the Invention
[0005] The purpose of this application is to provide an asynchronous clock generating device and an analog-to-digital converter that can achieve linear adjustment of delay and improve the accuracy of adjustment.
[0006] The embodiments of this application are implemented as follows:
[0007] One aspect of this application provides an asynchronous clock generating device, including: a signal generating module, a current source module, an asynchronous clock biasing module, a hysteresis clock generating module, and a control module;
[0008] The signal generation module is connected to the current source module, the hysteresis clock generation module, the control module, and external signals respectively. The signal generation module is used to generate a handshake signal based on the external signals, the target clock signal sent by the hysteresis clock generation module, and the control command sent by the control module, and then send the handshake signal to the current source module.
[0009] The current source module is connected to the asynchronous clock bias module. The current source module is used to generate a target electrical signal that meets the control command based on the handshake signal, and send the target electrical signal to the asynchronous clock bias module.
[0010] The asynchronous clock bias module is connected to the hysteresis clock generation module. The asynchronous clock bias module is used to adjust the output voltage according to the target electrical signal, and the hysteresis clock generation module is used to generate the target clock signal based on the adjusted output voltage and send the target clock signal to the signal generation module.
[0011] Optionally, the current source module includes: a power selection unit and a status selection unit; the power selection unit includes multiple power supplies that can be connected.
[0012] The power selection unit is connected to the signal generation module and the status selection unit respectively, and is used to turn on the target power under the action of the handshake signal. The target power is one or more power supplies that can be turned on.
[0013] The state selection unit is connected to the asynchronous clock bias module. The state selection unit is used to switch the working state and generate the target electrical signal under the power supply of the target power supply.
[0014] Optionally, the power selection unit includes: multiple selection switches;
[0015] Each selector switch is connected to a power source.
[0016] Optionally, the state selection unit includes: a first switch transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first module output terminal, and a second module output terminal;
[0017] The first terminal of the first switch is connected to the power selection unit, and the second terminal of the first switch is connected to the third terminal of the first switching transistor.
[0018] The first end of the second switch is connected to the power selection unit, and the second end of the second switch is connected to the first end of the first switching transistor.
[0019] The first end of the third switch is connected to the first end of the first switch tube, and the second end of the third switch is connected to the third end of the first switch tube.
[0020] The first end of the fourth switch is connected to the first end of the first switch tube, and the second end of the fourth switch is connected to the first end of the fifth switch.
[0021] The second terminal of the fifth switch is connected to the first power supply terminal, and the second terminal of the first switch tube is grounded.
[0022] The inputs of the first module's output terminal are connected to the second terminal of the fourth switch and the first terminal of the fifth switch, respectively. The output of the first module's output terminal is connected to the asynchronous clock bias module.
[0023] The input of the second module's output terminal is connected to the third terminal of the first switching transistor, and the output of the second module's output terminal is connected to the asynchronous clock bias module.
[0024] Optionally, the first switch and the fourth switch constitute the first group of switches, and the second switch, the third switch and the fifth switch constitute the second group of switches. Each switch in each group is in the same open / closed state at the same time, and the first group of switches and the second group of switches are in different open / closed states at the same time.
[0025] Optionally, the asynchronous clock bias module includes multiple clock bias circuits;
[0026] The input terminal of each clock bias circuit is connected to the output terminal of the current source module, and the output terminal of each clock bias circuit is connected to the input terminal of the hysteresis clock generation module.
[0027] Optionally, the clock bias circuit includes: a second switch, a third switch, a fourth switch, a first capacitor, a pulse selection unit, a first module input terminal, a second module input terminal, and a third module output terminal;
[0028] The first end of the second switch is connected to the second power supply terminal, the second end of the second switch is connected to the output terminal of the third module, and the third end of the second switch is connected to the pulse selection unit.
[0029] The first terminal of the third switch is connected to the output terminal of the third module, the second terminal of the third switch is connected to the input terminal of the first module, and the third terminal of the third switch is connected to the pulse selection unit.
[0030] The first terminal of the fourth switch is grounded, the second terminal of the fourth switch is connected to the input terminal of the first module, and the third terminal of the fourth switch is connected to the input terminal of the second module.
[0031] The first terminal of the first capacitor is connected to the input terminal of the second module, and the second terminal of the first capacitor is connected to the output terminal of the third module.
[0032] The second module's input terminal is also connected to the third power supply terminal.
[0033] Optionally, the pulse selection unit is a NOR gate circuit;
[0034] The first input terminal of the NOR gate is the enable terminal, and the second input terminal of the NOR gate is the pulse signal selection terminal; the output terminal of the NOR gate is connected to the third terminal of the second switch and the third terminal of the third switch, respectively.
[0035] Optionally, the hysteresis clock generation module includes: a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, a tenth switch, a second capacitor, a first current bias unit, a second current bias unit, and a clock output terminal;
[0036] The first terminal of the fifth switch is grounded, the second terminal of the fifth switch is connected to the first terminal of the first current bias unit, and the third terminal of the fifth switch is connected to the asynchronous clock bias module.
[0037] The first terminal of the sixth switch is connected to the fourth power supply terminal, the second terminal of the sixth switch is connected to the first terminal of the second current bias unit, and the third terminal of the sixth switch is connected to the third terminal of the ninth switch and the third terminal of the tenth switch, respectively.
[0038] The first terminal of the seventh switch is connected to the fourth power supply terminal, the second terminal of the seventh switch is connected to the third terminal of the sixth switch, and the third terminal of the seventh switch is connected to the third terminal of the eighth switch, the second terminal of the first current bias unit, and the second terminal of the second current bias unit.
[0039] The first terminal of the eighth switch is grounded, and the second terminal of the eighth switch is connected to the third terminal of the sixth switch.
[0040] The first terminal of the ninth switch is connected to the fourth power supply terminal, and the second terminal of the ninth switch is connected to the clock output terminal.
[0041] The first terminal of the tenth switch is grounded, and the second terminal of the tenth switch is connected to the clock output terminal.
[0042] The first terminal of the second capacitor is connected to the second terminal of the second current bias unit, and the second terminal of the second capacitor is grounded.
[0043] The first terminal of the first current bias unit is connected to the fourth power supply terminal.
[0044] Optionally, the signal generation module includes: a comparator and a NAND gate circuit;
[0045] The comparator's input is connected to an external signal, its first output is connected to the input of a NAND gate, its second output is connected to a current source module, and its clock is connected to the output of a hysteresis clock generation module.
[0046] The output of the NAND gate is connected to the current source module.
[0047] In another aspect of this application, an analog-to-digital converter is provided, which includes an asynchronous clock generating device and an analog-to-digital conversion circuit, wherein the output terminal of the analog-to-digital conversion circuit is connected to the input terminal of the asynchronous clock generating device.
[0048] The beneficial effects of the embodiments of this application include:
[0049] In the asynchronous clock generation device and analog-to-digital converter provided in this application embodiment, a handshake signal can be generated based on external signals, a target clock signal sent by a hysteresis clock generation module, and control commands sent by a control module. This handshake signal is then sent to a current source module, which generates a target electrical signal that satisfies the control commands based on the handshake signal. This target electrical signal is then sent to an asynchronous clock bias module to adjust the output voltage. This allows the hysteresis clock generation module to generate the target clock signal based on the adjusted output voltage and send the target clock signal to a signal generation module. Since the handshake signal is generated based on external signals, the target clock signal sent by the hysteresis clock generation module, and control commands sent by the control module (which can be generated based on actual needs), the handshake signal can generate a target electrical signal that satisfies the control commands. This allows for more precise adjustment of the clock delay, improving the accuracy of the delay adjustment and achieving linear delay adjustment. Attached Figure Description
[0050] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0051] Figure 1 This is a schematic diagram of the asynchronous clock generation device provided in the embodiments of this application;
[0052] Figure 2 This is a schematic diagram of the current source module in the asynchronous clock generation device provided in the embodiments of this application;
[0053] Figure 3 This is a schematic diagram of the structure of the state selection unit provided in the embodiments of this application;
[0054] Figure 4 This is a schematic diagram of the switch control signal in the state selection unit provided in the embodiments of this application;
[0055] Figure 5 This is a schematic diagram of the equivalent structure of the state selection unit when it is in operation, as provided in the embodiments of this application.
[0056] Figure 6 Another equivalent structural schematic diagram of the state selection unit provided in the embodiments of this application during operation;
[0057] Figure 7 This is a schematic diagram of the clock bias circuit in the asynchronous clock generation device provided in the embodiments of this application;
[0058] Figure 8 A schematic diagram of the hysteresis clock generation module in the asynchronous clock generation device provided in the embodiments of this application;
[0059] Figure 9 This is a schematic diagram of the signal generation module in the asynchronous clock generation device provided in the embodiments of this application;
[0060] Figure 10 This is a schematic diagram of the structure of an analog-to-digital converter provided in an embodiment of this application.
[0061] Icons: 10 - Asynchronous clock generator; 20 - Analog-to-digital converter circuit; 100 - Signal generation module; 110 - Comparator; 120 - NAND gate circuit; 200 - Current source module; 210 - Power supply selection unit; 220 - Status selection unit; 300 - Asynchronous clock bias module; 400 - Hysteresis clock generation module; 500 - Control module; M1 - First switch; M2 - Second switch; M3 - Third switch; M4 - Fourth switch; M5 - Fifth switch; M6 - Sixth switch; M7 - Seventh switch; M8 - Eighth switch; M9 - Ninth switch; M10 - Tenth switch Tube; S1 - First switch; S2 - Second switch; S3 - Third switch; S4 - Fourth switch; S5 - Fifth switch; C1 - First capacitor; C2 - Second capacitor; B1 - First current bias unit; B2 - Second current bias unit; B3 - Third current bias unit; VDD1 - First power supply terminal; VDD2 - Second power supply terminal; VDD3 - Third power supply terminal; VDD4 - Fourth power supply terminal; I1 - First module input terminal; I2 - Second module input terminal; O1 - First module output terminal; O2 - Second module output terminal; O3 - Third module output terminal; O4 - Clock output terminal; P - Pulse selection unit. Detailed Implementation
[0062] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0063] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0064] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0065] In the description of this application, it should be noted that the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0066] In successive approximation analog-to-digital converters, existing technologies typically use voltage-controlled delay circuits or capacitor charging / discharging circuits to achieve adjustable delays. However, since neither voltage-controlled delays nor capacitor charging / discharging circuits can linearly adjust the delay, it is often impossible to precisely adjust the delay to the desired amount during the adjustment process, resulting in low adjustment accuracy.
[0067] In addition, the delay generated by the delay unit is the same for each bit in the successive approximation process, and it is impossible to precisely control the delay of each bit. Therefore, the delay amount is often based on the bit with the longest delay. For bits that require shorter delay, the delay is often over-designed, resulting in wasted power consumption and reduced sampling rate of analog-to-digital converter.
[0068] To address the aforementioned problems in the prior art, this application provides an asynchronous clock generating device, the structural relationship of which will be explained in detail below.
[0069] Figure 1 Please refer to the schematic diagram of the asynchronous clock generation device provided in the embodiments of this application. Figure 1 An asynchronous clock generating device includes: a signal generating module 100, a current source module 200, an asynchronous clock biasing module 300, a hysteresis clock generating module 400, and a control module 500.
[0070] The signal generation module 100 is connected to the current source module 200, the hysteresis clock generation module 400, the control module 500, and external signals respectively. The signal generation module 100 is used to generate a handshake signal based on the external signals, the target clock signal sent by the hysteresis clock generation module 400, and the control command sent by the control module 500, and send the handshake signal to the current source module 200.
[0071] Specifically, the signal generation module 100 can be a circuit for generating handshake signals, which can be VALID (handshake mechanism) signals.
[0072] The current source module 200 is connected to the asynchronous clock bias module 300. The current source module 200 is used to generate a target electrical signal that meets the control command based on the handshake signal and send the target electrical signal to the asynchronous clock bias module 300.
[0073] Specifically, the current source module 200 can be a module with multiple selectable currents, which can select one or more selectable currents to be connected to the circuit based on the handshake signal, thereby generating the corresponding target electrical signal.
[0074] It should be noted that different current magnitudes from the connected current sources will result in different target electrical signals.
[0075] The asynchronous clock bias module 300 is connected to the hysteresis clock generation module 400. The asynchronous clock bias module 300 is used to adjust the output voltage according to the target electrical signal, and the hysteresis clock generation module 400 is used to generate a target clock signal based on the adjusted output voltage and send the target clock signal to the signal generation module 100.
[0076] Specifically, the asynchronous clock bias module 300 can be a circuit that generates a bias for the clock signal. The bias can be adjusted by selecting the pulse, thereby adjusting the output voltage based on the target electrical signal.
[0077] The hysteresis clock generation module 400 can specifically be a circuit that generates a clock signal with a certain hysteresis. It can perform hysteresis processing on the adjusted output voltage to generate and output the target clock signal.
[0078] It should be noted that the target clock signal output by the hysteresis clock generation module 400 can be input into the asynchronous clock bias module 300 and the signal generation module 100 respectively. The clock signal input into the asynchronous clock bias module 300 can realize pulse selection, and the clock signal input into the signal generation module 100 can be used as the sampling clock for generating the handshake signal.
[0079] Specifically, the control module 500 can generate control commands through pre-programming, and then send the control commands to the signal generation module 100 to generate handshake signals.
[0080] It should be noted that the overall working process of the above circuit is as follows:
[0081] First, the signal generation module 100 generates a handshake signal based on external signals, the target clock signal sent by the hysteresis clock generation module, and the control command sent by the control module. The handshake signal can be sent to the current source module. The current source module can obtain a high-precision current, which is the aforementioned target electrical signal, based on the handshake signal. The current source module can send the target electrical signal to the asynchronous clock bias module 300. The asynchronous clock bias module 300 adjusts the output voltage based on the target electrical signal. The hysteresis clock generation module 400 generates the target clock signal based on the adjusted output voltage and sends the target clock signal to the signal generation module 100.
[0082] In an asynchronous clock generation device provided in this application embodiment, a handshake signal can be generated based on an external signal, a target clock signal sent by a hysteresis clock generation module, and a control command sent by a control module. This handshake signal is then sent to a current source module, which generates a target electrical signal that satisfies the control command based on the handshake signal. This target electrical signal is then sent to an asynchronous clock bias module to adjust the output voltage. This allows the hysteresis clock generation module to generate the target clock signal based on the adjusted output voltage and send the target clock signal to a signal generation module. Since the handshake signal is generated based on an external signal, the target clock signal sent by the hysteresis clock generation module, and the control command sent by the control module (which can be generated based on actual needs), the handshake signal can generate a target electrical signal that satisfies the control command. This allows for more precise adjustment of the clock delay, improving the accuracy of the delay adjustment and achieving linear delay adjustment.
[0083] The specific structural relationship of the current source module in the asynchronous clock generation device provided in the embodiments of this application will be explained in detail below.
[0084] Figure 2 Please refer to the schematic diagram of the current source module in the asynchronous clock generation device provided in the embodiments of this application. Figure 2 The current source module 200 includes: a power selection unit 210 and a status selection unit 220; the power selection unit 210 includes multiple power supplies that can be connected.
[0085] The power selection unit 210 is connected to the signal generation module 100 and the state selection unit 220 respectively, and is used to turn on the target power supply under the action of the handshake signal. The target power supply is one or more power supplies that can be turned on. The state selection unit 220 is connected to the asynchronous clock bias module 300, and is used to switch the working state and generate the target electrical signal under the power supply of the target power supply.
[0086] It should be noted that the handshake signal may include the aforementioned VALID signal as well as CMPP (Comparator P, positive output of the comparator) and CMPN (Comparator N, negative output of the comparator) signals. The VALID signal can control the selection of the target power supply in the power selection unit 210; the CMPP and CMPN signals can be used to realize the state switching in the state selection unit 220.
[0087] Specifically, CMPP and CMPN signals can be analog signals obtained by sampling the positive input signal VIP and the negative input signal VIN. The positive input signal VIP and the negative input signal VIN are the aforementioned external signals.
[0088] Optionally, the power selection unit 210 includes: a plurality of selection switches; each selection switch is connected to a power source.
[0089] It should be noted that the power selection unit 210 can be configured with any number of selection switches. Each selection switch can be connected in series with a power supply. The opening and closing of each selection switch can be controlled by the VALID signal in the handshake signal mentioned above. For example, closing or opening the selection switch. The current provided by each power supply can be different. Connecting different power supplies can provide different currents.
[0090] In the asynchronous clock generation device provided in this application embodiment, the power selection unit can select the power supply that can be turned on through a handshake signal, thereby providing different currents to the state selection unit. Since the magnitude of each power supply that can be turned on is known, that is, a corresponding high-precision current can be provided according to actual needs, thereby obtaining a target electrical signal with high accuracy.
[0091] The specific structural connection relationship of the state selection unit provided in the embodiments of this application will be explained in detail below.
[0092] Figure 3 Please refer to the schematic diagram of the state selection unit provided in the embodiments of this application. Figure 3 The state selection unit 220 includes: a first switch M1, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a first module output terminal O1, and a second module output terminal O2.
[0093] Specifically, the first terminal of the first switch S1 is connected to the power selection unit 210, and the second terminal of the first switch S1 is connected to the third terminal of the first switching transistor M1; the first terminal of the second switch S2 is connected to the power selection unit 210, and the second terminal of the second switch S2 is connected to the first terminal of the first switching transistor M1; the first terminal of the third switch S3 is connected to the first terminal of the first switching transistor M1, and the second terminal of the third switch S3 is connected to the third terminal of the first switching transistor M1; the first terminal of the fourth switch S4 is connected to the first terminal of the first switching transistor M1, and the second terminal of the fourth switch S4 is connected to the first terminal of the fifth switch S5; the second terminal of the fifth switch S5 is connected to the first power supply terminal VDD1, and the second terminal of the first switching transistor M1 is grounded; the input of the first module output terminal O1 is connected to the second terminal of the fourth switch S4 and the first terminal of the fifth switch S5 respectively, and the output of the first module output terminal O1 is connected to the asynchronous clock bias module 300; the input of the second module output terminal O2 is connected to the third terminal of the first switching transistor M1, and the output of the second module output terminal O2 is connected to the asynchronous clock bias module 300.
[0094] It should be noted that during operation, the above-mentioned multiple switches can be divided into two groups. The first switch S1 and the fourth switch S4 are the first group of switches, and the second switch S2, the third switch S3 and the fifth switch S5 are the second group of switches. Each switch in each group is in the same open / closed state at the same time, and the first group of switches and the second group of switches are in different open / closed states at the same time.
[0095] Optionally, in order to switch the circuit state by controlling the on / off state of the two sets of switches during operation, in the first state, the first set of switches is open and the second set of switches is closed; in the second state, the second set of switches is open and the first set of switches is closed.
[0096] To facilitate the explanation of the switch's operating state, the timing relationship of the switch control signals in the state selection unit will be explained in detail below.
[0097] Figure 4 Please refer to the schematic diagram of the switch control signal in the state selection unit provided in the embodiments of this application. Figure 4 , Figure 4 It includes a first clock signal CK1 and a second clock signal CK2, where a low level indicates an open circuit and a high level indicates a closed circuit. The first clock signal CK1 controls the first group of switches, and the second clock signal CK2 controls the second group of switches.
[0098] according to Figure 4 The phase changes in the circuit indicate that each group of switches has two phases, and when the first group of switches is open, the second group of switches must be closed; correspondingly, when the first group of switches is closed, the second group of switches must be open.
[0099] The equivalent circuit relationship of the state switching unit under the two working states will be explained below.
[0100] Figure 5 For an equivalent structural diagram of the state selection unit provided in this application embodiment during operation, please refer to... Figure 5 , Figure 5 The circuit relationship shown is the first state mentioned above, which is... Figure 4 The timing state of phase 1.
[0101] In the first state, the output voltage of the first module output terminal O1 is the voltage of the first power supply terminal VDD1, and the voltage of the second module output terminal O2 is the voltage provided by the target current source connected in the power selection unit 210.
[0102] Figure 6 For another equivalent structural diagram of the state selection unit provided in the embodiments of this application during operation, please refer to... Figure 6 , Figure 6 The circuit relationship shown is the second state mentioned above, that is... Figure 4 The timing state of phase 2.
[0103] In the second state, the output voltage of the first module output terminal O1 is the voltage provided by the target current source connected in the power selection unit 210, and the voltage of the second module output terminal O2 is 0.
[0104] Optionally, the asynchronous clock bias module 300 includes multiple clock bias circuits; the input terminal of each clock bias circuit is connected to the output terminal of the current source module 200, and the output terminal of each clock bias circuit is connected to the input terminal of the hysteresis clock generation module 400.
[0105] Optionally, the number of clock bias circuits can be set according to actual needs, for example, it can be 10.
[0106] The following section will explain in detail the specific structural and connection relationships of the clock bias circuit provided in the embodiments of this application.
[0107] Figure 7 For a schematic diagram of the clock bias circuit in the asynchronous clock generation device provided in the embodiments of this application, please refer to... Figure 7 The clock bias circuit includes: a second switch M2, a third switch M3, a fourth switch M4, a first capacitor C1, a pulse selection unit P, a first module input terminal I1, a second module input terminal I2, and a third module output terminal O3.
[0108] Specifically, the first terminal of the second switch M2 is connected to the second power supply terminal VDD2, the second terminal of the second switch M2 is connected to the third module output terminal O3, and the third terminal of the second switch M2 is connected to the pulse selection unit P; the first terminal of the third switch M3 is connected to the third module output terminal O3, the second terminal of the third switch M3 is connected to the first module input terminal I1, and the third terminal of the third switch M3 is connected to the pulse selection unit P; the first terminal of the fourth switch M4 is grounded, the second terminal of the fourth switch M4 is connected to the first module input terminal I1, and the third terminal of the fourth switch M4 is connected to the second module input terminal I2; the first terminal of the first capacitor C1 is connected to the second module input terminal I2, and the second terminal of the first capacitor C1 is connected to the third module output terminal O3; the second module input terminal I2 is also connected to the third power supply terminal VDD3.
[0109] It should be noted that the second module input terminal I2 and the third power supply terminal VDD3 can be connected through the third current bias unit B3.
[0110] Optionally, the pulse selection unit P is a NOR gate circuit; the first input terminal of the NOR gate circuit is the enable terminal, and the second input terminal of the NOR gate circuit is the pulse signal selection terminal; the output terminal of the NOR gate circuit is connected to the third terminal of the second switch M2 and the third terminal of the third switch M3, respectively.
[0111] The enable terminal is at a low level, and the pulse signal selection terminal is initially at a high level. After sampling the required clock signal, it can become low. Since it is a NOR gate, it can be turned on when both are low, thereby turning on the third switch M3, and causing the output voltage of the third module output terminal O3 to start to decrease from the voltage provided by the second power supply terminal VDD2.
[0112] It should be noted that the clock bias circuit can change the operating state of the entire analog-to-digital converter. The clock frequency is adjustable in real time, and the pulse selection unit P can provide the operating time pulse. For example, for a 16-bit analog-to-digital converter, there are 16 consecutive pulses P<15:0>. For any one of these pulses P... In this case, when i takes different values from 0 to 15, the bias voltage generated by the clock bias circuit can be changed through the NOR gate, thereby enabling the real-time adjustment of each pulse width during the operation of the analog-to-digital converter.
[0113] In an asynchronous clock generation device provided in this application embodiment, the pulse selection unit in the clock bias circuit can specifically be a NOR gate circuit. During operation, the bias voltage of the circuit can be changed by enabling the NOR gate, thereby enabling real-time adjustment of the width of each pulse, that is, the clock frequency can be adjusted, thereby improving the flexibility and applicability of the circuit.
[0114] The following section will explain in detail the specific structural and connection relationships of the hysteresis clock generation module provided in the embodiments of this application.
[0115] Figure 8 For a schematic diagram of the hysteresis clock generation module in the asynchronous clock generation device provided in this application embodiment, please refer to... Figure 8 The hysteresis clock generation module 400 includes: a fifth switch M5, a sixth switch M6, a seventh switch M7, an eighth switch M8, a ninth switch M9, a tenth switch M10, a second capacitor C2, a first current bias unit B1, a second current bias unit B2, and a clock output terminal O4.
[0116] Among them, the first terminal of the fifth switch M5 is grounded, the second terminal of the fifth switch M5 is connected to the first terminal of the first current bias unit B1, and the third terminal of the fifth switch M5 is connected to the asynchronous clock bias module 300; the first terminal of the sixth switch M6 is connected to the fourth power supply terminal VDD4, the second terminal of the sixth switch M6 is connected to the first terminal of the second current bias unit B2, and the third terminal of the sixth switch M6 is connected to the third terminals of the ninth switch M9 and the tenth switch M10 respectively; the first terminal of the seventh switch M7 is connected to the fourth power supply terminal VDD4, the second terminal of the seventh switch M7 is connected to the third terminal of the sixth switch M6, and the third terminal of the seventh switch M7 is connected to the eighth switch M10 respectively. The third terminal of switch M8, the second terminal of the first current bias unit B1, and the second terminal of the second current bias unit B2 are connected; the first terminal of the eighth switch M8 is grounded, and the second terminal of the eighth switch M8 is connected to the third terminal of the sixth switch M6; the first terminal of the ninth switch M9 is connected to the fourth power supply terminal VDD4, and the second terminal of the ninth switch M9 is connected to the clock output terminal O4; the first terminal of the tenth switch M10 is grounded, and the second terminal of the tenth switch M10 is connected to the clock output terminal O4; the first terminal of the second capacitor C2 is connected to the second terminal of the second current bias unit B2, and the second terminal of the second capacitor C2 is grounded; the first terminal of the first current bias unit B1 is connected to the fourth power supply terminal VDD4.
[0117] Optionally, the input potential of the asynchronous clock bias module 300 is initially high, and the potential at the second terminal of the fifth switch M5 is pulled down to a low potential. When the input potential of the asynchronous clock bias module 300 begins to decrease, the potential at the second terminal of the fifth switch M5 begins to rise. After passing through a hysteresis circuit composed of the sixth switch M6, the seventh switch M7, and the eighth switch M8, as well as an inverter, a set of clock signals is generated. This clock signal is output through the clock output terminal O4, and this clock signal is the aforementioned target clock signal.
[0118] Optionally, the voltage change rate of the asynchronous clock bias module 300 can be adjusted by changing the size of the pulse selection unit P and the first capacitor C1 in the clock bias circuit, thereby changing the voltage change rate of the input voltage of the fifth switch M5, and thus changing the voltage rise rate of the second terminal of the fifth switch M5. After passing through the hysteresis circuit and the inverter, the width of the final clock is changed, thereby realizing the control of the delay of the output clock.
[0119] In the asynchronous clock generation device provided in this application embodiment, the delay of each bit can be precisely controlled by adjusting the pulse selection unit and the size of the first capacitor, avoiding excessive power consumption waste and thus improving the working efficiency of the device.
[0120] The following section will explain in detail the specific structural and connection relationships of the signal generation module provided in the embodiments of this application.
[0121] Figure 9 Please refer to the schematic diagram of the signal generation module in the asynchronous clock generation device provided in the embodiments of this application. Figure 9 The signal generation module 100 includes: a comparator 110 and a NAND gate circuit 120; the input terminal of the comparator 110 is connected to an external signal, the first output terminal of the comparator 110 is connected to the input terminal of the NAND gate circuit 120, the second output terminal of the comparator 110 is connected to the current source module 200, and the clock terminal of the comparator 110 is connected to the output terminal of the hysteresis clock generation module 400; the output terminal of the NAND gate circuit 120 is connected to the current source module 200.
[0122] It should be noted that comparator 110 can generate the aforementioned CMPP signal and CMPN signal through external signals, control signals sent by control module 500, and target clock signals generated by hysteresis clock generation module 400. Comparator 110 can send the CMPP signal and CMPN signal to NAND gate circuit 120 and current source module 200. NAND gate circuit 120 can obtain the aforementioned VALID signal based on the CMPP signal and CMPN signal, and then send the VALID signal to current source module 200.
[0123] The following section will explain in detail the specific structural and connection relationships of the analog-to-digital converters provided in the embodiments of this application.
[0124] Figure 10 Please refer to the schematic diagram of the analog-to-digital converter provided in the embodiments of this application. Figure 10 The analog-to-digital converter includes an asynchronous clock generator 10 and an analog-to-digital conversion circuit 20, the output of which is connected to the input of the asynchronous clock generator 10.
[0125] Optionally, the analog-to-digital converter 20 converts the analog signal into a digital signal and inputs the digital signal as an external signal into the asynchronous clock generator 10. The asynchronous clock generator 10 can adjust the pulse width of the clock to achieve adjustable delay in the circuit.
[0126] It should be noted that the analog-to-digital converter can specifically be a successive approximation analog-to-digital converter, and the above-mentioned asynchronous clock generation device can improve the sampling rate of the analog-to-digital converter.
[0127] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
[0128] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. An asynchronous clock generating device, characterized in that, include: The module includes a signal generation module, a current source module, an asynchronous clock bias module, a hysteresis clock generation module, and a control module. The signal generation module is connected to the current source module, the hysteresis clock generation module, the control module, and an external signal, respectively. The signal generation module is used to generate a handshake signal based on the external signal, the target clock signal sent by the hysteresis clock generation module, and the control command sent by the control module, and send the handshake signal to the current source module. The current source module is connected to the asynchronous clock bias module. The current source module is used to generate a target electrical signal that satisfies the control command based on the handshake signal, and send the target electrical signal to the asynchronous clock bias module. The asynchronous clock bias module is connected to the hysteresis clock generation module. The asynchronous clock bias module is used to adjust the output voltage according to the target electrical signal. The hysteresis clock generation module is used to generate a target clock signal based on the adjusted output voltage and send the target clock signal to the signal generation module. The current source module includes: a power selection unit and a state selection unit; the power selection unit includes multiple connectable power sources; the power selection unit is connected to the signal generation module and the state selection unit respectively, and is used to connect to a target power source under the action of the handshake signal, wherein the target power source is one or more of the connectable power sources; the state selection unit is connected to the asynchronous clock bias module, and the state selection unit is used to switch the working state and generate the target electrical signal under the power supply of the target power source; The asynchronous clock bias module includes multiple clock bias circuits; the input terminal of each clock bias circuit is connected to the output terminal of the current source module, and the output terminal of each clock bias circuit is connected to the input terminal of the hysteresis clock generation module. The clock bias circuit is used to generate a bias voltage, and the real-time adjustment of the pulse width is achieved through the bias voltage.
2. The asynchronous clock generating device as described in claim 1, characterized in that, The power selection unit includes: multiple selection switches; Each selector switch is connected to a power source.
3. The asynchronous clock generating device as described in claim 1, characterized in that, The state selection unit includes: a first switching transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first module output terminal, and a second module output terminal; The first end of the first switch is connected to the power selection unit, and the second end of the first switch is connected to the third end of the first switching transistor. The first end of the second switch is connected to the power selection unit, and the second end of the second switch is connected to the first end of the first switching transistor. The first end of the third switch is connected to the first end of the first switch tube, and the second end of the third switch is connected to the third end of the first switch tube. The first end of the fourth switch is connected to the first end of the first switch tube, and the second end of the fourth switch is connected to the first end of the fifth switch. The second end of the fifth switch is connected to the first power supply end, and the second end of the first switch tube is grounded. The inputs of the first module's output terminal are respectively connected to the second terminal of the fourth switch and the first terminal of the fifth switch, and the output of the first module's output terminal is connected to the asynchronous clock bias module; The input of the second module's output terminal is connected to the third terminal of the first switching transistor, and the output of the second module's output terminal is connected to the asynchronous clock bias module.
4. The asynchronous clock generating device as described in claim 3, characterized in that, The first switch and the fourth switch form a first group of switches, and the second switch, the third switch, and the fifth switch form a second group of switches. Each switch in each group is in the same on / off state at the same time, and the first group of switches and the second group of switches are in different on / off states at the same time.
5. The asynchronous clock generating device as described in claim 1, characterized in that, The clock bias circuit includes: a second switch, a third switch, a fourth switch, a first capacitor, a pulse selection unit, a first module input terminal, a second module input terminal, and a third module output terminal; The first end of the second switching transistor is connected to the second power supply terminal, the second end of the second switching transistor is connected to the output terminal of the third module, and the third end of the second switching transistor is connected to the pulse selection unit. The first end of the third switch is connected to the output end of the third module, the second end of the third switch is connected to the input end of the first module, and the third end of the third switch is connected to the pulse selection unit. The first terminal of the fourth switch is grounded, the second terminal of the fourth switch is connected to the input terminal of the first module, and the third terminal of the fourth switch is connected to the input terminal of the second module. The first end of the first capacitor is connected to the input terminal of the second module, and the second end of the first capacitor is connected to the output terminal of the third module. The input terminal of the second module is also connected to the third power supply terminal.
6. The asynchronous clock generating device as described in claim 5, characterized in that, The pulse selection unit is a NOR gate circuit; The first input terminal of the NOR gate is the enable terminal, and the second input terminal of the NOR gate is the pulse signal selection terminal; the output terminal of the NOR gate is connected to the third terminal of the second switch and the third terminal of the third switch, respectively.
7. The asynchronous clock generating device as described in claim 1, characterized in that, The hysteresis clock generation module includes: a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, a tenth switch, a second capacitor, a first current bias unit, a second current bias unit, and a clock output terminal; The first terminal of the fifth switch is grounded, the second terminal of the fifth switch is connected to the first terminal of the first current bias unit, and the third terminal of the fifth switch is connected to the asynchronous clock bias module. The first end of the sixth switch is connected to the fourth power supply end, the second end of the sixth switch is connected to the first end of the second current bias unit, and the third end of the sixth switch is connected to the third end of the ninth switch and the third end of the tenth switch, respectively. The first end of the seventh switch is connected to the fourth power supply terminal, the second end of the seventh switch is connected to the third end of the sixth switch, and the third end of the seventh switch is connected to the third end of the eighth switch, the second end of the first current bias unit, and the second end of the second current bias unit, respectively. The first terminal of the eighth switch is grounded, and the second terminal of the eighth switch is connected to the third terminal of the sixth switch. The first terminal of the ninth switch is connected to the fourth power supply terminal, and the second terminal of the ninth switch is connected to the clock output terminal. The first terminal of the tenth switch is grounded, and the second terminal of the tenth switch is connected to the clock output terminal; The first terminal of the second capacitor is connected to the second terminal of the second current bias unit, and the second terminal of the second capacitor is grounded. The first end of the first current bias unit is connected to the fourth power supply end.
8. The asynchronous clock generating device as described in claim 1, characterized in that, The signal generation module includes: a comparator and a NAND gate circuit; The input terminal of the comparator is connected to the external signal, the first output terminal of the comparator is connected to the input terminal of the NAND gate circuit, the second output terminal of the comparator is connected to the current source module, and the clock terminal of the comparator is connected to the output terminal of the hysteresis clock generation module. The output of the NAND gate is connected to the current source module.
9. An analog-to-digital converter, characterized in that, The analog-to-digital converter includes an asynchronous clock generating device as described in any one of claims 1-8 and an analog-to-digital conversion circuit, wherein the output terminal of the analog-to-digital conversion circuit is connected to the input terminal of the asynchronous clock generating device.