Interference signal generation method for UAV communication link based on binary phase coding

Abstract

The present invention discloses a method for generating an interference signal for a UAV communication link based on binary coding, comprising: generating a narrowband noise sequence in an FPGA, and generating a narrowband noise signal based on the narrowband noise sequence; wherein the narrowband noise sequence includes two noise sequences, a real part and an imaginary part; generating either noise sequence by: generating two pseudo-random sequences; performing nonlinear mapping processing of Sin and Log on the two pseudo-random sequences, respectively, and multiplying the results of the nonlinear mapping of Sin and Log to obtain a nonlinear mapping sequence; performing binary coding on the nonlinear mapping sequence according to the symbol level of the nonlinear mapping sequence to obtain a binary coding sequence; and performing frequency division processing on the binary coding sequence to obtain a noise sequence with narrowed bandwidth. The present invention solves the problem of insufficient output power in existing swept-frequency narrowband noise interference schemes caused by truncation of the digital filter output.

Description

Technical Field

[0001] The present invention belongs to the field of unmanned aerial vehicles (UAVs), and in particular relates to a method for generating interference signals for UAV communication links based on binary coding. Background Art

[0002] With the continuous innovation and rapid development of drone technology, drones have been widely used in aerial photography, meteorological detection, environmental mapping and other fields: industrial application-level drones can perform multi-scene inspection tasks, greatly improving work efficiency and safety performance; professional-level aerial photography drones can provide high-precision shooting from multiple angles, providing clearer photographic images; agricultural application-level drones can accurately sow on farmland, providing a more scientific agricultural planting method.

[0003] At the same time, the widespread use of drones has also brought new problems, among which the safety issues caused by indiscriminate and illegal drone flights are particularly prominent. Therefore, it is necessary to adopt drone countermeasure technology to counter indiscriminate and illegal drone flights.

[0004] The most effective and easily implemented drone countermeasure technology is jamming drone communication links. This technology uses jamming signals to disrupt drone communication links, forcing uncontrolled drones to return home or make an emergency landing, effectively addressing the safety issues caused by these unauthorized drones.

[0005] Common interference signal types include multi-tone interference, broadband noise interference, and swept narrowband noise interference. Multi-tone interference generates multiple single-frequency signals with a certain interval in the frequency domain, hoping to use these single-frequency signals to cover all operating frequencies within the entire frequency band of the drone communication link; broadband noise interference covers the entire frequency band of the drone communication link with white noise; and swept narrowband noise uses narrowband noise to scan the entire frequency band of the drone communication link.

[0006] However, since the total transmission power of the transmitter is fixed, and multi-tone interference and broadband noise interference need to cover the entire frequency band of the drone communication link, dispersing the total transmission power across the entire frequency band will result in the overall envelope amplitude of the interference signal being relatively low, resulting in poor interference effect.

[0007] Theoretically, the output power of narrowband noise is higher than that of multi-tone interference and broadband noise interference. When the sweep period and sweep frequency are set appropriately, the swept narrowband noise interference can achieve a better interference effect.

[0008] However, in the actual process of generating narrowband noise using an FPGA (Field-Programmable Gate Array), it is necessary to feed a digital broadband noise sequence into a digital filter for filtering to obtain a digital narrowband noise sequence. This narrowband noise sequence is then fed into a digital-to-analog converter (DA) to generate an analog narrowband noise signal. Because the output bit width of the digital filter is often many bits larger than that of the DA, the narrowband noise sequence needs to be truncated from the high bits before being fed into the DA. This truncation operation will result in an overall lower envelope amplitude of the narrowband noise signal output from the DA, reducing the power of the narrowband noise signal. As a result, the effect of frequency-sweep narrowband noise interference using the actual generated narrowband noise signal differs from the theoretical interference effect. Summary of the Invention

[0009] In order to solve the above problems existing in the prior art, the present invention provides a method for generating interference signals for UAV communication links based on binary coding.

[0010] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0011] A method for generating an interference signal for a UAV communication link based on binary phase coding comprises: generating a narrowband noise sequence in an FPGA, and generating a narrowband noise signal based on the narrowband noise sequence;

[0012] Wherein, the narrowband noise sequence includes two noise sequences, real part and imaginary part;

[0013] The generation method of any noise sequence includes:

[0014] Generate two pseudo-random sequences;

[0015] Performing nonlinear mapping processing of Sin and Log on the two pseudo-random sequences respectively, and multiplying the results of the nonlinear mapping processing of Sin and Log to obtain a nonlinear mapping sequence;

[0016] performing bi-phase coding on the nonlinear mapping sequence according to the symbol level of the nonlinear mapping sequence to obtain a bi-phase coded sequence;

[0017] Frequency division processing is performed on the two-phase code sequence to obtain a noise sequence with narrowed bandwidth.

[0018] In one embodiment, generating two pseudo-random sequences includes: generating the two pseudo-random sequences using two linear feedback shift registers constructed in an FPGA.

[0019] In one embodiment, performing nonlinear mapping processing of Sin and Log on the two pseudo-random sequences respectively includes: performing nonlinear mapping processing of Sin and Log on the two pseudo-random sequences respectively using a Sin-Log circuit constructed in an FPGA.

[0020] In one embodiment, performing bi-phase coding on the nonlinear mapping sequence according to the symbol level of the nonlinear mapping sequence to obtain a bi-phase coded sequence includes:

[0021] According to the symbol level of the nonlinear mapping sequence, the nonlinear mapping sequence is subjected to two-phase encoding by using a two-phase encoding circuit constructed in the FPGA to obtain a two-phase encoding sequence.

[0022] In one embodiment, the two-phase encoding circuit includes: a first comparator and a first multiplexer;

[0023] The first comparator is configured to compare the nonlinear mapping sequence with a 0 level symbol by symbol to obtain a sign positive / negative comparison result;

[0024] The first multiplexer is configured to output a maximum quantization value or a minimum quantization value as a two-phase code in response to the sign comparison result.

[0025] In one embodiment, the maximum quantization value is equal to 2 n-1 , the minimum quantization value is equal to -2 n ; n is equal to the bit width of the digital-to-analog converter;

[0026] The digital-to-analog converter is configured to perform digital-to-analog conversion on the narrowband noise sequence in the step of generating a narrowband noise signal based on the narrowband noise sequence.

[0027] In one embodiment, frequency division processing is performed on the two-phase code sequence to obtain a noise sequence with narrowed bandwidth, including:

[0028] Using a bandwidth conversion circuit constructed in the FPGA to perform bandwidth conversion on the two-phase code sequence to obtain a noise sequence with narrowed bandwidth;

[0029] The bandwidth conversion circuit receives the two-phase code sequence character by character in response to the clock and counts the clock at the same time; when the count value reaches a preset frequency division count value, the circuit outputs the symbol of the two-phase code sequence received in the current clock; when the count value does not reach the frequency division count value, the circuit retains the symbol of the two-phase code sequence output last time.

[0030] In one embodiment, the bandwidth conversion circuit includes: a frequency division counter, a second comparator, a D flip-flop, and a second multiplexer;

[0031] The frequency division counter is used to count the clock and output the count value;

[0032] The comparator is used to compare the count value with the frequency-divided count value and output a comparison result;

[0033] The D flip-flop has an input end connected to the output of the second multiplexer, and an output end connected to the input of the second multiplexer;

[0034] The second multiplexer receives the two-phase code sequence character by character in response to a clock; and selects to output a symbol of the two-phase code sequence or a symbol output by the D flip-flop according to the comparison result;

[0035] The frequency division counter is further configured to clear the count value when the comparison result indicates that the count value reaches the frequency division count value.

[0036] In one embodiment, the pseudo-random sequence is an n-level M sequence.

[0037] The present invention also provides an electronic device for implementing drone countermeasures, wherein the electronic device includes an FPGA, and the FPGA stores a computer program; when the FPGA executes the computer program, the FPGA implements the following method steps:

[0038] Generate two pseudo-random sequences;

[0039] Performing nonlinear mapping processing of Sin and Log on the two pseudo-random sequences respectively, and multiplying the results of the nonlinear mapping processing of Sin and Log to obtain a nonlinear mapping sequence;

[0040] performing bi-phase coding on the nonlinear mapping sequence according to the symbol level of the nonlinear mapping sequence to obtain a bi-phase coded sequence;

[0041] Frequency division processing is performed on the two-phase code sequence to obtain a noise sequence with narrowed bandwidth.

[0042] The present invention provides a method for generating interference signals for drone communication links based on binary coding. A narrowband noise sequence is obtained by performing nonlinear mapping, binary coding, and frequency division on a broadband pseudo-random sequence generated in an FPGA. This process eliminates the need for digital filtering to form the narrowband noise sequence, nor does it require truncation of the narrowband noise sequence. Consequently, the method achieves high narrowband output power, resolving the issue of insufficient output power in existing frequency-sweep narrowband noise interference schemes due to truncation of the digital filter output. Furthermore, because the bit rate of binary coding is equal to its bandwidth, the bandwidth of the narrowband noise can be flexibly adjusted by simply modifying the bit rate of the binary coding.

[0043] The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is a flowchart of generating a noise sequence in a method for generating an interference signal for a UAV communication link based on binary phase coding provided by an embodiment of the present invention;

[0045] Figure 2 is based on Figure 1 Schematic diagram of the circuit structure designed in FPGA for generating noise sequences according to the method shown;

[0046] Figure 3 yes Figure 2 A schematic diagram of the structure of the LFSR circuit in the circuit structure shown;

[0047] Figure 4 yes Figure 2 A schematic diagram of the structure of the Sin-Log circuit (sinusoidal AC circuit) in the circuit structure shown;

[0048] Figure 5 yes Figure 2 A schematic diagram of the structure of a two-phase encoding circuit in the circuit structure shown;

[0049] Figure 6 yes Figure 2 A schematic structural diagram of a bandwidth conversion circuit in the circuit structure shown;

[0050] Figure 7 is a spectrum comparison diagram of narrowband noise and broadband noise generated in an embodiment of the present invention;

[0051] Figure 8 FIG. 4 is a spectrum comparison diagram of the narrowband noise generated in the embodiment of the present invention and the narrowband noise generated by the existing method. DETAILED DESCRIPTION

[0052] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0053] In order to solve the problem of insufficient output power due to digital filter output truncation in existing frequency sweep narrowband noise interference solutions, an embodiment of the present invention provides a method for generating interference signals for UAV communication links based on binary coding. The method includes: generating a narrowband noise sequence in an FPGA, and generating a narrowband noise signal based on the narrowband noise sequence. The narrowband noise sequence includes two noise sequences, the real part and the imaginary part; the generation method of either noise sequence can be found in Figure 1 As shown, the following steps are included:

[0054] S10: Generate two pseudo-random sequences.

[0055] For details, see Figure 2 As shown in FIG, two linear feedback shift registers (LFSRs) built in an FPGA are used to generate two pseudo-random sequences, where the pseudo-random sequences are used to simulate white noise.

[0056] Among them, the characteristic polynomial of the pseudo-random sequence generated by LFSR is:

[0057] f(x)=c0+c1x+c2x 2 +L+c n x n =∑c i x i ;

[0058] Among them, x is the variable of the polynomial, c0~c n are the coefficients of each summation term, n is equal to the bit width of the digital-to-analog converter, i∈n. The digital-to-analog converter mentioned here is used to perform digital-to-analog conversion on the narrowband noise sequence in the above step of generating a narrowband noise signal based on the narrowband noise sequence.

[0059] Preferably, in order to maximize the randomness of the output noise, based on the above characteristic polynomial, the primitive polynomial of the n-th order LFSR is used to generate an n-level M sequence as the above pseudo-random sequence. The maximum number of cycles of the pseudo-random sequence obtained at this time is 2 n -1, that is, the repetition period of the current output pseudo-random sequence in the time domain is 2 n -1.

[0060] Among them, the structure of the linear feedback shift register is as follows Figure 3 As shown in the figure, clk is the FPGA clock, C0 to Cn-1 are n-bit random numbers input to the linear feedback shift register, D0 to Dn-1 are n-bit registers, and the modules between adjacent registers are XOR gates.

[0061] S20: performing nonlinear mapping processing of Sin and Log on the two pseudo-random sequences respectively, and multiplying the nonlinear mapping processing results of Sin and Log to obtain a nonlinear mapping sequence.

[0062] Specifically, the two LFSR pseudo-random sequences are f(x)1 and f(x)2, and they are mapped to Sin and Log respectively to obtain:

[0063] y1=sin(f(x)1),

[0064] y2=log2(f(x)2);

[0065] Then, multiply y1 and y2 to obtain a mixed nonlinear mapping sequence:

[0066] y o =sin(f(x)1)*log2(f(x)2).

[0067] It can be understood that after the nonlinear mapping process, in the time domain, the repetition period is increased by a factor of log2(y0)=log2(sin(f(x)1)*log2(f(x)2)).

[0068] In practical applications, see Figure 2 and Figure 4 As shown, a Sin-Log circuit built in an FPGA can be used to perform nonlinear Sin and Log mapping on two pseudo-random sequences, respectively. Sin_ROM represents the sine ROM instantiated in the FPGA, and Log_ROM represents the logarithmic ROM instantiated in the FPGA. The addresses of the two pseudo-random sequences generated in step S10 are assigned to the read addresses of the Sin_ROM and Log_ROM, respectively. The outputs of the Sin_ROM and Log_ROM are multiplied to obtain the nonlinear mapping sequence.

[0069] In step S20 , nonlinear mapping processing is performed on the two pseudo-random sequences respectively and then multiplied, so that the noise distribution in the frequency spectrum can be made more uniform.

[0070] S30: performing bi-phase coding on the nonlinear mapping sequence according to the symbol level of the nonlinear mapping sequence to obtain a bi-phase coded sequence.

[0071] For details, see Figure 2 As shown, according to the symbol level of the nonlinear mapping sequence, the nonlinear mapping sequence is bi-phase encoded using a bi-phase encoding circuit constructed in an FPGA to obtain a bi-phase encoded sequence.

[0072] For example, Figure 5 As shown, the two-phase encoding circuit may include: a first comparator ( Figure 5 comparaor) and the first multiplexer ( Figure 5 MUX in the .

[0073] The first comparator is used to compare the nonlinear mapping sequence with the 0 level symbol by symbol to obtain a sign positive / negative comparison result;

[0074] The first multiplexer is configured to output a maximum quantization value or a minimum quantization value as a binary code in response to a sign comparison result, thereby forming a binary code sequence.

[0075] Among them, the maximum quantization value is preferably equal to 2 n-1 , the minimum quantization value is preferably equal to -2 n, of course it is not limited to this; for example, the maximum quantization value is slightly less than 2 n-1 , the minimum quantization value is slightly greater than -2 n That's fine too.

[0076] S40: performing frequency division processing on the two-phase code sequence to obtain a noise sequence with narrowed bandwidth.

[0077] For details, see Figure 2 As shown, the bandwidth conversion circuit constructed in the FPGA is used to perform bandwidth conversion on the two-phase code sequence to obtain a noise sequence with narrowed bandwidth.

[0078] The bandwidth conversion circuit receives a two-phase code sequence character by character in response to a clock and simultaneously counts the clock; when the count value reaches a preset frequency division count value, the circuit outputs the symbol of the two-phase code sequence received in the current clock; when the count value does not reach the frequency division count value, the circuit retains the symbol of the two-phase code sequence output last time.

[0079] For example, Figure 6 As shown, the bandwidth conversion circuit may include: a frequency division counter, a second comparator ( Figure 6 comparator in), D flip-flop, and the second multiplexer ( Figure 6 MUX in the .

[0080] Among them, the frequency division counter is used to count the clock and output the count value cal. The internal structure of the frequency division counter is shown in Figure 6 As shown in the dotted box, it includes an adder and an n-bit register.

[0081] The comparator is used to compare the count value cal with the divided count value div and output the comparison result.

[0082] A D flip-flop, wherein the input end is connected to the output of the second multiplexer, and the output end is connected to the input of the second multiplexer.

[0083] The second multiplexer receives the two-phase code sequence character by character in response to the clock clk; selects to output the symbol of the two-phase code sequence or the symbol output by the D flip-flop according to the comparison result output by the comparator;

[0084] The frequency division counter is further used to clear the count value cal when the comparison result indicates that the count value cal reaches the frequency division count value div.

[0085] It can be understood that the code rate of the two-phase code is its signal bandwidth; therefore, the noise bandwidth B corresponding to the two-phase code sequence before frequency division is B = f s , f s is the code rate of the two-phase coding sequence. The noise bandwidth corresponding to the noise sequence obtained after frequency division processing is It can be seen from this that by setting different division count values ​​div in the FPGA, the noise bandwidth can be flexibly adjusted.

[0086] The beneficial effects of the embodiments of the present invention are further illustrated below through simulation experiments.

[0087] Simulation conditions: f s =125MHz, n=16.

[0088] Experimental content: Steps S10 to S40 are performed in sequence under the above simulation conditions.

[0089] (1) Generate broadband noise based on the two-phase code sequence obtained in step S30, capture 2 20 Perform FFT (Fast Fourier Transform) on the point data;

[0090] (2) The broadband noise is filtered by FIR (Finite Impulse Response, finite length unit impulse response), and the FIR filter output is truncated to the upper 16 bits, and 2 20 Perform FFT on point data;

[0091] (3) Generate narrowband noise based on the noise sequence obtained in step S40, and also capture 2 20 Perform FFT on the data of the points.

[0092] Experimental results analysis:

[0093] See also Figure 6 As shown in the figure, the "broadband noise" corresponds to the FFT result in the above experiment (1), and the "narrowband noise" corresponds to the FFT result in the above experiment (3). By comparison, it can be seen that after normalizing the "broadband noise" and "narrowband noise" according to the maximum value of the two, the frequency domain power of the effective bandwidth of the "narrowband noise" is higher than that of the "broadband noise", and the difference between the maximum values ​​is 0.1074dB, which is in line with the rule that the effective bandwidth becomes narrower and the output power becomes larger.

[0094] See also Figure 7 As shown, "narrowband noise (present invention)" corresponds to the FFT result in the above experiment (3), and "narrowband noise (truncated)" corresponds to the FFT result in the above experiment (2). By comparison, it can be seen that after normalizing the narrowband noise output by FIR filtering truncation and the narrowband noise generated in the embodiment of the present invention according to the maximum value of the two, the frequency domain power of the effective bandwidth of the narrowband noise generated in the embodiment of the present invention is higher than that of the narrowband noise output by FIR filtering truncation, and the difference between the maximum values ​​is 0.2934dB, indicating that the embodiment of the present invention greatly improves the output power of the narrowband noise.

[0095] In the interference signal generation method for drone communication links based on two-phase coding provided by an embodiment of the present invention, a narrowband noise sequence is obtained by performing nonlinear mapping, two-phase coding, and frequency division processing on a wideband pseudo-random sequence generated in an FPGA. In this process, there is no need to use digital filtering to form the narrowband noise sequence, nor is there any need to truncate the narrowband noise sequence. Therefore, it has a high narrowband output power, solving the problem of insufficient output power caused by truncation of the digital filter output in existing frequency-sweeping narrowband noise interference schemes. In addition, because the bit rate of the two-phase coding is equal to its bandwidth, the bandwidth of the narrowband noise can be flexibly adjusted by simply modifying the bit rate of the two-phase coding.

[0096] Based on the same inventive concept, an embodiment of the present invention further provides an electronic device for implementing drone countermeasures. The electronic device includes an FPGA, and a computer program is stored in the FPGA. When the FPGA executes the computer program, the following method steps are implemented:

[0097] (1) Generate two pseudo-random sequences;

[0098] (2) Perform nonlinear mapping of Sin and Log on the two pseudo-random sequences respectively, and multiply the results of the nonlinear mapping of Sin and Log to obtain a nonlinear mapping sequence;

[0099] (3) performing two-phase coding on the nonlinear mapping sequence according to the symbol level of the nonlinear mapping sequence to obtain a two-phase coded sequence;

[0100] (4) Perform frequency division processing on the two-phase coded sequence to obtain a noise sequence with narrowed bandwidth.

[0101] Optionally, generating two pseudo-random sequences includes: generating the two pseudo-random sequences using two linear feedback shift registers constructed in an FPGA.

[0102] Optionally, performing nonlinear mapping processing of Sin and Log on the two pseudo-random sequences respectively includes: performing nonlinear mapping processing of Sin and Log on the two pseudo-random sequences respectively using a Sin-Log circuit constructed in an FPGA.

[0103] Optionally, performing two-phase coding on the nonlinear mapping sequence according to the symbol level of the nonlinear mapping sequence to obtain a two-phase coded sequence includes:

[0104] According to the symbol level of the nonlinear mapping sequence, a two-phase encoding circuit constructed in an FPGA is used to perform two-phase encoding on the nonlinear mapping sequence to obtain a two-phase encoding sequence.

[0105] Optionally, the two-phase encoding circuit includes: a first comparator and a first multiplexer;

[0106] A first comparator is used to compare the nonlinear mapping sequence with the 0 level symbol by symbol to obtain a sign positive / negative comparison result;

[0107] The first multiplexer is configured to output a maximum quantization value or a minimum quantization value as a binary code in response to a sign comparison result.

[0108] Optionally, the maximum quantization value is equal to 2 n-1 , the minimum quantization value is -2 n ; n is equal to the bit width of the digital-to-analog converter;

[0109] The digital-to-analog converter is used to perform digital-to-analog conversion on the narrowband noise sequence in the step of generating the narrowband noise signal based on the narrowband noise sequence.

[0110] Optionally, frequency division processing is performed on the two-phase code sequence to obtain a noise sequence with narrowed bandwidth, including:

[0111] The bandwidth conversion circuit built in FPGA is used to convert the bandwidth of the two-phase code sequence to obtain a noise sequence with narrowed bandwidth.

[0112] The bandwidth conversion circuit receives a two-phase code sequence character by character in response to a clock and simultaneously counts the clock; when the count value reaches a preset frequency division count value, the circuit outputs the symbol of the two-phase code sequence received in the current clock; when the count value does not reach the frequency division count value, the circuit maintains the symbol of the two-phase code sequence output last time.

[0113] Optionally, the bandwidth conversion circuit includes: a frequency division counter, a second comparator, a D flip-flop, and a second multiplexer;

[0114] A frequency division counter is used to count the clock and output the count value;

[0115] A comparator, used to compare the count value with the frequency-divided count value and output a comparison result;

[0116] a D flip-flop, an input end of which is connected to the output of the second multiplexer, and an output end of which is connected to the input of the second multiplexer;

[0117] The second multiplexer receives the two-phase code sequence character by character in response to the clock; and selects to output the symbol of the two-phase code sequence or the symbol output by the D flip-flop according to the comparison result;

[0118] The frequency division counter is further used to clear the count value when the comparison result indicates that the count value reaches the frequency division count value.

[0119] Optionally, the pseudo-random sequence is an n-level M sequence.

[0120] It should be noted that, for the electronic device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0121] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0122] In the description of this specification, the reference terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" mean that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0123] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the disclosed embodiments by viewing the drawings and the disclosed content.

[0124] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A method for generating interference signals for UAV communication links based on binary coding, characterized in that: include: generating a narrowband noise sequence in the FPGA, and generating a narrowband noise signal based on the narrowband noise sequence; Wherein, the narrowband noise sequence includes two noise sequences, real part and imaginary part; The generation method of any noise sequence includes: Generate two pseudo-random sequences; Performing nonlinear mapping processing of Sin and Log on the two pseudo-random sequences respectively, and multiplying the results of the nonlinear mapping processing of Sin and Log to obtain a nonlinear mapping sequence; performing bi-phase coding on the nonlinear mapping sequence according to the symbol level of the nonlinear mapping sequence to obtain a bi-phase coded sequence; Frequency division processing is performed on the two-phase code sequence to obtain a noise sequence with narrowed bandwidth.

2. The interference signal generation method according to claim 1, characterized in that Generating two pseudo-random sequences includes: generating the two pseudo-random sequences by using two linear feedback shift registers constructed in an FPGA.

3. The interference signal generation method according to claim 1, characterized in that The two pseudo-random sequences are respectively subjected to nonlinear mapping processing of Sin and Log, comprising: utilizing a Sin-Log circuit constructed in an FPGA to respectively conduct nonlinear mapping processing of Sin and Log on the two pseudo-random sequences.

4. The interference signal generation method according to claim 1, characterized in that Performing two-phase coding on the nonlinear mapping sequence according to the symbol level of the nonlinear mapping sequence to obtain a two-phase coded sequence, including: According to the symbol level of the nonlinear mapping sequence, the nonlinear mapping sequence is subjected to two-phase encoding by using a two-phase encoding circuit constructed in the FPGA to obtain a two-phase encoding sequence.

5. The interference signal generating method according to claim 4, characterized in that: The two-phase encoding circuit includes: a first comparator and a first multiplexer; The first comparator is configured to compare the nonlinear mapping sequence with a 0 level symbol by symbol to obtain a sign positive / negative comparison result; The first multiplexer is configured to output a maximum quantization value or a minimum quantization value as a two-phase code in response to the sign comparison result.

6. The interference signal generating method according to claim 5, characterized in that: The maximum quantization value is equal to 2 n-1 , the minimum quantization value is equal to -2 n ; n is equal to the bit width of the digital-to-analog converter; The digital-to-analog converter is configured to perform digital-to-analog conversion on the narrowband noise sequence in the step of generating a narrowband noise signal based on the narrowband noise sequence.

7. The interference signal generating method according to claim 1, characterized in that: Performing frequency division processing on the two-phase code sequence to obtain a noise sequence with narrowed bandwidth includes: Using a bandwidth conversion circuit constructed in the FPGA to perform bandwidth conversion on the two-phase code sequence to obtain a noise sequence with narrowed bandwidth; The bandwidth conversion circuit receives the two-phase code sequence character by character in response to the clock and counts the clock at the same time; when the count value reaches a preset frequency division count value, the circuit outputs the symbol of the two-phase code sequence received in the current clock; when the count value does not reach the frequency division count value, the circuit retains the symbol of the two-phase code sequence output last time.

8. The interference signal generating method according to claim 7, characterized in that: The bandwidth conversion circuit includes: a frequency division counter, a second comparator, a D flip-flop and a second multiplexer; The frequency division counter is used to count the clock and output the count value; The comparator is used to compare the count value with the frequency-divided count value and output a comparison result; The D flip-flop has an input end connected to the output of the second multiplexer, and an output end connected to the input of the second multiplexer; The second multiplexer receives the two-phase code sequence character by character in response to a clock; and selects to output a symbol of the two-phase code sequence or a symbol output by the D flip-flop according to the comparison result; The frequency division counter is further configured to clear the count value when the comparison result indicates that the count value reaches the frequency division count value.

9. The interference signal generating method according to claim 6, characterized in that: The pseudo-random sequence is an n-level M sequence.

10. An electronic device for implementing drone countermeasures, characterized in that: The electronic device includes an FPGA, and the FPGA stores a computer program; when the FPGA executes the computer program, the following method steps are implemented: Generate two pseudo-random sequences; Performing nonlinear mapping processing of Sin and Log on the two pseudo-random sequences respectively, and multiplying the results of the nonlinear mapping processing of Sin and Log to obtain a nonlinear mapping sequence; performing bi-phase coding on the nonlinear mapping sequence according to the symbol level of the nonlinear mapping sequence to obtain a bi-phase coded sequence; Frequency division processing is performed on the two-phase code sequence to obtain a noise sequence with narrowed bandwidth.

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